TWI550822B - Apparatus and package with localized high density substrate routing and method of making same - Google Patents

Description

Device and package with localized high-density substrate winding and manufacturing method thereof

This case is roughly related to the electronic chip architecture.

A semiconductor device such as an electronic device may include a substrate winding having a lower density than some of the wafers attached to the substrate. Some devices may include complex winding schemes, particularly where the attached wafer contains a higher density winding than the windings in the substrate.

100‧‧‧ Equipment

102A‧‧‧Media

102B‧‧‧Media

104‧‧‧High-density interconnect components

106‧‧‧Electrical components

108‧‧‧ dielectric layer

110A‧‧‧First circuit component

110B‧‧‧Second circuit components

112‧‧‧ Conductive adhesive

114A‧‧‧ grain

114B‧‧‧ grain

116‧‧‧ Conductive adhesive

118‧‧‧Low-density interconnect components

120‧‧‧ busbar

122‧‧‧Adhesive layer

224‧‧‧Electrical mat

226‧‧‧ top surface

End of 238A‧‧

End of 238B‧‧‧

328‧‧‧Low density interconnect pads

332‧‧‧Electrical mat

334‧‧‧Adhesive layer

336‧‧‧Metal pad

500‧‧‧Electronic devices

502‧‧‧System Bus

510‧‧‧Electronic components

512‧‧‧ processor

514‧‧‧Communication circuit

516‧‧‧ display device

518‧‧‧ Horn

520‧‧‧External memory

522‧‧‧ main memory

524‧‧‧hard disk drive

526‧‧‧Removable media

530‧‧‧Keyboard/Controller

1 shows an example of an apparatus including a local high density substrate winding in accordance with one or more embodiments.

2 is an illustration of a high density interconnect element in accordance with one or more embodiments.

3 shows an example of another device including a local high density substrate winding in accordance with one or more embodiments.

Figure 4 shows the fabrication with a bureau in accordance with one or more embodiments A technical example of a device for winding a high-density substrate.

FIG. 5 shows an example of an electronic device in accordance with one or more embodiments.

SUMMARY OF THE INVENTION AND EMBODIMENT

The following description and the drawings are sufficient to show specific embodiments that may be practiced by those skilled in the art. Other embodiments may incorporate structural, logical, electrical, procedural or other changes. Portions and features of some embodiments may be included or substituted for those embodiments in other embodiments. The embodiments described in the scope of the claims contain all available equivalents of these claims.

Embodiments of systems and methods for localizing high density substrate windings are generally described herein. In one or more embodiments, an apparatus includes a medium, first and second circuit elements, one or more interconnect elements, and a dielectric layer. The medium can contain low density windings. The interconnecting component can be embedded in the medium and can include a plurality of electrically conductive members, and a conductive member of the electrically conductive members can be electrically coupled to the first and second circuit components. The interconnect element can include a high density winding therein. The dielectric layer can be on the interconnect element, and the dielectric layer can include the first and second circuit elements therethrough.

A substrate solution can be used to provide a wafer to wafer interconnect. The I/O (input/output) density in the package substrate can be determined by the minimum trajectory and spatial size of the substrate. The minimum trace and space size can be limited by the resolution of the lithography and plating processes used in the substrate process. This limit can be a function of the economic cost of completing the resolution. In a multi-wafer substrate The wire density can be about one hundred (100) times lower than the wire density in the wafer level winding process. Problems with the use of lower wire densities can include larger and reduced system and power performance of the substrate's dedicated I/O.

A problem with previous multi-wafer package substrates may be that they cannot be wound on the substrate using wafer level winding density in a cost effective or convenient manner. A solution to this problem may include the use of high density interconnect elements (eg, interconnected dies or interconnected wafers) that include wafer level windings (eg, high density windings) embedded in a medium (eg, a substrate). This solution can provide localized high-density winding components that allow for the creation of localized high-bandwidth (eg, density) wafer-to-wafer interconnects or the ability to modify package designs and the ability to benefit from high-bandwidth wafer-to-wafer interconnects. There is no need to make major changes to the process. This solution also provides high-density interconnects only in areas where high-density interconnects are useful, thus allowing less expensive lithography and electroplating processes to be used in conventional package windings (eg, low-density windings) that are not used in the substrate or Areas where high density interconnections are not desired. This solution may also provide dimensions when the interconnect element is built into the N-1 layer (eg, a layer below the upper layer of the substrate (the N layer)) or below when placing the high density interconnect component The change on. In embodiments that include more than one interconnect element, the alignment of one interconnect element can be independent of the other interconnect element. Embodiments comprising a high density interconnect built into the top layer of the substrate can unify the package core windings and the high frequency wide interconnect windings onto a single imaging bump bar on the substrate for subsequent wafer attachment. At the same time, this solution can also provide most wafers for different windings and may be more economical. The high frequency wide interconnect winding can be isolated to a portion of the wafer where the entity will be high The bandwidth interconnect is coupled to or near the location, thus leaving the remaining wafer space for low density winding. Variations in the position of the circuit components can be tolerated by including pads on the interconnect elements that are sized or shaped to be larger than circuit elements (e.g., conductive vias).

FIG. 1 shows an example of a device 100 that may include a local high density substrate winding. Apparatus 100 can include a medium 102A, one or more high density interconnect elements 104, an optional dielectric layer 108, one or more first circuit elements 110A, one or more second circuit elements 110B, an optional adhesion layer 122, or One or more grains 114A-B.

A low density interconnect winding can be included in the medium 102A. The medium 102A can be a substrate, such as a semiconductor substrate (eg, germanium, gallium, indium, germanium or combinations or variations thereof, and other substrates), one or more insulating layers, such as glass-reinforced epoxy, eg, FR-4 , polytetrafluoroethylene (Teflon), copper-paper reinforced epoxy resin (CEM-3), phenol-glass (G3), paper-phenols (FR-1 or FR-2), polyester-glass ( CEM-5), any other dielectric material, such as glass or a combination of, for example, those that can be used in printed circuit boards (PCBs). The medium 102A can be completed using a bumpless build-up layer process (BBUL) or other techniques for creating the medium 102A. The BBUL process includes one or more build-up layers formed under a component, such as high density interconnect component 104 or die 114. For example, a micro-via formation process for laser drilling can also form a connection between the build-up layer and the die or die bond pads. The build-up layer can be formed using high density accumulation patterning techniques. The die 114 or majority of the die 114 and the high density interconnect component 104 can be embedded within the substrate for electrical connection using BBUL or other processes.

The high density interconnect element 104 can include a plurality of conductive members 106 that are configured, placed, formed, or positioned therein. The conductive members 106 can be positioned within the high density interconnect elements 104, and the gap between the conductive members 106 can be less than, for example, by conventional substrate winding techniques using die winding techniques (eg, as small as about 100 points) One) to create a high density interconnect element 104 (eg, the high density interconnect element 104 can include a high density substrate winding therein). The high density interconnect element 104 can be a semiconductor die, such as a germanium die. The high density interconnect element 104 can comprise at least one layer of glass, ceramic, or organic material.

The high density interconnect element 104 can be positioned one layer below the surface within the medium 102A (eg, N-1 layer or less), or can be positioned on the top surface (eg, N layer) of the medium 102A, such as in FIG. Show.

The high density interconnect element 104 can include a conductive pad 224 positioned on the high density interconnect element 104 or at least partially within the high density interconnect element 104, for example, on the top surface 226 of the high density interconnect element 104 or At least partially below the top surface 226 of the high density interconnect element 104, as shown in FIG. Conductive pad 224 can be electrically coupled between conductive member 106 and circuit elements 110A-B, such as shown in FIG. Conductive pad 224 may comprise a conductive metal such as copper, gold, silver, aluminum, zinc, nickel, brass, bronze, iron, and the like. The conductive pads 224 (eg, high density conductive pads 224) may have a footprint that is larger than the corresponding footprint of the circuit component 110. This architecture allows for dimensional changes in manufacturing or when positioning the high density interconnect element 104 within the medium 102. The conductive pads 224 may comprise footprints that are circular, square, rectangular, triangular, or combinations thereof, and the like. The footprint of conductive pads 224 may be between about 175μm ² to 10000μm ^2, such as a conductive pad 224 may comprise the footprint size of 50μm, such as a conductive pad 224 having a square footprint of about 2500μm ^2, or with a footprint of about 1963μm ² Round shape. In some embodiments, the conductive pads 224 can comprise a footprint of between about 1900 μm ² and 2550 μm ² .

Dielectric layer 108 can be positioned over high density interconnect element 104 (the lower boundary of dielectric layer 108 is represented by a horizontal dashed line in medium 102A). Dielectric layer 108 can include circuit elements 110 therethrough. The inclusion of the dielectric layer 108 can assist in allowing dimensional changes in the high density interconnect element 104 to be placed, built, or positioned at least partially within or over the medium 102A. Dielectric layer 108 may comprise an oxide, or other material, such as an insulating material.

The high density interconnect element 104 can include interconnect circuitry, such as first and second circuit components 110A-B, which can be high density circuit components 110. Circuit elements 110A-B can be configured to be electrically coupled to conductive member 106, for example, by electrically coupling high density conductive pads 224 of die 114A-B to high density conductive pads 224 of high density interconnect element 104. Circuit elements 110A-B can be conductive vias. The circuit component 110 can comprise a footprint of between about 175 μm ² and 3600 μm ² . For example, the circuit component 110 can comprise a footprint size of about 30 μm, such as the circuit component 110 being substantially circular, having a footprint of about 707 μm ² , or substantially Square, with a footprint of 900 μm ² . In some embodiments, circuit component 110 can comprise a footprint of between about 600 μm ² and 1000 μm ² .

One or more of the dies 114A-B can be positioned over the medium 102. The die 114A-B can be electrically coupled to the circuit components 110A-B through a conductive adhesive 112, such as solder, tape, glue or other conductive adhesive. The conductive adhesive 112 can be electrically coupled, for example, by electrically coupling the high-density conductive pad 224A on the first die 114A or at least in the second die 114B or at least the conductive pad 224B therein. A die 114A to a second die 114B. The first or second die 114A-B can be logic, memory, central processing unit (CPU), graphics, radio, or any other type of die or package. The conductive pads 224 of the high density interconnect elements 104 can be positioned between the circuit elements 110 and the ends 238A-B of the conductive members 106.

The first and second dies 114A-B can include low density interconnect pads 328, such as for power, ground, or other electrical coupling or connection thereto. The low density interconnect pads 328 can be electrically coupled to the busbars 120, such as power, ground, or data busses, for example, through low density interconnect elements 118. The low density interconnect pads 328 can be electrically coupled to the conductive pads 332, for example, via the conductive adhesive 116. Conductive adhesive 116 can be solder (eg, solder paste), electroplated, or microspheres, such as microspheres that are architected for flip chip interconnects, such as controlled crash wafer bonding (C4) interconnects.

Adhesive layer 122 can operate to prevent conductive adhesive 116 from bridging between the conductors, for example, to help prevent short circuits. Adhesive layer 122 can be a solder resist (eg, a solder mask), a conductive adhesive, a vermiculite-filled underfill, or other type of insulator that can operate to prevent bridging between the conductors. Adhesive layer 122 can be positioned over dielectric layer 108 and then selectively Removed to at least partially expose circuit component 110 or conductive pad 332 or 224; or, adhesive layer 122 may be selectively positioned over dielectric layer 108 such that, for example, conductive elements of circuit component 110 are not all adhesive layers Covered by 122. The adhesive layer 122 may be distributed at or near the edge of the die 114 and may be, for example, by using air pressure or capillary action, for example, at least partially filling the space between the conductors under the die 114, in the die Flowing under 114.

FIG. 2 shows an example of dimensional variations in the placement of the first or second circuit component 110 or the high density interconnect component 104. By including a high density conductive pad 224 having a footprint greater than the footprint of the circuit component 110 to be coupled thereto, the placement of the circuit component 110, the high density conductive pad 224, and the formation of the circuit component 110 therein can be tolerated. The error of the hole, or the error of placing the high density interconnect element 104.

The high density interconnect element 104 can be electrically coupled to more than two dies 114 at the same time, for example, CPU crystals coupled to one or more of memory, logic, graphics, other CPU dies, or other types of dies. grain.

3 shows an example of a device 300 that can include a high density interconnect element 104 on the top layer of media 102B. In this embodiment, the high density interconnect component 104 can be secured to the location by an adhesive layer 334, such as a solder layer. Adhesive layer 334 can secure high density interconnect component 104 to an optional metal pad 336, such as a copper pad, or directly to media 102B. The metal pad 336 can be actuated to scatter the laser through the stop layer of the adhesive layer 334, for example, to stop the laser from penetrating the medium 102B. This architecture may allow for better control over the placement or attachment of the high density interconnect elements 104.

FIG. 4 shows an example of a technique 400 for making a device that can include a high density interconnect element 104. At 402, the high density interconnect element 104 can be built into the medium 102. The high density interconnect element 104 can include one or more conductive members 106. At 404, the dielectric layer 108 can be positioned over the high density interconnect element 104. At 406, circuit component 110 can be electrically coupled to high density interconnect component 104, for example, to electrically couple two circuit components 110A-B to each other.

An electronic device example using one or more high density interconnect elements 104 is included to illustrate a device application example of the present application. FIG. 5 shows an example of an electronic device 500 incorporating one or more high density interconnect elements 104. The electronic device 500 is merely an example of a device in which embodiments of the invention may be used. Examples of electronic device 500 may include, but are not limited to, personal computers, tablets, supercomputers, servers, telecommunications switches, routers, mobile phones, personal data assistants, MP3 or other digital music players, radios, and the like. In this example, electronic device 500 includes a data processing system that includes a system bus 502 to couple various components of the system. System bus 502 provides a communication link between the various components of electronic device 500 and can be implemented as a single bus, a combination of bus bars, or in any other suitable manner.

Electronic component 510 is coupled to system bus 502. Electronic component 510 can include circuitry or a combination of circuits. In an embodiment, electronic component 510 includes a processor 512 that can be any type. As used herein, "processor" means any type of computing circuit such as, but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISG) microprocessor. , Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Character (VLIW) microprocessor, graphics processor, digital signal processor (DSP), multi-core processor, or any other type of processor or processing circuit .

Other types of circuitry that may be included in electronic component 510 are custom circuits, special application integrated circuits (ASICs), or the like, for example, for wireless devices such as mobile phones, pagers, personal data assistants, mobile computers. One or more circuits (e.g., communication circuit 514) of a two-way radio and similar electronic system. The IC can perform any other type of function.

The electronic device 500 can include external memory 520, which can then include one or more memory components suitable for a particular application, such as main memory 522 in the form of random access memory (RAM), one or more hard drives. Machine 524, and/or one or more drivers that process removable media 526, such as compact discs (CDs), digital video discs (DVDs), and the like.

The electronic device 500 can also include a display device 516, one or more speakers 518, and a keyboard and/or controller 530, which can include a mouse, a trackball, a touch screen, a voice recognition device, or any other system that can be used. The device inputs information into the electronic device 500 and receives information from there.

Other points and examples

In Example 1, an apparatus includes a medium having a low density interconnect winding therein.

In Example 2, the device of Example 1 includes a first circuit component and a second circuit component.

In Example 3, the device of at least one of Examples 1 to 2 includes an interconnection element.

In Example 4, the interconnection elements of at least one of Examples 1 to 3 are embedded in the medium.

In Example 5, the interconnection element of at least one of Examples 1 to 4 includes a high density substrate winding therein.

In Example 6, the interconnection element of at least one of Examples 1 to 5 includes a plurality of conductive members.

In Example 7, the conductive members of the plurality of conductive members of at least one of Examples 1 to 6 are electrically coupled to the first circuit element and the second circuit element.

In Example 8, the apparatus of at least one of Examples 1 to 7 includes a dielectric layer over the interconnect die, the dielectric layer including first and second circuit elements therethrough.

In Example 9, the medium of at least one of Examples 1 to 8 is a substrate.

In Example 10, the medium of at least one of Examples 1 to 9 is a semiconductor (for example, germanium) substrate.

In Example 11, the interconnection elements of at least one of Examples 1 to 10 are interconnected dies.

In Example 12, the apparatus of at least one of Examples 1 to 11 includes the first die.

In Example 13, the first die of at least one of Examples 1 through 12 is electrically coupled to the first circuit component.

In Example 14, the first die of at least one of Examples 1 to 13 is disposed on the medium.

In Example 15, the apparatus of at least one of Examples 1 to 14 includes the second die.

In Example 16, the second die of at least one of Examples 1 through 15 is electrically coupled to the second circuit component.

In Example 17, the second die of at least one of Examples 1 to 16 is disposed on the medium.

In Example 18, the first die of at least one of Examples 1 to 17 is a logic die.

In Example 19, the second crystal grains of at least one of Examples 1 to 18 are memory crystal grains.

In Example 20, the first circuit component of at least one of Examples 1 to 19 is a first conductive via.

In Example 21, the second circuit component of at least one of Examples 1 to 20 is a second conductive via.

In Example 22, the first conductive via of at least one of Examples 1 through 21 is electrically coupled to the first pad.

In Example 23, the first pad of at least one of Examples 1 through 22 is on the top surface of the interconnect die or at least partially in the top surface of the interconnect die.

In Example 24, the first pad of at least one of Examples 1 to 23 is positioned between (1) the first conductive via and (2) the first end of the conductive member.

In Example 25, the second circuit component of at least one of Examples 1 through 24 is electrically coupled to the second pad.

In Example 26, the second pad of at least one of Examples 1 through 25 is on the top surface of the interconnect die or at least partially in the top surface of the interconnect die.

In Example 27, the second pad of at least one of Examples 1 to 26 is positioned between (1) the second conductive via and (2) the second end of the conductive member.

In Example 28, the first mat of at least one of Examples 1 through 27 comprised a footprint size of 50 microns.

In Example 29, the first circuit component of at least one of Examples 1 through 28 comprised a footprint size of about 30 microns.

In Example 30, the apparatus of at least one of Examples 1 to 29 contains an adhesive.

In Example 31, the adhesive of at least one of Examples 1 to 30 was a solder resist.

In Example 32, the adhesive of at least one of Examples 1 to 31 was over the dielectric layer.

In Example 33, the adhesive of at least one of Examples 1 to 32 did not entirely cover the first and second circuit elements.

In Example 34, the device of at least one of Examples 1 to 33 can be positioned in a package.

In the example 35, the first die of at least one of the examples 1 to 34 is electrically coupled to the first through the first conductive via and the second conductive via Two grains.

In Example 36, the second pad of at least one of Examples 1 to 35 comprises a footprint having a size of 50 microns.

In Example 37, the second circuit component of at least one of Examples 1 through 36 includes a footprint having a size of about 30 microns.

In Example 38, the interconnecting elements of at least one of Examples 1 through 37 are germanium interconnected dies.

In Example 39, a method is included in the medium 102 in which the high density interconnect element 104 is embedded.

In Example 40, the method of at least one of Examples 1 to 39 includes electrically coupling the first and second circuit elements 110 to the conductive members 106 of the interconnect elements.

In Example 41, the method of at least one of Examples 1 to 40 includes positioning the dielectric layer 108 over the interconnect element.

In Example 42, the method of at least one of Examples 1 to 41 includes positioning the first die 114A over the medium.

In Example 43, the method of at least one of Examples 1 to 42 includes electrically coupling the first die to the first circuit component.

In Example 44, the method of at least one of Examples 1 to 43 includes positioning the second die 114B over the medium.

In Example 45, the method of at least one of Examples 1 to 44 includes electrically coupling the second die to the second circuit component.

In Example 46, positioning the first die on the medium at least one of Examples 1 through 45 includes positioning logic grains at the base Above the board.

In Example 47, at least one of Examples 1 through 46 positions the second die onto the substrate comprising a locating memory die over the substrate.

In Example 48, electrically coupling the first and second circuit components of at least one of Examples 1 to 47 includes electrically coupling the first and second conductive vias to the conductive member.

In Example 49, the method of at least one of Examples 1 to 48 includes positioning the first pad on a top surface of the interconnecting component or at least partially in a top surface of the interconnecting component.

In Example 50, positioning the first pad of at least one of Examples 1 to 49 includes positioning the first pad between (1) the first conductive via and (2) the first end of the conductive member.

In the example 51, electrically coupling the at least one of the examples 1 to 50 to the first and second conductive vias to electrically couple the first conductive via to the first pad.

In Example 52, the method of at least one of Examples 1 to 51 includes positioning the second pad on a top surface of the interconnecting member, or at least partially in a top surface of the interconnecting component.

In Example 53, positioning the second pad includes positioning the second pad between (1) the second conductive via and (2) the second end of the conductive member.

In Example 54, the electrically coupling the first and second conductive vias of at least one of the examples 1 to 53 includes electrically coupling the second conductive via to the second pad.

In Example 55, positioning the first pad of at least one of Examples 1 to 54 includes positioning a first pad comprising a footprint size of about 50 microns.

In Example 56, electrically coupling the first and second circuit elements of at least one of Examples 1 through 55 includes electrically coupling a first circuit component comprising a footprint size of about 30 microns.

In Example 57, the method of at least one of Examples 1 to 56 includes positioning the adhesive layer 122 over the dielectric layer.

The description of the above embodiments contains reference to the drawings which form a part of the description of the embodiments. The drawings used in the exemplification show specific embodiments in which the invention can be implemented. These embodiments are also referred to herein as "examples." Some examples may include elements other than those shown or described. However, the inventors of the present invention have also exemplified the examples of providing only those elements shown or described. Furthermore, the inventors of the present invention have also come up with these specific examples (or one or more aspects thereof), or other examples shown or described herein (or one or more aspects thereof) or An example of a combination or replacement of the elements (or one or more aspects thereof).

In this document, the use of "a" or "an" or "an" or "an" In this document, the term "or" is used to mean that it is not excluded, or, for example, "A or B" includes "A, but not B", "B but not A", and unless otherwise specified "A and B". In this document, the terms "including" and "where" are used as the individual terms "including" and "where", etc. effect. Also, in the scope of the following claims, the terms "comprises" and "comprising" are open, that is, a system, device, article, composition, formulation, or manufacture of the components listed in the term in a claim. In addition, other components are included and are considered to fall within the scope of the claim. Furthermore, the terms "first", "second", and "third", etc., as used herein, are used in the context of the following claims, and are not intended to indicate the quantity of the items.

The above description is intended to be illustrative and not limiting. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may also be used, for example, by those skilled in the art after viewing the above description. The Abstract is provided by way of patent law to allow the reader to quickly ascertain the nature of the present disclosure. It is emphasized that it is not intended to explain or limit the scope or meaning of the patent application. Also, in the above description of the embodiments, various features may be grouped together to rationalize the case. This should not be interpreted as an unneeded disclosure feature that is an essential feature of any claim. On the contrary, the subject matter of the invention lies in all features that are less than the specific disclosed embodiments. Accordingly, the following claims are incorporated in the description of the embodiments, each of which is a separate embodiment and is intended to be understood that the embodiments can be combined in various combinations or alternatives. The scope of the invention should be determined by reference to the appended claims and the equivalent scope of the claims.

Claims (24)

An apparatus having a localized high-density substrate winding, comprising: a medium including a low-density interconnect winding therein; a first circuit component and a second circuit component; and an interconnection component, the interconnection component being embedded in the medium The interconnecting component includes a high-density winding, the interconnecting component includes a plurality of conductive members, and a conductive member of the plurality of conductive members is electrically coupled to the first circuit component and the second circuit component; An electrical layer overlying the interconnect element, the dielectric layer including the first and second circuit elements passing therethrough. The device of claim 1, comprising: a first die electrically coupled to the first circuit component, the first die above the medium; and a second die The second die is electrically coupled to the second circuit component, the second die being above the dielectric. The device of claim 2, wherein: the first die is a logic die; and the second die is a memory die. The device of claim 1, wherein the first circuit component is a first conductive via and the second circuit component is a second conductive via. The device of claim 4, wherein the first conductive via is electrically coupled to the first pad, and the first pad is on the top surface of the interconnect component or at least partially in the interconnect component In the top surface, the first pad is positioned at the The first conductive via is between the first end of the conductive member. The device of claim 5, wherein the second conductive via is electrically coupled to the second pad, the second pad being on the top surface of the interconnect component or at least partially interconnected In the top surface of the component, the second pad is positioned between the second conductive via and the second end of the conductive member. The device of claim 1, comprising: a solder resist on the dielectric layer, the solder resist not completely covering the first and second circuit components. A method for fabricating a device having a localized high-density substrate winding includes: embedding an interconnect die in a substrate, the interconnect die comprising a conductive member electrically coupling the first and second circuit components to a conductive member; and a positioning dielectric layer over the interconnected die. The method of claim 8, comprising: positioning the first die on the substrate; electrically coupling the first die to the first circuit component; positioning the second die on the substrate And electrically coupling the second die to the second circuit component. The method of claim 9, wherein: positioning the first die includes positioning logic grains on the substrate over the substrate; and positioning the second die to include positioning on the substrate The memory grains are above the substrate. The method of claim 8, wherein electrically coupling the first and second circuit components comprises electrically coupling the first and second conductive vias to the conductive member. The method of claim 11, comprising positioning the first pad over the top surface of the interconnect die or at least partially in a top surface of the interconnect die, and positioning the first pad Between (1) the first conductive via and (2) the first end of the conductive member; and electrically coupling the first and second conductive vias to electrically couple the first conductive via to the first a mat. The method of claim 12, comprising positioning the second pad on a top surface of the interconnect die or at least partially in a top surface of the interconnect die, positioning the second pad at ( 1) between the second conductive via and (2) the second end of the conductive member; and electrically coupling the first and second conductive vias to electrically couple the second conductive via to the second pad. The method of claim 8, comprising: positioning a solder resist on the dielectric layer. A package having a localized high-density substrate winding, comprising: first and second crystal grains; a substrate; first and second conductive vias; interconnecting crystal grains, wherein the interconnected crystal grains are embedded in the substrate The interconnect die includes a conductive member embedded therein, the interconnect die including first and second conductive pads on a top surface of the interconnect die or at least a portion on a top of the interconnect die The conductive member is electrically coupled to the first conductive via through the first conductive pad and electrically coupled to the second conductive via through the second conductive pad; a dielectric layer, the dielectric layer Above the interconnecting die, the dielectric layer includes the first and second conductive vias therebetween; and wherein the first die is electrically coupled to the first conductive via and the second conductive via Second grain. The package of claim 15, wherein the first die is a logic die and the second die is a memory die. The package of claim 15 wherein the first and second pads each comprise a footprint of 50 microns, and wherein the first and second conductive vias each comprise a footprint of 30 microns. The package of claim 15 includes a solder resist on the dielectric layer, the solder resist not covering the first and second conductive vias. An apparatus having a localized high-density substrate winding, comprising: a semiconductor substrate; a first circuit component and a second circuit component; a germanium interconnecting die, the germanium interconnecting die being embedded in the semiconductor substrate, the germanium interconnecting The die includes a conductive member electrically coupled to the first circuit component and the second circuit component; and a dielectric layer over the germanium interconnect die, the dielectric layer The first and second circuit elements are included therethrough. The device of claim 19, comprising: a first die electrically coupled to the first circuit component, The first die is above the substrate; and the second die is electrically coupled to the second circuit component, the second die being above the substrate. The device of claim 20, wherein: the first die is a logic die; and the second die is a memory die. The device of claim 19, wherein the germanium interconnect die comprises a first conductive pad on a top surface of the germanium interconnect die or at least a portion in a top surface of the germanium interconnect die The first conductive pad is electrically coupled to the first circuit component, and the first conductive pad includes a footprint size of about 50 microns. The apparatus of claim 19, wherein the first circuit component comprises a footprint size of about 30 microns. The device of claim 19, comprising: a solder resist on the dielectric layer, the solder resist not covering the first and second circuit components.