TW200409324A - High-density multi-chip modulestructure and the forming method thereof - Google Patents

Abstract

The invention discloses a high-density multi-chip module (MCM) structure and the forming method thereof. First of all, an insulating layer and a multilevel interconnect layer are sequentially formed on an integrated circuit substrate. The multilevel interconnect layer has a first surface having a plurality of first bonding pads thereon and a second surface having a plurality of first bonding pads thereon. Then an adhesive layer and a transparent substrate comprising a glass substrate are sequentially formed on the first surface of the multilevel interconnect layer. Next the integrated circuit substrate is removed, and a portion of the insulating layer is etched to expose the second bonding pads on the second surface of the multilevel interconnect layer. The a plurality of chips are electrically connected to the second bonding pads by flip chip or wire bonding processes and are mounted by using underfill/resin. Then a heat sink is disposed to provide heat dissipation and structural support. Finally, the transparent substrate and the adhesive layer are removed and the high-density multi-chip module (MCM) is completed.

Description

200409324 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to the structure and forming method of a high-density multi-chip module, in order to improve the chip density of the multi-chip module and shorten the time between circuits. Distance to improve communication efficiency between chips. 5-2 Background of the Invention: In the past, integrated circuit construction technology developed by integrated circuit manufacturers has attempted to meet miniaturization requirements. An improved method for miniaturized integrated circuits is to enable them to incorporate millions of transistor circuit elements including circuits, wafers, etc. on a silicon substrate. These improved methods have led to a greater emphasis on the method of constructing circuit components in a limited space.

The integrated circuit is manufactured in a integrated circuit device by a silicon wafer through complex etching, doping, deposition, and cutting techniques. A silicon wafer contains at least one integrated circuit chip, and each chip represents a separate integrated circuit. Finally, the chip can be constructed by a plastic compound (Molding Compound) that surrounds the chip, and has a variety of pins exposed and interconnected designs. For example: to provide a M-D-In-Line-Package (M-Dip) with a fairly flat structure, which has two rows of parallel pins extending from the bottom through hole, Contact and fix on the integrated circuit board below. The printed circuit board that allows higher density integrated circuits is a single-line package (Single-In-Line-Package; SIP

200409324 V. Description of the invention (2) Douyuan / Li pin structure (Sma11 0utline J-leaded; SOJ), which is a structure using a model. Kind of Ϊ: Ϊ ΐ 的 体 体 电路 片 # 目 目, constructing integrated circuit scp) 夕 B σ knife is an early chip package (Single Chip Package; 片片 炉 二 Γ 片 结构 i (Multlchip Package; MCP ) Two major categories, and more). If you are busy, Zhaochao ’s chip module assembly (Multi chip Module; MCM is divided into the pin 7 and the circuit board connection method, the integrated circuit can be constructed (S-fac M-type (Pin —Through —Hole (PTH) and the pins of the surface-adhesive components are: pin = '01;: two categories. Pin-insertion type socket) or the lead-through hole of the circuit board The typed components are fixed with 1 a, 1 fixed, and 1 dry-bonded. The surface is currently glued to a jif board, and then fixed by soldering. Fh-More advanced mounting technology is direct chip bonding (Direct size) ^ I H in order to reduce the volume of the integrated circuit structure «junction; = the degree of accumulation of the department. The wafer is directly connected. On the soil board (SUbStrate), the circuit is then photographed. Figure: :: ;;: = Mounting on the substrate ... Block 20 flip chip is connected to the substrate 30: "" Most of the solder bumps are bonded to the substrate 30, and then the chip 彳 j: Firstly, ^ knife a plurality of wafers 1 〇Adhesive will be "10 and the substrate 30 through the lead 200409324 V. Description of the invention (3), so that the signal can be transmitted between the wafer and the substrate. Finally in the crystal Cover 40 is used to protect the majority of the wafers 10 on the substrate. In the above-mentioned conventional technology, most of the wafers are directly or indirectly connected to the substrate and are routed by the circuit of the substrate (routing). The electrical communication with each other will increase the difficulty of winding the circuit of the substrate itself in the conventional technology, and the larger the distance between the chip and the volume of the integrated circuit cannot be reduced, which increases the package size. The cost of the substrate is increased, and the electrical performance is limited due to the long circuit communication path between the chips. Although the industry has proposed a multifunctional single chip (Silicon on a Chip; S0C) that integrates active and passive components Solution, but its design and manufacturing process is still difficult and expensive. 5-3 Purpose and Summary of the Invention: In view of the above background of the invention, the traditional structure and method of directly connecting most wafers to the substrate cannot be reduced. The volume of the integrated circuit will reduce the communication efficiency between the circuits in the package. Therefore, the present invention provides an area density multi-chip module. Structure and formation method 'uses a plurality of interconnecting layers formed on a integrated circuit substrate to connect a plurality of chips, thereby forming a high-density multi-chip module to shorten the distance between circuits in a multi-chip package, and Improve the communication efficiency between circuits. The second object of the present invention is to use the integrated circuit substrate

200409324 V. Description of the Invention (4) The multi-layer interconnection layer connects multiple chips to form a high-density multi-chip module, which can smoothly reduce the size of the multi-chip package and reduce the manufacturing cost of the multi-chip module. A third object of the present invention is to use a plurality of interconnecting layers formed on a integrated circuit substrate to connect a plurality of chips, thereby forming a high-density multi-chip module, in order to simplify the traditional substrate winding process and improve multi-chip. Wafer Package Yield The fourth object of the present invention is to use a plurality of interconnecting layers formed on an integrated circuit substrate to connect a plurality of wafers, thereby forming a high-density multi-chip module, which can be easily designed and integrated with processes. Active components and passive components are included in the multi-chip module of the present invention. According to the above-mentioned object, the present invention provides a structure and a forming method of a high-density multi-chip module, which uses a plurality of interconnecting layers formed on an integrated circuit substrate to connect a plurality of chips to form a high density. Multi-chip module. In the invention, an insulating layer and a plurality of interconnecting layers are sequentially formed on a integrated circuit substrate, wherein the first surface of the multilayer interconnecting layer is provided with a plurality of first pads, and the second surface is provided with a plurality of first pads. Two solder pads. Next, a bonding layer and a transparent substrate, such as a glass substrate, are sequentially formed on the first surface of the multilayer interconnecting layer. Next, the integrated circuit substrate is removed, and a part of the insulating layer is etched to expose the second pad on the second surface of the multilayer interconnection layer. Next, most of the chips are electrically connected to the chip by flip-chip or wire connection.

200409324 V. Description of the invention (5) Two solder pads, and the wafer is fixed by the sealing compound. A heat sink is then installed to provide heat dissipation and structural support. Finally, the transparent substrate and the adhesive layer are removed to complete the high-density multi-chip module of the present invention. The high-density multi-chip module of the present invention can shorten the distance between the circuits in the package and smoothly reduce the size of the package. The high-density multi-chip module of the present invention can further improve the performance of the package. 5-4 Detailed Description of the Invention: Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited by the embodiments, which is subject to the scope of subsequent patents. The invention provides a structure and a forming method of a high-density multi-chip module, which uses a plurality of interconnecting layers formed on an integrated circuit substrate to connect a plurality of chips to form a high-density multi-chip module. Referring to the second figure, this is an integrated circuit substrate provided by the present invention, and an insulating layer, a multilayer interconnecting layer, an adhesive layer, and a transparent substrate are formed on the integrated circuit substrate. The schematic. The present invention first provides an integrated circuit substrate 100, and forms an insulating layer 110 on the integrated circuit substrate 100. Next, a plurality of interconnecting layers 120 is formed on the surface of the insulating layer 110, wherein the plurality of interconnecting layers 120

200409324 V. Description of the invention (6)-12 The first surface 122 includes a plurality of first pads 13 and a second surface 124 u a and a plurality of first I dry pads 132. Next, an organic bonding layer 1440 is formed on the first surface 122 of the multilayer interconnecting layer 120, and a transparent substrate 50 is formed on the organic bonding layer 14o, such as: glass substrate, quartz substrate, etc. . The organic bonding layer 140 may be a polymer polymer glue, and its function is to increase the bonding force between the transparent substrate 150 and the multilayer interconnecting layer i 2 〇 to avoid the transparent substrate 150 fell off, and the transparent substrate was used to provide structural support for subsequent processes. >,?, shown in the first figure 'This is a schematic diagram of removing the integrated circuit substrate and part of the insulating layer to expose the second pad. After forming the lunar substrate on the organic bonding layer, it can be used to meet the needs of the manufacturing process to determine whether to turn the integrated circuit to make the transparent substrate contact the process operation equipment and carry out subsequent process steps. Range. Next, the insulating layer 1 10 of the integrated circuit substrate 舁 part is removed to expose the second bonding pad 132 on the second surface j24 of the multilayer interconnecting layer i 20, where the integrated circuit substrate 100 can be researched. 3 ways? • And part of the insulating layer is removed by ordinary etching. All ί. The position of the first solder pad 1 3 2 is the position where the solder bumps on the wafer are contacted in subsequent processes. Most of the chips are electrically connected to the second solder through FHp-ChlP BUmp or V-line connection,., D (Wlre-Bonding) or other means, so as to interconnect with multiple layers. Line layer connection 'to enable the signal to be transmitted between the interconnect layers of most chip layers. Only three examples are provided below.

200409324 V. Description of the invention (7) The phase between the wafer and the multilayer interconnecting wire I Η 媪 伯 伯 a, 0 to make the high-density polycrystalline chip core group of the present invention, but most of the wire layers are not connected to each other. On the evening, the number of modes in which the film is connected to multiple layers is shown in Figure A and the fourth figure. This is Yue # ^. ^ This is the first t-day of connecting Japanese and Japanese films with multiple layers of interconnecting wires-the example of the towel "most wafers 2 _ embarrassed by the majority of solders on each wafer 2000" 2 19 / lu ># The tail ZiU is bonded to the second cousin of the multi-layer interconnect layer 120—the pad 1 3 2 and interconnects with the multi-layer interconnect layer 1 2 0: and enables the signal to be transmitted on most chips. 2 0 0 and multi-layer interconnected 12 0 delivery. As shown in the fifth picture, this is a schematic diagram of installing a "seat sink" around the wafer in the fourth picture. When most of the wafers 200 are interconnected with the multilayer interconnect layer -120, Immediately use the sealant i 丨 / to fight) to fix the wafer and protect the connection between the wafer 2000 and the multilayer interconnect layer i 2 ′ and avoid the occurrence of several wafers 2000 between each other. The contact phenomenon causes a short circuit defect. Then, a heat sink MO with a groove structure can be installed around a plurality of wafers 2000 and on the insulation ==, and the heat sink MO can be used for several wafers 200, On the one hand, the dispersion efficiency of the majority of wafers is increased by 200, on the one hand, it can provide the EMm shielding function, and on the other hand, it can provide ... between the inactive surface of the 200 / ^ and the heat sink 32. A 0 can be used to bond the two to increase the heat transfer efficiency. Most of the chips 200 and the heat sink 3 2 0 are packaged with a resin 300. ^

Page 12 200409324

Refer to Figure 6 for a schematic view of this helmet. When in many chips TTF Tianming \ high-density multi-chip modules can use light, laser, or heat to heat the surrounding women's heat to dissipate 4 pieces after 3 2 0, followed by the polymer molecular structure, so that this work, The organic bonding layer 14 is decomposed by a knife, and then a laser and a light source are used to adhere t to remove the transparent substrate 15 (stripping) Etchlng) ^ The first interconnection layer 120 deprives the organic The bonding layer 140 is exposed to expose the multi-chip module. Another 1 2 2 and completed the high density of the invention

Referring to the seventh figure, this master drinks a second embodiment. The high-density multi-chip module ^ ^ implemented in the second two 3 each chip 2 0 0 multiple cases on the active surface / the majority of the chip 2_ by the first surface of the layer interconnect layer 120 ^ ^ contact bump 210 It is electrically connected to the multi-layer # 2 2 (1¾), and first uses a non-active surface to use an adhesive I field on the second surface 1 24 of the interconnect layer 1 20, and then: = The guide wire 2! 0 electrically connects the majority of the wafers 200 of this part ☆ with a part of the second pads 132 on the second surface 124 of the multi-layered household joint 120. To make the news = this different form ( Flip-chip or wire bonding) are transferred between a plurality of wafers 200 and a plurality of interconnecting layers 120.

—As shown in the seventh picture of the tea, the underfill / Resin 300 is used to fix the wafer and protect the connection between the wafer 200 and the multilayer interconnect layer 120, and to avoid the majority of wafers 2000 Short circuit caused by contact between each other

Page 13 200409324 V. Description of the Invention (9)-Missing. ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Λ 10,000 面 面 面 面 面 面 面 夕 夕 晶片 晶片 晶片 晶片 晶片 晶片 2 0 2 0 0 0 It can provide EM I shielding function, and on the other hand, it can provide multi-die mode, and the structure strength. According to the process and product requirements, a thermally conductive adhesive layer 31 can be used between the non-active surface of most flip-chip wafers and the heat sink 3 2 0 to increase thermal conductivity. # 一 ^ 知 ， shown in the eighth figure ’This is the second embodiment of the high-density multi-chip module of the present invention. In the third embodiment, the plurality of wafers 200 are first adhered to the second surface 124 of the multilayer interconnect layer 120 with their non-active surfaces, and then the plurality of wafers are electrically connected with the wires 230. The chip 200 is interconnected with multiple layers, and the second pads 32 on the second surface 12 of the layer 120, so that the signal can be connected to the multilayer interconnect layer 1 2 with the multiple chips 2 00. Between. Still seeing and seeing the figure of the eighth figure, 'sealing glue (Underfi 1 1 / Re esi η) 3 0 0 is to fix the chip and protect the connection between the chip 2 0 and the multilayer interconnect layer 1 2 0, and avoid A phenomenon in which a plurality of wafers 200 are in contact with each other results in a short-circuit depression. A heat sink 32 can be installed around the majority of wafers 200 to increase the heat dissipation efficiency of the majority of wafers 200. On the one hand, it can provide e μ I shielding function. On the other hand, it can provide multi-chip modules. Structural strength. ^ Using the structure and method of the present invention, a high-density multi-chip module made by connecting a plurality of wafers to a plurality of interconnecting layers on a substrate of an integrated circuit can reduce the distance between the plurality of wafers. And shorten the circuit and power

Page 14 200409324

V. Description of the Invention (ίο) In the multi-chip module of Qiadu, electricity will be accelerated, and the size of the circuit's operational circuit. The distance between the roads. Therefore, the signal transmission speed & operation efficiency between the high road and the circuit of the present invention will be improved, and the structure of the above-mentioned forms will not be reduced. This is not a high-density map of multi-chip simulation. It can be divided into the first surface multi-wafer die embodiment, which is completed by the South-density multi-g-private-community module, T, and φ 4 day-chip modules, which can be applied to multiple seals and one structure. Description, but limited. And only the first embodiment is used to apply the application method of the high-poor fragmentation group of the present invention with _M &, and any practical example ^ ^ ^ 夂 门 山 度 焉 ^^ can be applied separately ,

Making the scope of the invention. Referring to the ninth figure, this is: a schematic diagram of the invention of a multi-chip board group directly forming a ball grid array package for a plurality of solder balls 4 10, which is freshly connected to the multi-chip die by the process of solder balls on the traditional package. A plurality of first interconnect pads 1 2 1 of a plurality of multilayer interconnecting layers 12 2 to 12 are directly completed to complete a ball grid array package having a group. Referring to the tenth figure, this is a schematic view of a high-density multi-chip module of the present invention combined with a package substrate in a flip-chip manner to form a ball grid array flip-chip package. First, a general bump process is used to form a solder bump 4 2 0 on each of the first solder pads 1 3 1 on the first surface 1 2 2 of the multilayer interconnect layer 12 2 of the multi-chip module. Next, in a general flip-chip packaging process, the solder bumps 4 2 0 are respectively bonded to a plurality of bump pads 5 1 0 on a substrate 5 0 0, so as to integrate the high-density multi-chip module 4 0 0 of the present invention. It is fixed on the substrate 5 0, wherein the multi-chip module and the substrate are filled with primer 4 0 0 (Underfi 1 1) to fix the multi-chip module on the substrate 5 0 0 and avoid bumps 4 1 0 each other Happen between

Page 15 200409324 V. Description of the invention (11) The contact phenomenon that causes a short circuit in a semiconductor device. Finally, in the above solder ball manufacturing process, a plurality of solder balls 5 50 are respectively soldered to a plurality of solder ball pads 5 40 on the bottom surface of the substrate 500. Referring to FIG. 11, this is a schematic diagram of a high-density multi-chip module combined with a package substrate to form a Cavity T-Down ball grid package. First, a package substrate 500 including a through hole 5 2 0 is provided. Next, the high-density multi-chip module 400 of the present invention is installed in this shell hole 5 2 0, wherein the heat sink 3 2 0 on the high-density chip module 400 contacts the shell hole 5 2 0. The side wall, where the substrate 500 is on the same side as the first surface 12 of the multi-chip module is provided with a plurality of contacts 5 and 0 and a plurality of balls 5 4 0. Next, a plurality of wires 5 3 0 are used to connect the plurality of first pads 1 3 1 on the first surface 1 2 2 of the high-density chip module and the plurality of contacts 5 1 0 of the 5 0 ^ surface of the package substrate. A glue filling process is performed to cover the lead f 5 3 0, the first surface 122 of the multilayer interconnection layer ι 2 0, and the substrate 5 0 f with a plurality of contacts 5 1 0 to avoid high density The chip module is subject to external loops, and its quality and performance are reduced. Finally, in the above process of solder balls, the plurality of solder balls 5 50 are respectively welded and connected to the plurality of solder ball pads 5 4 0. In summary, the present invention provides a method for forming and forming a high-density multi-chip module, which uses a plurality of internal wiring layers formed on a substrate of an integrated circuit to connect a plurality of chips, thereby forming a high Multi-chip density module. According to the invention, an insulating layer and a plurality of interconnecting layers are sequentially formed on a integrated circuit substrate. The first surface of the multilayer interconnecting layer is provided with a plurality of first pads.

Page 16 200409324 V. Description of the invention (12) The second surface is provided with a plurality of second pads. Next, a bonding layer and a transparent substrate, such as a glass substrate, are sequentially formed on the first surface of the multilayer interconnecting layer. Next, the integrated circuit substrate is removed, and a part of the insulating layer is etched to expose the second pad on the second surface of the multilayer interconnection layer. Next, a plurality of chips are electrically connected to the second bonding pad by flip-chip or wire bonding, and the chip is fixed by using a sealant. A heat sink is then installed to provide heat dissipation and structural support. Finally, the transparent substrate and the adhesive layer are removed to complete the high-density multi-chip module of the present invention. The high-density multi-chip module of the present invention can shorten the distance between the circuits in the package and smoothly reduce the size of the package. The use of the high-density multi-chip module of the present invention can further improve the efficiency of the package. It not only has practical effects, but also has a design that has never been seen before. It has improved efficacy and progress.申请 Apply in accordance with the law. For this reason, the examiner would like to examine it in detail, and pray that he would grant the patent as soon as possible. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application.

200409324 Brief description of the drawings The above and the rest about the purpose, characteristics and advantages of the present invention can be more completely explained in the detailed description of the invention and the accompanying drawings. The first diagram is a schematic diagram of the structure of a conventional multi-chip package. The second diagram is an integrated circuit substrate provided by the present invention, and an insulating layer, a multilayer interconnecting layer, a first fresh pad, a first Schematic diagram of two fresh pads, an organic bonding layer, and a transparent substrate;

The third figure is a schematic diagram of removing the integrated circuit substrate and a part of the insulating layer to expose the second pad; the fourth figure is a schematic diagram of the first embodiment of a chip connecting multiple interconnecting layers. The fifth figure is around the chip and insulating Schematic diagram of installing a heat sink on the layer;

The sixth figure is a schematic view of the first embodiment of the high-density multi-chip module of the present invention; the seventh figure is the second embodiment of the high-density multi-chip module of the present invention;

Page 18 200409324 Brief description of the drawings The eighth figure is a schematic diagram of the third embodiment of the high-density multi-chip module of the present invention The ninth figure is a schematic diagram of the high-density multi-chip module of the present invention directly forming a ball grid array package The tenth figure is a schematic view of a high-density multi-chip module combined with a package substrate in a flip-chip manner to form a ball grid array flip-chip package; the eleventh figure is a high-density multi-chip module combined package of the present invention; A schematic view of a substrate forming a ball grid array package with an opening downward (Cavity-D ow η). Representative symbols of the main parts: 1 0 wafer 2 0 solder bump 3 0 substrate 3 5 lead 4 0 sealant 1 0 0 integrated circuit substrate 1 1 0 insulation layer 1 2 0 multilayer interconnecting layer 122 multilayer interconnection The first surface of the wire layer 12 The second surface of the multilayer interconnecting layer

Page 19 200409324 Schematic description 131 First pad 13 2 Second pad 1 4 0 Adhesive layer 1 5 0 Transparent substrate 2 0 0 Wafer 2 10 Bump 2 2 0 Adhesive layer 2 3 0 Wire 3 0 0 封 胶 31 0 Thermally conductive adhesive layer

3 2 0 heat sink 4 0 0 primer 41 0 bump 5 0 0 substrate 5 1 0 contact 5 3 0 wire 5 4 0 solder ball pad 5 5 0 solder ball

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Claims (1)

200409324 6. Scope of patent application 1. A high-density multi-chip module structure, wherein the structure includes: a multilayer interconnect layer having a first surface and a second surface; a plurality of first soldering pads located in the multilayer Most of the first surface of the interconnecting layer are second and second, a patterned insulating layer is located on the second surface of the multilayer interconnecting layer, is located on the second surface of the multilayer interconnecting layer, and is exposed. The second solder pads; a plurality of wafers located on the insulation layer and electrically connected to the second solder pads; and a heat sink located on the insulation layer and surrounding and covering the plurality of wafers. 2. For example, the high-density multi-chip module structure of the first patent application scope, wherein any one of the above-mentioned multiple chips is electrically connected to the second pads in a flip-chip (F 1 ip-Chip) manner. . 3. For example, the high-density multi-chip module structure of the scope of the patent application, wherein the non-active surface of the chip electrically connected to the second pads in a flip-chip manner can be connected to the chip by a thermally conductive adhesive layer. The heat sink is connected. 4. For example, the high-density multi-chip module structure of the first patent application scope, in which any one of the plurality of chips mentioned above is electrically connected to the second pads by a wire connection (Wire-Β ο nding) method. . 200409324 6. Scope of patent application 5. For example, the high-density multi-chip module structure of the first patent application scope, wherein the space between the above-mentioned heat sink and the plurality of chips and the multilayer interconnection layer is filled with sealant. 6. —A method for forming a high-density multi-chip module, comprising: providing an integrated circuit substrate; forming an insulating layer on the integrated circuit substrate; forming a multilayer interconnecting layer on the insulating layer , Wherein the first surface of the multilayer interconnection layer is provided with a plurality of first pads, and the second surface is provided with a plurality of second pads; Forming a bonding layer on the first surface of the multilayer interconnecting layer; forming a transparent substrate on the bonding layer; removing the integrated circuit substrate and part of the insulating layer to expose the second group of plutonium; Arranging a plurality of chips on the insulating layer and electrically connecting them to the second solder pads individually; and mounting a heat sink on the insulating layer to surround and cover the plurality of crystals 7. For the method for forming a high-density multi-chip module according to item 6 of the patent application scope, wherein any one of the above-mentioned plurality of chips is provided on the insulating layer in a flip-chip (F 1 ip-C hi ρ) manner, The plurality of solder bumps are electrically connected to the second solder pads. Page 22 200409324 6. Scope of patent application 8. The method for forming a high-density multi-chip module as described in item 7 of the scope of patent application, wherein before the heat sink is installed, the above-mentioned flip-chip method is used with the second solder pads. A non-active surface of the electrically connected wafer may form a thermally conductive adhesive layer. 9. The method for forming a high-density multi-chip module according to item 6 of the scope of patent application, wherein any one of the above-mentioned plurality of chips is provided on the insulating layer by a wire connection (Wire-Β ο nding) method, and The plurality of wires are electrically connected to the second pads. 10. The method for forming a high-density multi-chip module according to item 6 of the scope of patent application, wherein before installing the heat sink, the plurality of wafers and the wafers and the second solder pads are fixed with a sealant. Connection. 1 1. The method for forming a high-density multi-chip module according to item 6 of the patent application scope, wherein the above-mentioned adhesive layer is made of an organic polymer material. 12. The method for forming a high-density multi-chip module according to item 6 of the patent application scope, wherein after the heat sink is installed, the method further includes a step of sequentially removing the transparent substrate and the adhesive layer. 1 3. The method for forming a high-density multi-chip module according to item 12 of the scope of patent application, wherein the above-mentioned step of removing the transparent substrate is to use one of light, laser, and heating methods to decompose the adhesion The molecular structure of the layer causes it to lose its viscosity to remove the transparent substrate. 200409324 6. Application for patent scope 1 4. The method for forming a high-density multi-chip module as described in item 12 of the patent scope, wherein the above-mentioned steps for removing the adhesive layer are using laser and plasma etching (Plasma Etching) And stripping to remove the adhesive layer. 1 5. A method for forming a high-density multi-chip module, comprising: providing an integrated circuit substrate; forming an insulating layer on the integrated circuit substrate; forming a multilayer interconnecting layer on the insulating layer A plurality of first pads are provided on a first surface of the multilayer interconnecting layer, and a plurality of second pads are provided on a second surface of the multilayer interconnecting layer; an adhesive layer is formed on the first surface of the multilayer interconnecting layer Forming a transparent substrate on the bonding layer; removing the integrated circuit substrate and a part of the insulating layer to expose the second core; placing a plurality of chips on the insulating layer and electrically connecting them individually To the second pad; installing a heat sink on the insulating layer and surroundingly covering the plurality of chips; removing the transparent substrate; and removing the bonding layer. 16. The method for forming a high-density multi-chip module as described in item 15 of the scope of patent application 200409324 6. Method of applying for a patent, in which any one of the above-mentioned plurality of wafers is provided on the insulating layer in a flip-chip (FI ip-Chip) manner, and a plurality of solder bumps and the second solder pads are provided. Electrical connection. 17. The method for forming a high-density multi-chip module according to item 15 of the scope of patent application, wherein before the heat sink is installed, the above-mentioned non-conductive chip is electrically connected to the second bonding pads in a flip-chip manner. A thermally conductive adhesive layer can be formed on the active surface 18. The method for forming a high-density multi-chip module according to item 15 of the scope of patent application, wherein any one of the above-mentioned plurality of chips is provided on the insulating layer by a wire-bonding method, and borrows A plurality of wires are electrically connected to the second pads. 19. The method for forming a high-density multi-chip module according to item 15 of the scope of patent application, wherein before installing the heat sink, the plurality of wafers and the wafers and the second solders are fixed with a sealant. The connection of the pad. 20. The method for forming a high-density multi-chip module according to item 15 of the scope of patent application, wherein the above-mentioned adhesive layer is made of an organic polymer material. 2 1. The method for forming a high-density multi-chip module according to item 15 of the scope of patent application, wherein the above-mentioned step of removing the transparent substrate is to use one of light, laser, and heating methods to decompose the adhesion The molecular structure of the layer makes it lose Page 25 200409324 6. Scope of patent application Viscosity to remove the transparent substrate. 2 2. The method for forming a high-density multi-chip module according to item 15 of the scope of patent application, wherein the above steps for removing the adhesive layer are using laser, plasma etching, and stripping. ) To remove the adhesive layer. Page 26