WO2023241304A1

WO2023241304A1 - Chip packaging methods and chip

Info

Publication number: WO2023241304A1
Application number: PCT/CN2023/095076
Authority: WO
Inventors: 詹克团; 卓铭; 杨帅; 杨存永; 刘博�
Original assignee: 北京比特大陆科技有限公司
Priority date: 2022-06-17
Filing date: 2023-05-18
Publication date: 2023-12-21
Also published as: CN115116860A

Abstract

The present application relates to the technical field of packaging. Disclosed in the present application are chip packaging methods and a chip. A method comprises: providing a semiconductor device to be packaged and a first substrate, the first substrate comprising a first pad; adding a first packaging material to a surface of the first pad so as to form a bonding layer, attaching to the first pad a base of said semiconductor device by means of the bonding layer, and performing surface packaging processing on said semiconductor device and the first pad; forming bump structures on the surface of said semiconductor device facing away from the base; providing a second substrate, attaching the bump structures to the second substrate, and performing flip packaging processing on said semiconductor device and the second substrate; and, by means of a second packaging material, performing plastic packaging processing on said semiconductor device. The embodiments of the present application aim to improve the heat dissipation efficiency and the heat dissipation effect of a chip, thereby prolonging the service life of the chip.

Description

Chip packaging method and chip

Technical field

The present application relates to the field of packaging technology, and in particular, to a chip packaging method and a chip.

Background technique

For high-power chips, due to their high power, the chip temperature will rise during operation. In the existing technology, people generally attach a heat sink to the surface of the chip after packaging for heat dissipation. However, due to the packaging material wrapping the chip, The thermal conductivity is very low, which will cause most of the heat emitted by the chip to be unable to be conducted to the outside world, thereby reducing the service life of the chip and even causing the chip to burn out. Therefore, the heat dissipation effect of existing chip heat dissipation solutions will be limited by the packaging material, resulting in a greatly reduced heat dissipation effect and low heat dissipation efficiency.

Contents of the invention

This application provides a chip packaging method and a chip, aiming to improve the heat dissipation efficiency and heat dissipation effect of the chip, thereby increasing the service life of the chip.

In a first aspect, embodiments of the present application provide a chip packaging method, which method includes:

providing a semiconductor device to be packaged and a first substrate, the first substrate including a first bonding pad;

Adding a first packaging material to the surface of the first bonding pad to form an adhesive layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the adhesive layer, and attaching the substrate to the first bonding pad. The semiconductor device to be packaged and the first pad are subjected to surface packaging processing;

Form a bump structure on the side of the semiconductor device to be packaged facing away from the substrate;

Provide a second substrate, attach the bump structure to the second substrate, and perform a flip-chip packaging process on the semiconductor device to be packaged and the second substrate;

The semiconductor device to be packaged is subjected to a plastic packaging process through a second packaging material.

In a second aspect, embodiments of the present application also provide a chip packaging method, which method includes:

Provide a semiconductor device to be packaged, and form a bump structure on a side of the semiconductor device to be packaged facing away from the substrate;

Perform a plastic packaging process on the semiconductor device to be packaged through a second packaging material, so that the semiconductor device to be packaged is injection molded;

providing a first substrate, the first substrate including a first pad;

A first packaging material is added to the surface of the first bonding pad to form an adhesive layer, and the semiconductor device substrate to be packaged is attached to the first bonding pad through the adhesive layer, and the The semiconductor device to be packaged and the first pad are subjected to surface packaging processing.

In a third aspect, embodiments of the present application further provide a chip, which includes:

Semiconductor device;

a first substrate, the first substrate including a first pad connected to the substrate of the semiconductor device through an adhesive layer;

A bump structure arranged on the side of the semiconductor device facing away from the substrate;

a second substrate, the second substrate is connected to the side of the chip facing away from the substrate through the bump structure;

Filling medium is used to fill the gap between the first substrate and the second substrate and encapsulate the semiconductor device.

Embodiments of the present application provide a chip packaging method and a chip. The method includes: providing a semiconductor device to be packaged and a first substrate, where the first substrate includes a first bonding pad; Injecting a first packaging material to form an adhesive layer, bonding the substrate of the semiconductor device to be packaged to the first pad through the adhesive layer, and bonding the semiconductor device to be packaged with the first pad The pad is subjected to surface packaging processing; a bump structure is formed on the side of the semiconductor device to be packaged away from the substrate; a second substrate is provided, the bump structure is attached to the second substrate, and the bump structure is attached to the second substrate. The semiconductor device and the second substrate are flip-chip encapsulated; the semiconductor device to be encapsulated is plastic encapsulated through the second encapsulating material; thus, it can avoid being limited by the low thermal conductivity of the encapsulating material and can emit heat from the chip. Heat is conducted to the outside world from both the top and bottom of the chip at the same time, improving the heat dissipation efficiency and effect of the chip, thereby increasing the service life of the chip.

Description of the drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic flow chart of a chip packaging method provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a first pad provided by an embodiment of the present application;

Figure 3 is a schematic diagram of a partial structure of surface packaging in a chip packaging method provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of a bump structure provided by an embodiment of the present application;

Figure 5 is a schematic diagram of a flip-chip packaging scenario in a chip packaging method provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of a chip provided by an embodiment of the present application;

Figure 7 is a schematic flow chart of a chip packaging method provided by another embodiment of the present application;

Reference signs:
100. Chip
10. Semiconductor devices;
20. First substrate; 21. First pad; 22. Adhesive layer;
30. Bump structure; 31. Bump metal layer; 32. Solder ball;
40. The second substrate; 41. The second pad;
50. Fill the medium.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all contents and operations/steps, nor are they necessarily performed in the order described. For example, some operations/steps can also be decomposed, combined or partially merged, so the actual order of execution may change according to actual conditions.

It should be understood that the terminology used in the specification of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise.

It is further to be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. .

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments may be combined with each other without conflict.

Chip packaging technology is a process technology that wraps memory chips to prevent the chip from contacting the outside world and prevent damage to the chip from the outside world. Impurities, bad gases, and even water vapor in the air will corrode the precision circuits on the chip, causing a decline in electrical performance. Different packaging technologies vary greatly in manufacturing procedures and processes, and packaging also plays a vital role in the performance of the memory chip itself.

Existing packaging technologies can generally be divided into through-hole packaging and SMD packaging. Since the temperature of the chip will increase during operation, in the existing technology, people generally attach a heat sink to the surface of the chip after packaging for heat dissipation. However, Since the thermal conductivity of the packaging material surrounding the chip is generally very low, the heat emitted by the chip cannot be well conducted to the outside world for heat dissipation. Therefore, the heat dissipation effect will be limited by the packaging material, greatly reducing the heat dissipation effect.

Embodiments of the present application provide a chip packaging method and a chip, which can avoid being limited by the low thermal conductivity of the packaging material, can conduct the heat emitted by the chip to the outside world from the top and bottom of the chip at the same time, and improve the heat dissipation efficiency of the chip. Heat dissipation effect, thereby increasing the service life of the chip.

Please refer to FIG. 1 , which is a schematic flowchart of a chip packaging method provided by an embodiment of the present application.

As shown in Figure 1, the chip packaging method specifically includes steps S101-S105.

S101. Provide a semiconductor device to be packaged and a first substrate, where the first substrate includes a first bonding pad.

As shown in FIG. 2 , the semiconductor device 10 to be packaged is an unpackaged bare chip (ie, die), which may be an unpackaged wafer or die. The wafer refers to silicon used in the production of silicon semiconductor integrated circuits. Wafers; silicon wafers can be processed into various circuit component structures and become devices with specific electrical functions. Integrated circuit products.

Since the material of the semiconductor device 10 to be packaged is silicon, and the thermal conductivity of silicon is 118 W/m.k, which is above 100 W/m.k, the semiconductor device 10 to be packaged can conduct heat well.

As shown in FIG. 2 , the first substrate 20 may be ceramic or a printed circuit board (PCB). The first substrate 20 includes a first bonding pad 21. The first bonding pad 21 may be a metal pad, specifically a metal pad with good thermal conductivity such as a copper pad, used to dissipate heat from the semiconductor device 10 to be packaged.

In some embodiments, the first pad 21 is formed on the surface of the first substrate 20 .

Specifically, the surface of the first substrate 20 is configured to correspond to the substrate on which the semiconductor device 10 is to be packaged, and the first pad 21 can be directly soldered to the first substrate 20 . The function of the first pad 21 is to dissipate heat, and when the chip is working, heat will be generated. At this time, the heat can be quickly radiated to the entire first substrate 20 through the first pad 21, so that the heat dissipation area becomes larger and the heat dissipation speed is faster.

For example, the first pad 21 can be welded at any position on the first substrate 20. Preferably, the first pad 21 can be welded at the center of the first substrate 20. As shown in Figure 2, the first substrate 20 In a zigzag shape, the first pad 21 is disposed at the center of the first substrate 20 . This can achieve better heat dissipation effect.

S102. Add a first packaging material to the surface of the first bonding pad to form an adhesive layer, and attach the substrate of the semiconductor device to be packaged to the first bonding pad through the adhesive layer, and Surface packaging processing is performed on the semiconductor device to be packaged and the first pad.

The adhesive layer 22 may be formed by injecting a first packaging material onto the surface of the first bonding pad 21 , and is used to bond the substrate of the semiconductor device 10 to be packaged to the first bonding pad 21 . The first packaging material may include a soldering material for soldering the substrate of the semiconductor device 10 to be packaged to the first pad 21 . The substrate for the semiconductor device 10 to be packaged may be made of SiC, Si or GaAs.

Specifically, the thermal conductivity of the soldering material is 50 W/m.k, so the soldering material can also conduct heat well and the adhesive layer 22 is formed of the soldering material, that is, the semiconductor device 10 to be packaged can be packaged through the adhesive layer 22 Most of the heat emitted is conducted to the outside world, thereby avoiding being restricted by the low thermal conductivity of the packaging material, and enabling the heat emitted by the chip to be quickly conducted from above the chip to the outside world.

Specifically, the surface package includes a QuadFlatNo-lead package (QuadFlatNo-lead Package, QFN) or DFN (DualFlatNo-lead Package) package. Among them, the pins of the DFN package are distributed on both sides of the package and the overall appearance is rectangular, while the pins of the QFN package are distributed on all four sides of the package and the overall appearance is square. QFN packaging has the advantages of small size, light weight, good heat dissipation, good electrical performance, good reliability and high cost performance, so QFN packaging is generally chosen.

In some embodiments, the first packaging material is printed on the first pad 21 to form an adhesive layer 22, and the substrate of the semiconductor device 10 to be packaged is placed on the adhesive layer 22; The substrate of the device 10 is soldered to the first bonding pad 21 , so that the substrate of the semiconductor device 10 to be packaged is packaged on the first bonding pad 21 . This allows the semiconductor device 10 to be packaged to conduct most of the heat emitted by it to the outside through the adhesive layer 22 , thereby avoiding being restricted by the low thermal conductivity of the packaging material and enabling the heat emitted by the chip to be quickly conducted from above the chip. to the outside world.

For example, since the thickness of the wafers coming out of the general wafer factory is about 550 to 725 microns, and the total thickness of the conventional QFN package is also 550 to 750 microns, the wafer cannot be put in without thinning. . Therefore, the wafers coming out of the wafer factory need to be ground and thinned to obtain the semiconductor device 10 to be packaged, so that the semiconductor device 10 to be packaged can be easily packaged in a limited space. Specifically, chemical mechanical polishing or laser cutting can be used to thin the wafer substrate.

Generally, N independently functional dies can be made on a wafer. Before packaging, the wafer can be diced to separate the dies one by one, and then each die can be bonded separately. Packaging process; or before packaging, the wafer is packaged, the protective layer can be bonded to the top or bottom of the wafer, and then the circuit is connected, and then the wafer is cut into individual chips, that is, wafer level packaging.

For the separated die, if the die does not have pins at this time, it needs to be placed on a metal carrier, because the metal carrier has pins. After the metal carrier is connected through silver paste or adhesive film , waiting for the next step of soldering wires.

As shown in FIG. 3 , the first packaging material is then printed on the first pad 21 to form an adhesive layer 22 , and the substrate of the semiconductor device 10 to be packaged is placed on the adhesive layer 22 , so that the semiconductor device 10 to be packaged is The substrate 10 is bonded to the adhesive layer 22, and then the substrate of the semiconductor device 10 to be packaged is welded to the first pad 21, so that the substrate of the semiconductor device 10 to be packaged is connected to the first pad 21, that is, The substrate of the semiconductor device 10 to be packaged is packaged on the first pad 21 .

Specifically, soldering the substrate of the semiconductor device 10 to be packaged to the first bonding pad 21 is actually also performing wire bonding processing on the semiconductor device 10 to be packaged, and connecting the pins of the semiconductor device 10 to be packaged to the first bonding pad 21 stand up. For example, automatic wire bonding equipment can be used to connect the function Pad of the semiconductor device 10 to be packaged with the pins of the first pad 21 with bonding wires, and connect the functions of the chip design to the external circuit board through the frame pins, thereby Make sure the product can work properly after being powered on.

S103. Form a bump structure 30 on the side of the semiconductor device to be packaged facing away from the substrate.

As shown in FIG. 4 , the bump structure 30 includes a bump metal layer 31 and a plurality of bumps located on the bump metal layer 31 . The bump metal layer 31 may be a Cu/Ni composite layer or a Ti/Cu composite layer.

Specifically, a polybenzoxazole (PBO) layer may be formed on the side of the semiconductor device 10 to be packaged away from the substrate, and at least a portion of the openings may be formed in the PBO layer, using physical vapor deposition (PVD). A first metal layer is deposited on the surface of the PBO layer and in the opening, and a photoresist layer is formed on the surface of the first metal layer, and openings are opened again at corresponding positions in the photoresist layer through photolithography processes such as exposure and development. And a second metal layer is deposited at the opening, and the first metal layer and the second metal layer together serve as the bump metal layer 31; and then electroplating is performed on the bump metal layer 31 to obtain a plurality of bumps. A bump structure 30 is formed on a side of the packaged semiconductor device 10 facing away from the substrate.

For example, a planar process can be used to make lead-free solder joints at the input/output terminal (I/O) of the integrated circuit chip.

S104. Provide a second substrate, attach the bump structure to the second substrate, and perform a flip-chip packaging process on the semiconductor device to be packaged and the second substrate.

The second substrate 40 may be a ceramic or a printed circuit board. The flip-chip packaging includes flip-chip technology (Flip-chip) or flip-chip ball grid array (Flip Chip Ball Grid Array, FC-BGA) packaging.

Flip-Chip packaging is to interconnect the chip with the second substrate 40 through bumps (i.e., bumps) with the functional area of the chip facing down and in an inverted manner facing away from the substrate. The chip placement direction is opposite to that of the traditional package with the functional area facing upward. Flip-Chip packaging has the advantages of small size, thin thickness, light weight, higher density, better radio frequency performance, and strong heat dissipation capability.

Referring to FIG. 5 , in some embodiments, the second bonding pad 41 corresponding to the bump structure 30 is formed on the surface of the second substrate 40 ; the bump structure 30 and the corresponding second bonding pad 41 are aligned and patched at Process; invert the bump structure 30 on the second substrate 40, and solder the bump structure 30 to the corresponding second pad 41, so that the bump structure 30 forms a solder ball 32, and is connected to the solder ball 32 through the solder ball 32. The second substrate 40 is connected. This allows the semiconductor device 10 to be packaged to conduct most of the heat emitted by it to the outside through the second substrate 40, avoiding being restricted by the low thermal conductivity of the packaging material, and allowing the heat emitted by the chip to be transferred from above the chip to below the chip simultaneously. Conducted to the outside world, it improves the heat dissipation efficiency and effect of the chip, thereby increasing the service life of the chip.

The second bonding pad 41 may be a metal bonding pad, specifically a metal bonding pad with good thermal conductivity such as a copper bonding pad, used to dissipate heat from the semiconductor device 10 to be packaged.

Specifically, a second bonding pad 41 corresponding to the bump structure 30 is formed on the surface of the second substrate 40 , and the second bonding pad 41 can be directly soldered to the second substrate 40 . The function of the second pad 41 is to dissipate heat, and when the chip is operating, heat will be generated. At this time, heat can be quickly radiated to the entire second substrate 40 through the second bonding pad 41, so that the heat dissipation area becomes larger and the heat dissipation speed is faster.

Exemplarily, as shown in FIGS. 4 and 5 , the bumps on the bump structure 30 and the second pads 41 on the second substrate 40 are aligned and patched, and then the semiconductor device 10 to be packaged is inverted. On the second substrate 40 , that is, the bump structure 30 is disposed facing the second substrate 40 , and finally a solder reflow process is used to form a solder ball 32 between the side of the semiconductor device 10 to be packaged away from the substrate and the second substrate 40 . Specifically, the photoresist layer can be removed, and the excess first metal layer on the surface of the PBO layer can be removed by wet etching, and then a reflow process can be performed to round the bumps into solder balls 32 .

S105. Perform a plastic packaging process on the semiconductor device to be packaged using a second packaging material.

The second encapsulation material may be a plastic encapsulation material, and the semiconductor device 10 to be encapsulated is plastic encapsulated using the plastic encapsulation material to fill the gap between the first substrate 20 and the second substrate 40 .

For example, the plastic package may be an epoxy molding compound (Epoxy molding compound) package. Among them, EMC is a thermosetting plastic and one of the common packaging materials for semiconductor packaging. The main ingredients are fillers, epoxy resins, curing agents, coupling agents, flame retardants, release agents, and modifications. Additives, etc.; among them, the filler content is the highest, which can improve the parameters and properties of epoxy resin, such as reducing the expansion coefficient, increasing thermal conductivity, increasing elastic modulus, etc.

In some embodiments, the thermal conductivity of the first packaging material is greater than that of the second packaging material. Thermal Conductivity.

Among them, the thermal conductivity of the plastic packaging material is 50W/m.k, and the second packaging material is a material with a smaller thermal conductivity such as plastic packaging material. The existing packaging technology generally fixes the chip to the corresponding heat dissipation chip carrier. In this way, although the side of the chip and the heat dissipation chip carrier can be used for heat dissipation, the side of the chip and the heat dissipation chip carrier that is away from it Wrapped by plastic packaging material, the side of the chip away from the heat-dissipating chip carrier cannot dissipate heat in time, and the heat dissipation effect will be limited by the packaging material, greatly reducing the heat dissipation effect and lowering the heat dissipation efficiency.

Since the thermal conductivity of the packaging material is very low, the problems of low heat dissipation and low heat dissipation efficiency in the existing packaging method can be solved by replacing the packaging material with a lower thermal conductivity with a material with a higher thermal conductivity. That is, the first packaging material is added to the surface of the first pad 21 to form the adhesive layer 22, and the first substrate 20 and the second substrate 40 are used to transfer the heat emitted by the chip from above the chip (ie, through the first substrate 20). It is conducted to the outside world at the same time as the bottom of the chip (that is, through the second substrate 40), thereby improving the heat dissipation efficiency and effect of the chip, thereby increasing the service life of the chip.

In some embodiments, the semiconductor device 10 to be packaged is injection molded with a second packaging material to fill the gap between the first substrate 20 and the second substrate 40 ; and the semiconductor device 10 to be packaged after injection molding is cured. , so that the semiconductor device 10 to be packaged is injection molded.

Specifically, as shown in FIG. 6 , the injection molding process of the semiconductor device 10 to be packaged using the second packaging material specifically includes: filling the gap between the first substrate 20 and the second substrate 40 with underfill glue, that is, filling the gap with the underfill glue. The glue is applied to the edge of the assembled device, and the "capillary effect" of the liquid is used to make the glue penetrate and fill the bottom of the semiconductor device 10 to be packaged, and then heated to solidify the injection-molded semiconductor device 10 to be packaged, so that the semiconductor device 10 to be packaged can be solidified. The semiconductor device 10 is injection molded, even if the filling glue, the semiconductor device 10 to be packaged, the first substrate 20 and the second substrate 40 are integrated, the electrical, thermal and mechanical connection between the chip and the first substrate 20 and the second substrate 40 is finally realized. connection, thereby obtaining the packaged semiconductor device 10, that is, the chip 100.

Among them, the chip packaging method (ie, steps S101-S105) provided by the above embodiment is to first perform surface packaging processing on the semiconductor device 10 to be packaged, and then perform flip-chip packaging processing.

Please refer to FIG. 7 , which is a schematic flowchart of a chip packaging method provided by another embodiment of the present application.

As shown in Figure 7, the chip packaging method specifically includes steps S201-S205.

S201. Provide a semiconductor device to be packaged, and form a bump structure on a side of the semiconductor device to be packaged facing away from the substrate.

S202. Provide a second substrate, attach the bump structure to the second substrate, and perform a flip-chip packaging process on the semiconductor device to be packaged and the second substrate.

S203. Perform a plastic packaging process on the semiconductor device to be packaged using a second packaging material, so that the semiconductor device to be packaged is injection molded.

S204. Provide a first substrate, where the first substrate includes a first bonding pad.

S205. Add a first packaging material to the surface of the first bonding pad to form an adhesive layer, attach the semiconductor device substrate to be packaged to the first bonding pad through the adhesive layer, and attach the substrate to the first bonding pad through the adhesive layer. The semiconductor device to be packaged and the first pad are subjected to surface packaging processing.

Among them, the chip packaging method (ie, steps S201-S205) provided by this embodiment is to first perform a flip-chip packaging process on the semiconductor device 10 to be packaged, and then perform a surface packaging process. This application provides two chip packaging methods (ie, steps S101-S105 and steps S201-S205). The packaging steps of the two are different, and the remaining specific implementation solutions are the same.

Please refer to FIG. 6 , which is a schematic structural diagram of a chip provided by an embodiment of the present application. Specifically, it can be obtained by packaging the semiconductor device 10 to be packaged using the chip packaging method as described above. The heat generated by the chip 100 can be simultaneously conducted to the outside world from the top of the chip 100 and the bottom of the chip 100, thereby improving the heat dissipation efficiency and effect of the chip 100, thereby increasing the service life of the chip 100.

The chip 100 includes a semiconductor device 10 , a first substrate 20 , a bump structure 30 , a second substrate 40 and a filling medium 50 . The first substrate 20 includes a first pad 21, which is connected to the substrate of the semiconductor device 10 through an adhesive layer 22; the bump structure 30 is provided on a side of the semiconductor device 10 facing away from the substrate; the second substrate 40 is connected to the side of the semiconductor device 10 away from the substrate through the bump structure 30; the filling medium 50 is used to fill the gap between the first substrate 20 and the second substrate 40 and encapsulate the semiconductor device 10.

The semiconductor device 10 may be a packaged wafer or die. Both the first substrate 20 and the second substrate 40 may be ceramics or printed circuit boards. The first substrate 20 includes a first bonding pad 21. The first bonding pad 21 may be a metal pad, specifically a metal pad with good thermal conductivity such as a copper pad, used to dissipate heat from the semiconductor device 10 to be packaged.

Specifically, the adhesive layer 22 may be formed by injecting a first packaging material onto the surface of the first bonding pad 21 to bond the substrate of the semiconductor device 10 to be packaged to the first bonding pad 21 . The first packaging material may include a soldering material for soldering the substrate of the semiconductor device 10 to be packaged to the first pad 21 .

The filling medium 50 can be obtained by plastically encapsulating the semiconductor device 10 with a second encapsulating material and injection molding, and is used to fill the gap between the first substrate 20 and the second substrate 40 . The second packaging material may be a plastic packaging material or the like.

In some embodiments, the thermal conductivity of the first packaging material is greater than the thermal conductivity of the second packaging material.

Among them, the thermal conductivity of the plastic packaging material is 50W/m.k, and the second packaging material is a material with a smaller thermal conductivity such as plastic packaging material. The existing packaging technology generally fixes the chip 100 to the corresponding heat-dissipation chip carrier. In this way, although the side of the chip 100 and the heat-dissipation chip carrier can be used for heat dissipation, since the chip 100 and the heat-dissipation chip carrier The side facing away from the chip 100 and the heat-dissipating chip carrier cannot be dissipated in time. The heat dissipation effect will be limited by the packaging material, which greatly reduces the heat dissipation effect and lowers the heat dissipation efficiency.

Since the thermal conductivity of the packaging material is very low, the problems of low heat dissipation and low heat dissipation efficiency in the existing packaging method can be solved by replacing the packaging material with a lower thermal conductivity with a material with a higher thermal conductivity. That is, the first packaging material is added to the surface of the first pad 21 to form the adhesive layer 22, and the first substrate 20 and the second substrate 40 are used to transfer the heat emitted by the chip 100 from above the chip 100 (i.e., through the first substrate 20) The heat dissipation efficiency and heat dissipation effect of the chip 100 are improved and the service life of the chip 100 is improved.

It should be understood that the terminology used in the specification of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

It will also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations. It should be noted that, as used herein, the terms "include", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or system that includes a list of elements not only includes those elements, but It also includes other elements not expressly listed or that are inherent to the process, method, article or system. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

The above serial numbers of the embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments. The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of various equivalent methods within the technical scope disclosed in the present application. Modification or replacement, these modifications or replacements shall be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A chip packaging method, characterized in that the method includes:

providing a semiconductor device to be packaged and a first substrate, the first substrate including a first bonding pad;

Adding a first packaging material to the surface of the first bonding pad to form an adhesive layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the adhesive layer, and attaching the substrate to the first bonding pad. The semiconductor device to be packaged and the first pad are subjected to surface packaging processing;

Form a bump structure on the side of the semiconductor device to be packaged facing away from the substrate;

Provide a second substrate, attach the bump structure to the second substrate, and perform a flip-chip packaging process on the semiconductor device to be packaged and the second substrate;

The semiconductor device to be packaged is subjected to a plastic packaging process through a second packaging material.
The method of claim 1, wherein the thermal conductivity of the first packaging material is greater than the thermal conductivity of the second packaging material.
The method according to claim 1, wherein the surface packaging includes QFN packaging or DFN packaging; the flip-chip packaging includes Flip-Chip packaging or FC-BGA packaging.
The method of claim 1, wherein the first packaging material is added to the surface of the first pad to form an adhesive layer, and the semiconductor device to be packaged is sealed through the adhesive layer. The substrate is attached to the first bonding pad, and surface packaging processing is performed on the semiconductor device to be packaged and the first bonding pad, including:

Print the first packaging material on the first pad to form an adhesive layer, and place the substrate of the semiconductor device to be packaged on the adhesive layer;

The substrate of the semiconductor device to be packaged is soldered to the first bonding pad, so that the substrate of the semiconductor device to be packaged is packaged on the first bonding pad.
The method of claim 1, wherein the bump structure is attached to the second substrate, and the semiconductor device to be packaged and the second substrate are flip-chip packaged, include:

forming a second pad corresponding to the bump structure on the surface of the second substrate;

Perform alignment and patch processing on the bump structure and the corresponding second pad;

The semiconductor device to be packaged is inverted on the second substrate, and the bump structure is soldered to the corresponding second pad, so that the bump structure forms a solder ball and passes through the solder balls and The second substrate is connected.
The method of claim 1, wherein the plastic packaging process of the semiconductor device to be packaged using a second packaging material includes:

Perform an injection molding process on the semiconductor device to be packaged through the second packaging material to fill the gap between the first substrate and the second substrate;

The injection-molded semiconductor device to be packaged is cured so that the semiconductor device to be packaged is injection molded.
The method according to any one of claims 1 to 6, characterized in that the first packaging material includes welding material, and the second packaging material includes plastic packaging material.
The method according to any one of claims 1 to 6, characterized in that the first substrate and the second substrate are ceramics or printed circuit boards.
A chip packaging method, characterized in that the method includes:

Provide a semiconductor device to be packaged, and form a bump structure on a side of the semiconductor device to be packaged facing away from the substrate;

Provide a second substrate, attach the bump structure to the second substrate, and perform a flip-chip packaging process on the semiconductor device to be packaged and the second substrate;

Perform a plastic packaging process on the semiconductor device to be packaged through a second packaging material, so that the semiconductor device to be packaged is injection molded;

providing a first substrate, the first substrate including a first pad;

Adding a first packaging material to the surface of the first bonding pad to form an adhesive layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the adhesive layer, and attaching the substrate to the first bonding pad. The semiconductor device to be packaged and the first pad are subjected to surface packaging processing.
A chip, characterized in that the chip includes:

Semiconductor device;

a first substrate, the first substrate including a first pad connected to the substrate of the semiconductor device through an adhesive layer;

A bump structure arranged on the side of the semiconductor device facing away from the substrate;

a second substrate, the second substrate is separated from the substrate by the bump structure and the semiconductor device; One side connection;

Filling medium is used to fill the gap between the first substrate and the second substrate and encapsulate the semiconductor device.