CN115116860A - Chip packaging method and chip - Google Patents
Chip packaging method and chip Download PDFInfo
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- CN115116860A CN115116860A CN202210689679.4A CN202210689679A CN115116860A CN 115116860 A CN115116860 A CN 115116860A CN 202210689679 A CN202210689679 A CN 202210689679A CN 115116860 A CN115116860 A CN 115116860A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Abstract
The application discloses a chip packaging method and a chip, and relates to the technical field of packaging. The method comprises the following steps: providing a semiconductor device to be packaged and a first substrate, wherein the first substrate comprises a first bonding pad; injecting a first packaging material to the surface of the first bonding pad to form a bonding layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad; forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from the substrate; providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate; and carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material. The embodiment of the application aims at improving the heat dissipation efficiency and the heat dissipation effect of the chip, so that the service life of the chip is prolonged.
Description
Technical Field
The present disclosure relates to the field of packaging technologies, and in particular, to a chip packaging method and a chip.
Background
For a high-power chip, because the power of the chip is high, the temperature of the chip rises during working, in the prior art, people generally apply a heat radiating fin to the surface of the packaged chip to radiate heat, however, because the coefficient of heat conductivity of the packaging material wrapping the chip is very low, most of heat emitted by the chip cannot be conducted to the outside, the service life of the chip is shortened, and even the chip is burnt out. Therefore, the heat dissipation effect of the conventional chip heat dissipation scheme is limited by the packaging material, so that the heat dissipation effect is greatly reduced, and the heat dissipation efficiency is low.
Disclosure of Invention
The application provides a chip packaging method and a chip, aiming at improving the heat dissipation efficiency and the heat dissipation effect of the chip, so that the service life of the chip is prolonged.
In a first aspect, an embodiment of the present application provides a chip packaging method, where the method includes:
providing a semiconductor device to be packaged and a first substrate, wherein the first substrate comprises a first bonding pad;
injecting a first packaging material to the surface of the first bonding pad to form a bonding layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad;
forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from the substrate;
providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate;
and carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material.
In a second aspect, an embodiment of the present application further provides a chip packaging method, where the method includes:
providing a semiconductor device to be packaged, and forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from a substrate;
providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate;
carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material so as to enable the semiconductor device to be packaged to be subjected to injection molding;
providing a first substrate, wherein the first substrate comprises a first bonding pad;
and filling a first packaging material on the surface of the first bonding pad to form a bonding layer, bonding the semiconductor device substrate to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad.
In a third aspect, an embodiment of the present application further provides a chip, where the chip includes:
a semiconductor device;
a first base plate including a first pad connected to a substrate of the semiconductor device through an adhesive layer;
the bump structure is arranged on one surface of the semiconductor device, which is far away from the substrate;
the second substrate is connected with one surface of the chip, which is far away from the substrate, through the bump structure;
and the filling medium is used for filling the gap between the first substrate and the second substrate and packaging the semiconductor device.
The embodiment of the application provides a chip packaging method and a chip, wherein the method comprises the following steps: providing a semiconductor device to be packaged and a first substrate, wherein the first substrate comprises a first bonding pad; injecting a first packaging material to the surface of the first bonding pad to form a bonding layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad; forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from the substrate; providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate; carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material; therefore, the limitation of the low heat conductivity of the packaging material can be avoided, the heat emitted by the chip can be conducted to the outside from the upper part of the chip and the lower part of the chip at the same time, the heat dissipation efficiency and the heat dissipation effect of the chip are improved, and the service life of the chip is prolonged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a chip packaging method according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a first bonding pad according to an embodiment of the present application;
fig. 3 is a schematic partial structure diagram of a surface package in a chip packaging method according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a bump structure according to an embodiment of the present application;
fig. 5 is a schematic view of a flip-chip packaging scenario in a chip packaging method according to an embodiment of the present application;
FIG. 6 is a schematic structural diagram of a chip according to an embodiment of the present disclosure;
fig. 7 is a schematic flowchart of a chip packaging method according to another embodiment of the present application;
reference numerals are as follows:
100. chip and method for manufacturing the same
10. A semiconductor device;
20. a first substrate; 21. a first pad; 22. an adhesive layer;
30. a bump structure; 31. a bump metal layer; 32. a solder ball;
40. a second substrate; 41. a second bonding pad;
50. and filling the medium.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The flow diagrams depicted in the figures are merely illustrative and do not necessarily include all of the elements and operations/steps, nor do they necessarily have to be performed in the order depicted. For example, some operations/steps may be decomposed, combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It is to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The chip packaging technology is a process technology for wrapping a memory chip to avoid the chip from contacting with the outside and prevent the chip from being damaged by the outside. Impurities and undesirable gases in the air, and even water vapor, can corrode the precision circuitry on the chip, thereby causing degradation of electrical performance. Different packaging technologies are widely different in manufacturing processes and technologies, and play a crucial role in performance of the memory chip after packaging.
The conventional packaging technology can be generally divided into through hole type packaging, surface mount type packaging and the like, the temperature of a chip rises due to work, in the prior art, people generally apply a radiating fin to the surface of the packaged chip for radiating, however, the heat conductivity coefficient of the packaging material wrapping the chip is generally very low, the heat emitted by the chip cannot be well conducted to the outside for radiating, so that the radiating effect can be limited by the packaging material, and the radiating effect is greatly reduced.
The embodiment of the application provides a chip packaging method and a chip, which can avoid being limited by low thermal conductivity of packaging materials, can conduct heat emitted by the chip to the outside from the upper part and the lower part of the chip simultaneously, and improves the heat dissipation efficiency and the heat dissipation effect of the chip, thereby prolonging the service life of the chip.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a chip packaging method according to an embodiment of the present application.
As shown in fig. 1, the chip packaging method specifically includes steps S101-S105.
S101, providing a semiconductor device to be packaged and a first substrate, wherein the first substrate comprises a first bonding pad.
As shown in fig. 2, the semiconductor device 10 to be packaged is an unpackaged die (i.e., die), which may be an unpackaged wafer or die, where the wafer refers to a silicon wafer used for manufacturing a silicon semiconductor integrated circuit; various circuit element structures can be processed on a silicon wafer to form an integrated circuit product with specific electrical functions.
Since the material of the semiconductor device 10 to be packaged is silicon, which has a thermal conductivity of 118W/m.k, which is 100W/m.k or more, the semiconductor device 10 to be packaged conducts heat well.
As shown in fig. 2, the first substrate 20 may be a ceramic or Printed Circuit Board (PCB). The first substrate 20 includes a first bonding pad 21, and the first bonding pad 21 may be a metal bonding pad, specifically, a metal bonding pad with good thermal conductivity such as a copper bonding pad, and is used for dissipating heat of the semiconductor device 10 to be packaged.
In some embodiments, the first pads 21 are formed on the surface of the first substrate 20.
Specifically, the surface of the first substrate 20 is configured to be disposed corresponding to a substrate of the semiconductor device 10 to be packaged, and the first pads 21 may be directly soldered on the first substrate 20. The first pads 21 serve to dissipate heat, which is generated when the chip is in operation. At this time, heat can be rapidly radiated to the entire first substrate 20 through the first pads 21, so that the heat dissipation area is increased and the heat dissipation speed is increased.
For example, the first pad 21 may be soldered at any position of the first substrate 20, and preferably, the first pad 21 may be soldered at a central position of the first substrate 20, as shown in fig. 2, the first substrate 20 has a shape of a Chinese character 'hui', and the first pad 21 is disposed at the central position of the first substrate 20. Thereby achieving better heat dissipation effect.
S102, injecting a first packaging material to the surface of the first bonding pad to form a bonding layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad.
Among them, the adhesive layer 22 may be formed by pouring a first packaging material to the surface of the first pad 21 for attaching the substrate of the semiconductor device 10 to be packaged to the first pad 21. The first packaging material may include a solder material for soldering the substrate of the semiconductor device 10 to be packaged onto the first pads 21. The substrate of the semiconductor device 10 to be packaged may be made of SiC, Si, or GaAs.
Specifically, the thermal conductivity of the solder material is 50W/m.k, so the solder material can conduct heat well and the adhesive layer 22 is formed of the solder material, i.e. the semiconductor device 10 to be packaged can conduct most of the heat emitted therefrom to the outside through the adhesive layer 22, thereby avoiding being limited by the low thermal conductivity of the packaging material and being capable of conducting the heat emitted from the chip to the outside from above the chip quickly.
Specifically, the surface Package includes a quad flat no-lead Package (QFN) or a DFN (dual flat no-lead Package) Package. Pins of the DFN package are distributed on two sides of the package body, the overall appearance of the package body is rectangular, and pins of the QFN package are distributed on four sides of the package body, and the overall appearance of the package body is square. QFN packages have the advantages of small size, light weight, good heat dissipation, good electrical performance, good reliability, high cost performance and the like, so QFN packages are generally selected.
In some embodiments, the first packaging material is printed on the first pads 21 to form an adhesive layer 22, and the substrate to be packaged with the semiconductor device 10 is attached on the adhesive layer 22; the substrate of the semiconductor device 10 to be packaged is soldered on the first pads 21, so that the substrate of the semiconductor device 10 to be packaged is packaged on the first pads 21. Therefore, the semiconductor device 10 to be packaged can conduct most of the heat emitted by the semiconductor device to be packaged to the outside through the adhesive layer 22, so that the limitation of low thermal conductivity of the packaging material is avoided, and the heat emitted by the chip can be conducted to the outside from the upper part of the chip quickly.
For example, since the thickness of a wafer from a typical wafer factory is about 550 to 725 micrometers, and the total thickness of a conventional QFN package is also 550 to 750 micrometers, the wafer cannot be placed therein without thinning. Therefore, it is necessary to perform lapping thinning processing on the wafer coming out from the wafer factory so as to obtain the semiconductor device 10 to be packaged, whereby the semiconductor device 10 to be packaged can be packaged in a limited space in a subsequent convenient manner. Specifically, the substrate of the wafer may be thinned by chemical mechanical polishing or laser cutting.
Generally, N independent functional bare chips (die) can be formed on a wafer, before packaging, the wafer can be diced, 1 bare chip is diced, and then each bare chip is bonded and packaged; or before packaging, the wafer is packaged, the protective layer can be adhered to the top or the bottom of the wafer, then the wafer is connected with a circuit, and then the wafer is cut into single chips, namely wafer-level packaging.
For the separated bare chip (die), the bare chip does not have pins at this time, and the bare chip needs to be placed on a metal carrier, because the metal carrier is provided with pins, and the metal carrier waits for the next bonding wire after being connected through silver paste or an adhesive film.
As shown in fig. 3, a first packaging material is printed on the first pad 21 to form an adhesive layer 22, the substrate of the semiconductor device 10 to be packaged is attached to the adhesive layer 22, so that the substrate of the semiconductor device 10 to be packaged is attached to the adhesive layer 22, and the substrate of the semiconductor device 10 to be packaged is then bonded to the first pad 21, so that the substrate of the semiconductor device 10 to be packaged is connected to the first pad 21, that is, the substrate of the semiconductor device 10 to be packaged is packaged on the first pad 21.
Specifically, the substrate of the semiconductor device 10 to be packaged is soldered to the first pads 21, and actually, the semiconductor device 10 to be packaged is subjected to wire bonding to connect the semiconductor device 10 to be packaged and the leads of the first pads 21. For example, an automatic wire bonding apparatus may be used to wire bond the functional Pad of the semiconductor device 10 to be packaged with the pins of the first bonding Pad 21, and connect the chip design function to the external circuit board through the frame pins, so as to ensure that the product can work properly when powered on.
And S103, forming a bump structure 30 on the surface of the semiconductor device to be packaged, which is far away from the substrate.
As shown in fig. 4, the bump structure 30 includes a bump metal layer 31 and a plurality of bumps on the bump metal layer 31. The bump metal layer 31 may be a Cu/Ni composite layer or a Ti/Cu composite layer.
Specifically, a Polybenzoxazole (PBO) layer may be formed on a surface of the semiconductor device 10 to be packaged away from the substrate, at least a portion of an opening is formed in the PBO layer, a first metal layer is deposited on the surface of the PBO layer and in the opening by using a Physical Vapor Deposition (PVD) method, a photoresist layer is formed on the surface of the first metal layer, a second metal layer is formed at a corresponding position in the photoresist layer by photolithography processes such as exposure and development, and the second metal layer is deposited at the opening, where the first metal layer and the second metal layer jointly serve as the bump metal layer 31; then, a plurality of bumps are plated on the bump metal layer 31, so that a bump structure 30 is formed on the side, away from the substrate, of the semiconductor device 10 to be packaged.
Illustratively, a planar process may be used to make lead-free solder joints at the input/output (I/O) terminals of an integrated circuit chip.
S104, providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate.
The second substrate 40 may be a ceramic or a printed circuit board. The Flip Chip package includes a Flip Chip technology (Flip-Chip) or a Flip Chip Ball Grid Array (FC-BGA) package.
Flip-Chip packaging interconnects the second substrate 40 with bumps (i.e., bumps) by flipping the functional region of the Chip downward and back to the substrate, with the Chip placed in the opposite direction from the functional region of the conventional package upward. The Flip-Chip package has the advantages of small size, thin thickness, light weight, higher density, better radio frequency performance, strong heat dissipation capability and the like.
Referring to fig. 5, in some embodiments, a second pad 41 corresponding to the bump structure 30 is formed on a surface of the second substrate 40; aligning and mounting the bump structure 30 and the corresponding second bonding pad 41; the bump structure 30 is inverted on the second substrate 40, and the bump structure 30 is soldered to the corresponding second pad 41, so that the bump structure 30 forms a solder ball 32 and is connected to the second substrate 40 through the solder ball 32. Therefore, the semiconductor device 10 to be packaged can conduct most of heat emitted by the second substrate 40 to the outside through the second substrate, limitation of low thermal conductivity of packaging materials is avoided, the heat emitted by the chip can be conducted to the outside from the upper side and the lower side of the chip at the same time, the heat dissipation efficiency and the heat dissipation effect of the chip are improved, and the service life of the chip is prolonged.
The second bonding pad 41 may be a metal bonding pad, specifically, a metal bonding pad with good thermal conductivity such as a copper bonding pad, and is used for dissipating heat of the semiconductor device 10 to be packaged.
Specifically, the second pad 41 corresponding to the bump structure 30 is formed on the surface of the second substrate 40, and the second pad 41 may be directly soldered on the second substrate 40. The second pads 41 function to dissipate heat, which is generated when the chip is in operation. At this time, heat can be rapidly radiated to the entire second substrate 40 through the second pad 41, so that the heat dissipation area is increased and the heat dissipation speed is increased.
Illustratively, as shown in fig. 4 and 5, the bump on the bump structure 30 and the second pad 41 on the second substrate 40 are aligned and subjected to a mounting process, then the semiconductor device 10 to be packaged is inverted on the second substrate 40, that is, the bump structure 30 and the second substrate 40 are arranged in a facing manner, and finally the solder ball 32 is formed between the surface of the semiconductor device 10 to be packaged, which faces away from the substrate, and the second substrate 40 by using a solder reflow process. Specifically, the photoresist layer is removed, the excess first metal layer on the surface of the PBO layer is removed by wet etching, and then a reflow process is performed, so that the bump is rounded into the solder ball 32.
And S105, carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material.
The second packaging material may be a plastic packaging material, and the semiconductor device 10 to be packaged is subjected to plastic packaging treatment through the plastic packaging material so as to fill a gap between the first substrate 20 and the second substrate 40.
Illustratively, the plastic package may be an Epoxy molding compound (Epoxy molding compound) package. Wherein, EMC is a Thermosetting plastic (Thermosetting plastic), is one of common packaging materials for semiconductor packaging, and comprises the main components of filler, epoxy resin, curing agent, coupling agent, flame retardant, mold release agent, modified additive and the like; the filler content is the highest, and parameters and properties of the epoxy resin can be improved, such as reduction of expansion coefficient, improvement of thermal conductivity, increase of elastic modulus and the like.
In some embodiments, the first encapsulant material has a thermal conductivity greater than a thermal conductivity of the second encapsulant material.
The heat conductivity coefficient of the plastic packaging material is 50W/m.k, and the second packaging material is a material with a smaller heat conductivity coefficient, such as a plastic packaging material. The conventional packaging technology generally fixes the chip on the corresponding heat dissipation type chip carrier, so that although the chip can be attached to the heat dissipation type chip carrier for heat dissipation, the surface of the chip, which deviates from the heat dissipation type chip carrier, is wrapped by the plastic package material, so that the surface of the chip, which deviates from the heat dissipation type chip carrier, cannot be subjected to heat dissipation in time, the heat dissipation effect is limited by the packaging material, the heat dissipation effect is greatly reduced, and the heat dissipation efficiency is low.
And because the thermal conductivity coefficient of the packaging material is very low, the packaging material with lower thermal conductivity coefficient can be replaced by the material with higher thermal conductivity coefficient, so that the problems of lower heat dissipation effect and lower heat dissipation efficiency in the existing packaging method are solved. That is, by filling the first packaging material on the surface of the first bonding pad 21 to form the adhesive layer 22, and simultaneously conducting the heat emitted by the chip from the top of the chip (i.e., through the first substrate 20) and from the bottom of the chip (i.e., through the second substrate 40) to the outside by using the first substrate 20 and the second substrate 40, the heat dissipation efficiency and the heat dissipation effect of the chip are improved, and the service life of the chip is prolonged.
In some embodiments, the semiconductor device 10 to be packaged is subjected to an injection molding process by a second packaging material to fill a gap between the first substrate 20 and the second substrate 40; and curing the injection-molded semiconductor device 10 to be packaged so as to injection mold the semiconductor device 10 to be packaged.
Specifically, as shown in fig. 6, the injection molding of the semiconductor device 10 to be packaged by the second packaging material specifically includes: filling underfill in a gap between the first substrate 20 and the second substrate 40, that is, coating the underfill on the edge of the assembled device, filling the bottom of the semiconductor device 10 to be packaged with the underfill by using a "capillary effect" of liquid, and then heating to cure the injection-molded semiconductor device 10 to be packaged, so that the semiconductor device 10 to be packaged is injection-molded, that is, the underfill is integrated with the semiconductor device 10 to be packaged, the first substrate 20 and the second substrate 40, and finally the electrical, thermal and mechanical connection between the chip and the first substrate 20 and the second substrate 40 is achieved, thereby obtaining the packaged semiconductor device 10, that is, the chip 100.
In the chip packaging method (i.e., steps S101 to S105) provided in the above embodiment, the surface packaging process is performed on the semiconductor device 10 to be packaged, and then the flip-chip packaging process is performed.
Referring to fig. 7, fig. 7 is a schematic flowchart illustrating a chip packaging method according to another embodiment of the present application.
As shown in fig. 7, the chip packaging method specifically includes steps S201 to S205.
S201, providing a semiconductor device to be packaged, and forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from the substrate.
S202, providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate.
S203, carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material so as to enable the semiconductor device to be packaged to be subjected to injection molding.
S204, providing a first substrate, wherein the first substrate comprises a first bonding pad.
S205, injecting a first packaging material to the surface of the first bonding pad to form a bonding layer, bonding the to-be-packaged semiconductor device substrate to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the to-be-packaged semiconductor device and the first bonding pad.
In the chip packaging method (i.e., steps S201 to S205) provided in this embodiment, the semiconductor device 10 to be packaged is flip-chip packaged first, and then surface packaging is performed. The application provides two chip packaging methods (i.e. steps S101-S105 and steps S201-S205), the packaging steps of the two methods are different, and the rest of specific implementation schemes are the same.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a chip according to an embodiment of the present application. Specifically, the semiconductor device 10 to be packaged can be obtained by packaging the semiconductor device 10 by the chip packaging method as described above. The heat generated by the chip 100 can be conducted to the outside from the top of the chip 100 and the bottom of the chip 100, so as to improve the heat dissipation efficiency and the heat dissipation effect of the chip 100, and further improve the service life of the chip 100.
The chip 100 includes a semiconductor device 10, a first substrate 20, a bump structure 30, a second substrate 40, and a filling medium 50. Wherein the first substrate 20 includes a first pad 21, and the first pad 21 is connected to the substrate of the semiconductor device 10 through an adhesive layer 22; the bump structure 30 is disposed on a side of the semiconductor device 10 facing away from the substrate; the second substrate 40 is connected to the side of the semiconductor device 10 away from the substrate through the bump structure 30; the filling medium 50 is used to fill the gap between the first substrate 20 and the second substrate 40 and to encapsulate the semiconductor device 10.
The semiconductor device 10 may be a packaged wafer or die, among others. The first substrate 20 and the second substrate 40 may be ceramic or printed circuit boards. The first substrate 20 includes a first bonding pad 21, and the first bonding pad 21 may be a metal bonding pad, specifically, a metal bonding pad with good thermal conductivity such as a copper bonding pad, and is used for dissipating heat of the semiconductor device 10 to be packaged.
Specifically, the adhesive layer 22 may be formed by pouring a first packaging material to the surface of the first pad 21 for attaching the substrate of the semiconductor device 10 to be packaged to the first pad 21. The first packaging material may include a solder material for soldering the substrate of the semiconductor device 10 to be packaged onto the first pads 21.
The filling medium 50 may be obtained by plastic-encapsulating and injection-molding the semiconductor device 10 with a second encapsulation material, and is used for filling the gap between the first substrate 20 and the second substrate 40. The second packaging material may be a plastic packaging material or the like.
In some embodiments, the first encapsulant material has a thermal conductivity greater than a thermal conductivity of the second encapsulant material.
The heat conductivity coefficient of the plastic packaging material is 50W/m.k, and the second packaging material is a material with a smaller heat conductivity coefficient, such as a plastic packaging material. In the conventional packaging technology, the chip 100 is generally fixed to the corresponding heat dissipation type chip carrier, so that although heat can be dissipated by using the surface of the chip 100 attached to the heat dissipation type chip carrier, the surface of the chip 100 away from the heat dissipation type chip carrier is wrapped by the plastic packaging material, so that the surface of the chip 100 away from the heat dissipation type chip carrier cannot dissipate heat in time, the heat dissipation effect is limited by the packaging material, the heat dissipation effect is greatly reduced, and the heat dissipation efficiency is low.
And because the thermal conductivity coefficient of the packaging material is very low, the packaging material with lower thermal conductivity coefficient can be replaced by the material with higher thermal conductivity coefficient, so that the problems of lower heat dissipation effect and lower heat dissipation efficiency in the existing packaging method are solved. That is, by filling the first packaging material on the surface of the first pad 21 to form the adhesive layer 22, and simultaneously conducting the heat emitted from the chip 100 to the outside from the upper side of the chip 100 (i.e., through the first substrate 20) and the lower side of the chip 100 (i.e., through the second substrate 40) by using the first substrate 20 and the second substrate 40, the heat dissipation efficiency and the heat dissipation effect of the chip 100 are improved, and thus the service life of the chip 100 is prolonged.
It is to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or system in which the element is included.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments. While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and various equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method of chip packaging, the method comprising:
providing a semiconductor device to be packaged and a first substrate, wherein the first substrate comprises a first bonding pad;
injecting a first packaging material to the surface of the first bonding pad to form a bonding layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad;
forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from the substrate;
providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate;
and carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material.
2. The method of claim 1, wherein the first encapsulant material has a thermal conductivity greater than a thermal conductivity of the second encapsulant material.
3. The method of claim 1, wherein the surface package comprises a QFN package or a DFN package; the Flip-Chip package comprises a Flip-Chip package or an FC-BGA package.
4. The method of claim 1, wherein the injecting a first packaging material to the surface of the first pad to form an adhesive layer, attaching a substrate of the semiconductor device to be packaged to the first pad through the adhesive layer, and performing a surface packaging process on the semiconductor device to be packaged and the first pad comprises:
printing the first packaging material on the first bonding pad to form a bonding layer, and attaching the substrate of the semiconductor device to be packaged on the bonding layer;
and welding the substrate of the semiconductor device to be packaged on the first bonding pad so as to package the substrate of the semiconductor device to be packaged on the first bonding pad.
5. The method of claim 1, wherein the attaching the bump structure to the second substrate and flip-chip packaging the semiconductor device to be packaged and the second substrate comprises:
forming a second bonding pad corresponding to the bump structure on the surface of the second substrate;
aligning and mounting the bump structure and the corresponding second bonding pad;
and inverting the semiconductor device to be packaged on the second substrate, and welding the bump structure on the corresponding second bonding pad to form a solder ball on the bump structure, and connecting the solder ball with the second substrate.
6. The method of claim 1, wherein the plastic packaging the semiconductor device to be packaged by the second packaging material comprises:
performing injection molding treatment on the semiconductor device to be packaged through the second packaging material to fill a gap between the first substrate and the second substrate;
and curing the semiconductor device to be packaged after injection molding so as to injection mold the semiconductor device to be packaged.
7. The method of any of claims 1-6, wherein the first encapsulant material comprises a solder material and the second encapsulant material comprises a mold compound.
8. The method of any of claims 1-6, wherein the first substrate and the second substrate are ceramic or printed circuit boards.
9. A method of chip packaging, the method comprising:
providing a semiconductor device to be packaged, and forming a bump structure on one surface of the semiconductor device to be packaged, which is far away from a substrate;
providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip packaging processing on the semiconductor device to be packaged and the second substrate;
carrying out plastic packaging treatment on the semiconductor device to be packaged through a second packaging material so as to enable the semiconductor device to be packaged to be subjected to injection molding;
providing a first substrate, wherein the first substrate comprises a first bonding pad;
and filling a first packaging material on the surface of the first bonding pad to form a bonding layer, attaching the substrate of the semiconductor device to be packaged to the first bonding pad through the bonding layer, and carrying out surface packaging treatment on the semiconductor device to be packaged and the first bonding pad.
10. A chip, wherein the chip comprises:
a semiconductor device;
a first base plate including a first pad connected to a substrate of the semiconductor device through an adhesive layer;
the bump structure is arranged on one surface of the semiconductor device, which is far away from the substrate;
the second substrate is connected with one surface of the semiconductor device, which is far away from the substrate, through the bump structure;
and the filling medium is used for filling the gap between the first substrate and the second substrate and packaging the semiconductor device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210689679.4A CN115116860A (en) | 2022-06-17 | 2022-06-17 | Chip packaging method and chip |
| PCT/CN2023/095076 WO2023241304A1 (en) | 2022-06-17 | 2023-05-18 | Chip packaging methods and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210689679.4A CN115116860A (en) | 2022-06-17 | 2022-06-17 | Chip packaging method and chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115116860A true CN115116860A (en) | 2022-09-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210689679.4A Pending CN115116860A (en) | 2022-06-17 | 2022-06-17 | Chip packaging method and chip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115116860A (en) |
| WO (1) | WO2023241304A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023241304A1 (en) * | 2022-06-17 | 2023-12-21 | 北京比特大陆科技有限公司 | Chip packaging methods and chip |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3597754B2 (en) * | 2000-04-24 | 2004-12-08 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP4390541B2 (en) * | 2003-02-03 | 2009-12-24 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| TWI228806B (en) * | 2003-05-16 | 2005-03-01 | Advanced Semiconductor Eng | Flip chip package |
| US7968999B2 (en) * | 2008-02-28 | 2011-06-28 | Lsi Corporation | Process of grounding heat spreader/stiffener to a flip chip package using solder and film adhesive |
| US8237257B2 (en) * | 2008-09-25 | 2012-08-07 | King Dragon International Inc. | Substrate structure with die embedded inside and dual build-up layers over both side surfaces and method of the same |
| US8247900B2 (en) * | 2009-12-29 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Flip chip package having enhanced thermal and mechanical performance |
| CN115116860A (en) * | 2022-06-17 | 2022-09-27 | 北京比特大陆科技有限公司 | Chip packaging method and chip |
-
2022
- 2022-06-17 CN CN202210689679.4A patent/CN115116860A/en active Pending
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2023
- 2023-05-18 WO PCT/CN2023/095076 patent/WO2023241304A1/en unknown
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023241304A1 (en) * | 2022-06-17 | 2023-12-21 | 北京比特大陆科技有限公司 | Chip packaging methods and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023241304A1 (en) | 2023-12-21 |
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