TWI297538B - Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof - Google Patents

Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof Download PDF

Info

Publication number
TWI297538B
TWI297538B TW092119210A TW92119210A TWI297538B TW I297538 B TWI297538 B TW I297538B TW 092119210 A TW092119210 A TW 092119210A TW 92119210 A TW92119210 A TW 92119210A TW I297538 B TWI297538 B TW I297538B
Authority
TW
Taiwan
Prior art keywords
wafer
heat
wafer carrier
carrier
heat sink
Prior art date
Application number
TW092119210A
Other languages
Chinese (zh)
Other versions
TW200503210A (en
Inventor
Chin Te Chen
Chang Fu Lin
Shih Kuang Chiu
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Priority to TW092119210A priority Critical patent/TWI297538B/en
Publication of TW200503210A publication Critical patent/TW200503210A/en
Application granted granted Critical
Publication of TWI297538B publication Critical patent/TWI297538B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

1297538 五、發明說明（1) 【發明所屬之技術領域】 一種具高散熱高電性之堆疊式半導體晶片封裝件及其 製法，係有關於一種於兩晶片間置入一散熱件之半導體封 裝件及其製法。 【先前技術】 由於電子產品之微小化以及高運作速度需求的增加， 為求提昇單一半導體封裝件之性能與容量以符合電子產品 小型化、大容量與高速化之趨勢，將半導體封裝件以堆疊 式（stacked)晶片的形式呈現，此種封裝件得縮減整體 體積並得提昇電性功能，遂成為一種封裝的主流。 具堆疊式晶片之半導體封裝件係在單一封裝件之晶片 承載件上接置並電性連接有至少兩個以上的半導體晶片， 且晶片與晶片承載件間之接置方式為將半導體晶片——垂 直疊接於該晶片承載件上。 Φ 請參閱第1圖如美國專利第5，8 1 5，3 7 2號所揭露之一堆 疊式球栅陣列式（Ball Grid Array; BGA)半導體封裝件 1之剖面示意圖，如圖所示.，該封裝件1具有一藉由覆晶 (f 1 ip chip).形式接置於基板10之第一晶片11，一第二 晶片1 2透過一黏著層1 3接置於該第一晶片1 1之上，而該第 二晶片12則是透過鋅線連接（wire bonding)形式，藉由 接置於數個銲墊1 2 a上的複數條銲線1 4，電性連接至該基 板1 0之複數個銲墊1 0 a上，俾使該第二晶片1 2包括電源 (power)、接地（ground)及訊號（signal)得透過該 基板1 0中的複數條導電跡線1 0 b，以及接置於該基板1 0之1297538 V. Technical Description of the Invention (1) A stacked semiconductor chip package having high heat dissipation and high electric power, and a method for manufacturing the same, relating to a semiconductor package in which a heat dissipating member is interposed between two wafers And its method of production. [Prior Art] Due to the miniaturization of electronic products and the increasing demand for high operating speed, in order to improve the performance and capacity of a single semiconductor package to meet the trend of miniaturization, large capacity, and high speed of electronic products, semiconductor packages are stacked. In the form of a stacked wafer, such a package has to reduce the overall volume and enhance the electrical function, which becomes the mainstream of a package. A semiconductor package having a stacked wafer is connected to and electrically connected to at least two semiconductor wafers on a wafer carrier of a single package, and the wafer and the wafer carrier are connected to each other by a semiconductor wafer. Vertically spliced on the wafer carrier. Φ See Figure 1 for a cross-sectional view of a stacked ball grid array (BGA) semiconductor package 1 as disclosed in U.S. Patent No. 5,8,5,3,7, 2, which is incorporated herein by reference. The package 1 has a first wafer 11 attached to the substrate 10 by a flip chip, and a second wafer 12 is placed on the first wafer 1 through an adhesive layer 13. 1 , and the second wafer 12 is electrically connected to the substrate 1 by a wire bonding form by a plurality of bonding wires 14 connected to the plurality of pads 1 2 a. The plurality of pads 1 0 a, the second wafer 1 2 includes a power, a ground, and a signal to pass through the plurality of conductive traces 10 b in the substrate 10 And the substrate 10

17364石夕品.ptd 第9頁 1297538 .，五、發明說明（2) 複數個銲球1 5，與如印刷電路板等之外部裝置電性連接。 之後，再透過一封裝膠體1 6將前述之構件加以封裝成一封 裝件。 然而前述習知的半導體封裝件1，其基板1 0上所接置 並電性連接之該第一晶片1 1與該第二晶片1 2間，係以藉由 該黏著層13以背對背（back to back)，亦即，以非作用 表面對非作用表面之方式相互連接，此種習知技術雖然解 決了部分以覆晶形式接合晶片與銲線接合式晶片以堆疊之 方式置於一封裝件中的問題。但是此種封裝結構卻有至少 兩，顯著之缺點。其一係為該等半導體晶片透過間隔一黏 著λ之背對背方式相互連接，會導致該等半導體晶片於運 作時所產生之熱能無法有效的逸散，如此，該等半導體晶 片不但無法有效逸散其晶片本身所產生的熱能，此外復會 受到另一半導體晶片所散發出熱量的影響，進而造成半導 體晶片運作效能降低甚至損毀的情況發生。其二則係為前 述之封裝結構並不具有提供該等半導體晶片背面接地之功 能，無,法有效提昇該等晶片之電性品質。 綜上所述.，一種得應用於背對背形式堆疊之多晶片封 裝件中，藉以提供該封裝件中之複數個半導體晶片除得有 效i散其本身於運作時所產生的熱能外，復得提供該等半 導體晶片藉由接地元件電性連接至晶片承載件，俾達到提 昇該封裝件電性品質之具高散熱高電性之堆疊式半導體晶 片封裝件及其製法，遂成為目前亟待解決之問題。. 【發明内容】17364 石夕品.ptd Page 9 1297538 ., V. Description of the invention (2) A plurality of solder balls 15 are electrically connected to an external device such as a printed circuit board. Thereafter, the aforementioned components are packaged into a package by an encapsulant 16. However, the conventional semiconductor package 1 is disposed between the first wafer 11 and the second wafer 12 on the substrate 10 and electrically connected by the adhesive layer 13 back to back. To back), that is, the non-acting surface is connected to each other in an inactive surface manner. This prior art solves the problem that a portion of the wafer is bonded in a flip chip form and the wire bond wafer is stacked in a package. The problem in . However, this package structure has at least two, significant disadvantages. The semiconductor wafers are interconnected in a back-to-back manner through a gap λ, which causes the thermal energy generated by the semiconductor wafers to be effectively dissipated during operation, so that the semiconductor wafers cannot effectively dissipate them. The thermal energy generated by the wafer itself is further affected by the heat emitted by the other semiconductor wafer, which causes the semiconductor wafer to operate in a degraded or even damaged state. The second is that the package structure described above does not have the function of providing grounding of the back surface of the semiconductor wafers, and the method effectively improves the electrical quality of the wafers. In summary, one can be applied to a multi-chip package in a back-to-back stack, in order to provide a plurality of semiconductor wafers in the package, in addition to effectively dissipating the heat energy generated by the operation itself, The semiconductor wafer is electrically connected to the wafer carrier by the grounding member, and the stacked semiconductor chip package with high heat dissipation and high electrical conductivity for improving the electrical quality of the package and the method for manufacturing the same are becoming urgent problems to be solved. . [Content of the Invention]

17364矽品.ptd 第10頁 1297538 五、發明說明（3) 為解決以上所述習知 在於提供一種具高散熱高 及其製法，透過於以背對 熱件之方式，藉以讓該等 得有效的加以逸散。 本發明之又一目的在 技術之缺點，本發明之主要目的 電性之堆疊式半導體晶片封裝件 背接置之半導體晶片間接置一散 半導體晶片於運作時所生的熱能 璺式半導體晶片 半導體晶片間接 件之方式，藉以 接至該封裝件， 為達成以上 電性之堆疊式半 導體封裝件電性 載件形成有至少 置區、至少一用 形成接地迴路之 pad)與銲線墊 封裝件及 置一電性 讓該等半 俾提南該 所述及其 導體晶片 連接外部 一用以接 以與該電 接地區、 (finger) 於提供一種具高散熱高電性之堆 其製法，透過於以背對背接置之 連接至晶片承載件接地區的散熱 導體晶片得透過接地迴路電性連 封裝件本身電性品質。 的佈線層；至少一藉由覆 片接置區的第一晶片；一 他之目的，本發明之具高散熱高 封裝件包括有：一用以提供該半 之晶片承載件，其中，該晶片承 置並電性連接電子元件之晶片接 子元件及該外部裝置電性連接俾 複數個銲球銲墊（s ο 1 d e r b a 1 1 以及一佈設有複數之導電跡線 晶形式接置於該晶片承載件之晶 跨置於該第一晶片上並透過一具 有良好導電效果之導電膠，如銀膠等，與該晶片承載件之 接地區電性連接之散熱件；一形成於該第一晶片與該散熱 件之間且具有良好導熱與導電效果之傳導層；至少一以非 作用表面接置於一具有良好導熱效果黏著層上，俾透過該 黏著層與該散熱件相互連接，並藉由銲線接合形式與該晶17364矽品.ptd Page 10 1297538 V. INSTRUCTIONS (3) In order to solve the above, it is known to provide a high heat dissipation height and a method for manufacturing the same, which is effective in the way of backing the hot parts. Take it apart. A further object of the present invention is the disadvantage of the present invention. The main purpose of the present invention is to electrically place a stacked semiconductor chip package with a semiconductor wafer that is in contact with a semiconductor wafer in operation. The method of indirect parts is connected to the package, and at least one of the electrical components of the stacked semiconductor package for achieving the above electrical conductivity is formed with at least one pad, at least one pad for forming a ground loop, and a wire pad package and Electrically allowing the semiconductor wafers to be connected to the outside of the conductor chip to be connected to the electrical connection region, and to provide a method for manufacturing a high heat dissipation and high power. The heat-dissipating conductor wafers connected to the wafer carrier-connected regions back-to-back are electrically connected to the ground loop to electrically connect the package itself. a wiring layer; at least one of the first wafers through the chip contact region; and for the purpose of the invention, the high heat dissipation package of the present invention comprises: a wafer carrier for providing the half, wherein the wafer a wafer connector component for electrically and electrically connecting the electronic component and the external device electrically connected to the plurality of solder ball pads (s ο 1 derba 1 1 and a cloth with a plurality of conductive trace crystal forms attached to the wafer a carrier is placed on the first wafer and passed through a conductive adhesive having a good conductive effect, such as silver glue, etc., and a heat sink connected to the area of the wafer carrier; a first wafer is formed on the first wafer a conductive layer having a good thermal conduction and a conductive effect between the heat dissipating member; at least one non-active surface is attached to an adhesive layer having a good thermal conductive effect, and the adhesive layer is connected to the heat dissipating member through the adhesive layer, and Wire bonding form and the crystal

iiii®Iiii®

17364石夕品.ptd 第11頁 1297538 ,,五、發明說明（4) 片承載件及散熱件電性連接之第二晶片；複數條用以電性 連接該第二晶片至該晶片承載件之銲線；以及一形成於該 晶片承載件上並包覆住該複數個晶片與銲線的封裝膠體。 前述之具高散熱高電性之堆疊式半導體晶片封裝件其 製法包括：透過覆晶形式接置並電性連接該第一晶片於該 晶片承載件之晶片接置區上。其次，於該第一晶片上形成 該具有良好導熱與導電效果之傳導層。再者，接置並電性 連接一導電及導熱效果良好之散熱件於該傳導層及該接地 區上，藉以透過該散熱件逸散該第一晶片運作時所產生的 熱f，且提供該第一晶片透過該散熱件與該接地區電性連 接。接著，透過一介於該第二晶片非作用表面與該散熱件 之黏著層接置該第二晶片於該散熱件上，該第二晶片復藉 由複數之銲線分別與該散熱件及該晶片承載件電性連接。 最後，形成一封裝膠體，俾包覆該第一晶月、第二晶片、 散熱件、複數之銲線及部分之晶片承載件。 相較於習知的具高散熱高電性之堆疊式半導體晶片封 裝件及其製法，本發明之具高散熱高電性之堆疊式半導體 晶片封裝件及.其製法，除得透過在以背對背接置之半導體 晶片間接置一散熱件之方式，藉以讓該等半導體晶片於運 % >所生的熱能得有效的加以逸散外。另一方面，復得提 供讓該等半導體晶片透過由該散熱件所形成的接地迴路電 性傳導至該封裝件外，俾提高該封裝件本身電性品質。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方17364石夕品.ptd Page 11 1297538,, 5, invention description (4) a second wafer electrically connected to the sheet carrier and the heat sink; a plurality of strips for electrically connecting the second wafer to the wafer carrier a bonding wire; and an encapsulant formed on the wafer carrier and covering the plurality of wafers and bonding wires. The above-mentioned stacked semiconductor chip package having high heat dissipation and high electric power comprises the steps of: connecting and electrically connecting the first wafer to the wafer receiving area of the wafer carrier through a flip chip. Next, the conductive layer having good thermal and electrical conductivity is formed on the first wafer. Furthermore, a heat-dissipating component having a good electrical conduction and heat-conducting effect is electrically connected to the conductive layer and the connection region, so that the heat generated by the operation of the first wafer is dissipated through the heat dissipation member, and the heat is provided. The first wafer is electrically connected to the connection region through the heat sink. Then, the second wafer is connected to the heat dissipating member via an adhesive layer between the inactive surface of the second wafer and the heat dissipating member, and the second wafer is separated from the heat dissipating member and the wafer by a plurality of bonding wires. The carrier is electrically connected. Finally, an encapsulant is formed to coat the first crystal, the second wafer, the heat sink, the plurality of bonding wires and a portion of the wafer carrier. Compared with the conventional stacked semiconductor chip package with high heat dissipation and high electric property and the preparation method thereof, the stacked semiconductor chip package with high heat dissipation and high electric power of the invention is prepared by back-to-back The semiconductor wafers are indirectly placed in a heat dissipating manner, so that the heat generated by the semiconductor wafers can be effectively dissipated. On the other hand, the recovery provides electrical conduction of the semiconductor wafer through the ground loop formed by the heat sink to the outside of the package to improve the electrical quality of the package itself. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments.

17364石夕品.ptd 第12頁 1297538 五、發明說明（5) 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 (第一實施例） 請參閱第2圖，其中顯示於本實施例中本發明之具高 散熱高電性之堆疊式半導體晶片封裝件2之剖面示意圖， 需特別說明者，係該圖式與本說明書中之其他圖式同為一 簡化示意圖，僅以示意方式顯示與本發明之具高散熱高電 性之堆疊式半導體晶片封裝件及其製法有關之構件，實際 之半導體封裝件其結構佈局與製程應更加複雜。 於本實施例中，本發明之具高散熱高電性之堆疊式半 導體晶片封裝件2主要係包括有一晶片承載件2卜至少一 第一晶片2 2、一散熱件2 3、——傳導層2 4、至少一第二晶片 2 5、複數條銲線2 6以及一封裝膠體2 7。 請參閱第2 aSI ，該晶片承載件2 1，係用以提供該半導 體封裝件2與外部構件電性連接之用，於本實施例中，該 晶片承載件21係為一球柵陣列式（BGA)基板，該晶片承 載件2 1具有一用以與該第一晶片2 2電性連接之第一表面 2 1 a，以及一相對於該第一表面2 1 a用以植接複數個呈柵狀 陣列排列的銲球（Solder bal 1) 21 1之第二表面21b，俾 得透過該銲球2 1 1將整個封裝單元銲結及電性連接至如印 刷電路板之外部裝置上。17364 石夕品.ptd Page 12 1297538 V. INSTRUCTIONS (5) A person skilled in the art can readily appreciate other advantages and effects of the present invention from the disclosure of this specification. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. (First Embodiment) Referring to FIG. 2, there is shown a cross-sectional view of a stacked semiconductor chip package 2 of the present invention having high heat dissipation and high electrical conductivity in the present embodiment, which is specifically described. The other drawings in this specification are also a simplified schematic diagram, and only show the components related to the stacked semiconductor chip package with high heat dissipation and high electric power of the present invention and the manufacturing method thereof, and the actual layout of the semiconductor package. And the process should be more complicated. In this embodiment, the stacked semiconductor chip package 2 of the present invention having high heat dissipation and high electrical conductivity mainly comprises a wafer carrier 2, at least one first wafer 2, a heat sink 23, and a conductive layer. 2, at least a second wafer 2 5, a plurality of bonding wires 26 and an encapsulant 27. Referring to the second aSI, the wafer carrier 21 is used to provide electrical connection between the semiconductor package 2 and the external component. In the embodiment, the wafer carrier 21 is a ball grid array ( a BGA) substrate, the wafer carrier 21 has a first surface 2 1 a for electrically connecting to the first wafer 22, and a plurality of substrates for implanting the plurality of surfaces 1 1 a with respect to the first surface 2 1 a The second surface 21b of the solder ball (Solder bal 1) 21 1 of the grid array is soldered and electrically connected to the external device such as the printed circuit board through the solder ball 21 1 .

II

17364矽品.ptd 第13頁 五、發明說明^ — ~〜—一—- 晶片承巷二Γι ϋ承載件2 1復具有一晶片接置區2 1 4以供該 日日/1艰載件2 1接置該第一晶夕田· _曰h 2 Μ β # 用，至少一用以與該第 日日Λ “與该第二晶片2 5及該外立R验2Ε a A、α玖$ 1 A Γ·。 裝置電性連接俾形成接 地迴接地區215;此外，該晶片承载件21復佈設有複 數ϋν的佈線層（未圖示）’同時於該導電跡線之 兩=。卩=別形成有該銲塾212與複數個輝線墊213，且使談 銲墊2 1 2形成於該晶片接置區2 i 4之内。 該第一晶片22具有一作用表面221與一非作用表面 2 2 2,並以覆晶方式接置並電性連接於該晶片承載件2ι 上〇其中，於該作用表面221上形成有複數個銲球22U， 並將該銲球22 la銲結至形成於該晶片接置區214内之 212上，俾供該第一晶片22電性連接於該晶片承載件^之 上。此外，該第一晶片22與該晶片承載件21間復形成有一 底部填膠28( underfin)，俾強化該些銲球221丑之 強度。 依 该散熱件2 3，其係跨置於該第一晶片2 2上並透過一旦 有良好導電效果之導電膠2 3 1，如銀膠等，與該晶片承載、 件21之接地區.2 15電性連接。於本實施例中了該=熱^ 23 之主要材質得為銅，且其背對該晶片承載件2丨之表面2 3 上1形成有一錄金或鍍銀層2 3 2，以利於該表面23a上進= 銲線接合作業。 丁 該傳導層2 4，其係形成於該第一晶片2 2之非作用表面 2 2 2與該散熱件23之間，具有良好導熱導電效果之特性' 得用以提供該第一晶片2 2於運作產生熱能時，得將該熱能17364矽品.ptd Page 13 V. Invention Description ^ — ~~—一—- The wafer carrier 2Γ ϋ carrier 2 1 has a wafer connection area 2 1 4 for the day/1 difficulty 2 1 is connected to the first crystal 夕田· _曰h 2 Μ β #, at least one for use with the first day Λ "with the second wafer 25 and the external R test 2 Ε a A, α 玖 $ 1 A Γ · The device is electrically connected to form a ground return region 215; in addition, the wafer carrier 21 is overlaid with a plurality of ϋ ν wiring layers (not shown) 'at the same time as the two conductive traces = 卩 = The solder pad 212 and the plurality of glow pad 213 are formed, and the conductive pad 2 1 2 is formed in the wafer receiving area 2 i 4 . The first wafer 22 has an active surface 221 and a non-active surface. 2 2 2, and is flip-chip connected and electrically connected to the wafer carrier 2 ι, wherein a plurality of solder balls 22U are formed on the active surface 221, and the solder balls 22 la are soldered to form The first wafer 22 is electrically connected to the wafer carrier ^ at the 212 in the wafer receiving region 214. Further, the first wafer 22 and the wafer carrier 21 are double-shaped. Forming an underfill 28 to strengthen the strength of the solder balls 221. According to the heat dissipating member 23, it is placed on the first wafer 22 and penetrates the conductive adhesive once it has a good conductive effect. 2 3 1, such as silver glue, etc., is connected to the wafer carrier, the connection area of the device 21. 2 15 . In this embodiment, the main material of the heat = 23 is copper, and the back of the wafer The surface 2 3 of the carrier member 2 is formed with a gold or silver plating layer 23 2 to facilitate the bonding operation of the surface 23a. The conductive layer 24 is formed on the first wafer. The non-acting surface of the 2 2 and the heat dissipating member 23 have a good thermal conductivity effect. The thermal energy can be provided when the first wafer 22 is operated to generate thermal energy.

該第 1297538 五、發明說明（7) 藉由該傳導層2 4傳遞至該散熱件2 3，再透過該散熱件2 3將 該熱能有效逸散至封裝件外，俾提昇該封裝件2中晶片之 穩定性與使用壽命。另一方面，該第一晶片22復透S過背面 接地之方式，藉由該傳導層2 4將接地訊號傳導至該散熱件 2 3，再藉由該散熱件2 3將接地訊號傳導至該接地區2 1 5。 於本實施例中，該傳導層2 4得為一散熱與導電效果良好之 散熱導電 T ( thermal grease)。 .晶片 2 5具有一介《衣to ζ ΰ i興一非作用表面 2 5 2，並以銲線接合方式與該晶片承載件21電性連接。 該作用表面2Λ1卜游# 士…批加△日a μ ^ ^ 施例中=上曰形成丄數個二線墊2 53。此外，於本， 形成有-具面25 2與該散熱件23間 片25於該散Li2熱效果之黏著層29,俾接置該第二^ 言亥複數條銲绩、 墊2 5 3至該晶片承’ \、糸甩以連接該第二晶片25之銲差 層2 3 2,藉以 牛21之銲線墊21 3以及該散熱件2 件23電性連接該晶片承載件21及該散熱 號於外部裝置上。2::原及/或其他工作訊號與接地訊 /亥封袭膠體27丄;=” ’該鮮線26得為-金線< 包復住该第—晶片2^、、噌埶j於3亥晶片承載件21上並用 線26及部分之晶片二7牛三3、第二晶片25、複數之杳 污染物所侵害。於太Ϊ t 精以避免其受外界之水氣d (molding)、本貫鈿例中，該封裝膠麟9 m、# ” ^ D .、 g)作業藉以將槲胙仏入仏 膠體27係透過模層The 1297538 fifth invention description (7) is transmitted to the heat dissipating member 23 by the conductive layer 24, and the thermal energy is effectively dissipated to the outside of the package through the heat dissipating member 23, and the package member 2 is lifted. The stability and lifetime of the wafer. On the other hand, the first wafer 22 is re-passed through the back surface of the ground, and the grounding signal is transmitted to the heat sink 23 through the conductive layer 24, and the ground signal is transmitted to the heat sink 23. Connect to the area 2 1 5 . In this embodiment, the conductive layer 24 is a thermal grease that has good heat dissipation and electrical conductivity. The wafer 25 has a non-active surface 252 and is electrically connected to the wafer carrier 21 by wire bonding. The surface of the action 2Λ1卜游#士...additional △day a μ ^ ^ In the example, the upper 曰 forms a number of two-line pads 2 53 . In addition, in the present invention, an adhesive layer 29 is formed between the surface of the surface 25 2 and the heat dissipating member 23 in the heat effect of the Li2, and the second plurality of soldering marks and pads 2 5 3 are attached to the second layer. The wafer is connected to the soldering layer 2 3 2 of the second wafer 25, and the soldering pad 21 3 of the bovine 21 and the heat dissipating member 23 are electrically connected to the wafer carrier 21 and the heat dissipation. No. on the external device. 2:: original and / or other work signals and grounding / Hai seal colloid 27 丄; = " 'The fresh line 26 is - gold line < cover the first - wafer 2 ^, 噌埶 j The 3 watt wafer carrier 21 is invaded by the wire 26 and a part of the wafer 2 7 ox 3, the second wafer 25, and a plurality of sputum contaminants. The enthalpy is used to avoid the external moisture d (molding) In the example of the present example, the package rubber lining 9 m, # ” ^ D ., g) is used to insert the yttrium colloid 27 through the mold layer.

Resin)等封裝材料开環氧樹脂（ 冑w成於該晶片承載件21之上。The encapsulating material such as Resin) is opened on the wafer carrier 21 by an epoxy resin.

:P〇2:P〇2

第15頁Page 15

•1297538•1297538

，五、發明說明（8) 請併同參照第2圖及第3a至3 e圖，前述之具高散熱高 電性之堆豐式半導體晶片封裝件2其製法包括以下步驟: 請參閱第3 a圖，首先，置備該晶片承載件2 1，並於号Γ 晶片承載件2 1之第一表面2 1 a接置該第一晶片2 2。承前所/ 述，於本實施例中，該第一晶片2 2係透過覆晶方式接置並 電性連接於該晶片承載件2 1上。其中，該第一晶片2 2之作 用表面2 2 1上形成有複數個銲球2 2 1 a，透過將該銲球22 1 a 録結至形成於5亥晶片接置區2 1 4内之鲜塾2 1 2上，以使今第 一晶片2 2接置並電性連接於該晶片承載件2 1上。此外，復 形，該底部填膠2 8於該第一表面2 1 a與該晶片承载件2 i 4 間，俾強化該些銲球2 2 1 a之銲接強度。 其次，如第3 b圖所示，於該第一晶片2 2之非作用表面 2 2 2上形成該傳導層24。 、 再者’如第3 c圖所示，接置該散熱件2 3於該傳導声2 $ 及該接地區2 1 5上，於本實施例中，該散熱件2 3係透過該 導電膠2 3 1接置並電性連接該散熱件2 3於該接地區2 1 5上， 藉以透過該散熱件23逸散該第一晶片22運作時所產生的執 能至該封裝件· 2，同時提供該第一晶片2 2接地之功能。承“、 前所述’該散熱件23之表面23a上已預先形成有一錄金或 慰，層2 3 2，以利於该表面2 3 a上進行銲線接合作業。' $ 接著，如第3 d圖所示，於該第二晶片2 5之非作用 2 5 2與該散熱件23間形成該黏著層29,俾接琶 "面 25於該散熱件23上，該第二晶片復藉由//之°=線—^片 與該散熱件2 3及該晶片承載件2 1電性連接。5. Inventive Note (8) Please refer to FIG. 2 and Figures 3a to 3e together. The above-mentioned method for manufacturing a high-heating and high-power stacking semiconductor chip package 2 includes the following steps: A, first, the wafer carrier 2 1 is placed and the first wafer 2 2 is attached to the first surface 2 1 a of the wafer carrier 2 1 . As described above, in the present embodiment, the first wafer 2 is electrically connected to the wafer carrier 21 by a flip chip. A plurality of solder balls 2 2 1 a are formed on the active surface 2 2 1 of the first wafer 22, and the solder balls 22 1 a are recorded and formed in the 5 watt wafer receiving area 2 1 4 . The fresh wafer 2 is placed on the wafer carrier 21 for electrical connection. In addition, the underfill is between the first surface 2 1 a and the wafer carrier 2 i 4 , and the bonding strength of the solder balls 2 2 1 a is strengthened. Next, as shown in Fig. 3b, the conductive layer 24 is formed on the non-active surface 22 of the first wafer 22. Further, as shown in FIG. 3c, the heat sink 2 is connected to the conductive sound 2$ and the connection region 2 15 . In the embodiment, the heat sink 2 3 is transmitted through the conductive adhesive. 2 3 1 is connected and electrically connected to the heat sink 2 3 in the connection area 2 1 5 , thereby dissipating the function generated by the operation of the first wafer 22 through the heat sink 23 to the package 2 At the same time, the function of grounding the first wafer 22 is provided. The front surface of the heat dissipating member 23 has a gold or a consolation layer formed thereon, and a layer 2 3 2 is formed on the surface 23a of the heat dissipating member 23 to facilitate the bonding work on the surface 23a. '$ Next, as in the third As shown in the figure d, the adhesive layer 29 is formed between the non-active 2 2 2 of the second wafer 25 and the heat sink 23, and the surface 25 is on the heat sink 23, and the second wafer is borrowed. The heat sink member 23 and the wafer carrier 21 are electrically connected to each other.

17364矽品.Ptd 第16頁 1297538 五、發明說明（9) 最後，如第3e圖所示，形成該封裝膠體27於該晶片承 載件2 1之第一表面2 1 a上，俾包覆該第一晶片2 2、散熱件 2 3、第二晶片2 5、複數之銲線2 6及部分之晶片承載件2 1。 (第二實施例） 請參閱第4圖，其中顯示本發明之具高散熱高電性之 堆疊式半導體晶片封裝件2 ’第二實施例之剖面示意圖。如 圖所示，本發明之第二實施例之具高散熱高電性之堆疊式 半導體晶片封裝件2 ’與第一實施例所揭示者大抵相同。其 不同之處在於該散熱件2 3 ’僅透過該傳導層2 4 ’接置於該第 一晶片2 2 ’之非作用表面2 2 2 ’上，而並未如第一實施例 般，透過該導電膠2 3 a接置並電性連接該散熱件2 3於該晶 片承載件2 1之接地區2 1 5上。而係於該銲線2 6 ’電性連接該 第二晶片2 5 ’與該散熱件2 3 ’後，再透過該銲線2 6 ’電性連 接晶片承載件2 1 ’及該散熱件2 3 ’，俾使該第二晶片2 5 ’之 接地訊號得傳遞至該晶片承載件2 1 ’之接地區2 1 5上。 上述實施例僅為例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此項技藝之人士均可在不 違背本發明之精神及範疇下，對上述實施例進行修飾與變 化。因此，本發明之權利保護範圍，應如後述之申請專利 範圍所列。17364矽品.Ptd Page 16 1297538 V. INSTRUCTION DESCRIPTION (9) Finally, as shown in Fig. 3e, the encapsulant 27 is formed on the first surface 2 1 a of the wafer carrier 2 1 The first wafer 2, the heat sink 2 3, the second wafer 25, the plurality of bonding wires 26 and a portion of the wafer carrier 21. (Second Embodiment) Referring to Fig. 4, there is shown a cross-sectional view showing a second embodiment of a stacked semiconductor chip package 2' having high heat dissipation and high electric power according to the present invention. As shown in the figure, the stacked semiconductor chip package 2' having high heat dissipation and high electric power according to the second embodiment of the present invention is substantially the same as that disclosed in the first embodiment. The difference is that the heat sink 2 3 ′ is only disposed on the non-active surface 2 2 2 ′ of the first wafer 2 2 ′ through the conductive layer 24 ′′, and is not transmitted through the first embodiment. The conductive adhesive 2 3 a is connected and electrically connected to the heat sink 2 3 on the area 2 1 5 where the wafer carrier 2 1 is connected. After the bonding wire 26 6 ' is electrically connected to the second wafer 2 5 ′ and the heat sink 2 3 ′, the wafer carrier 2 1 ′ and the heat sink 2 are electrically connected through the bonding wire 26 6 ′. 3 ', the ground signal of the second wafer 2 5 ' is transmitted to the area 2 1 5 of the wafer carrier 2 1 '. The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later.

17364s夕品.ptd 第17頁 1297538 摄I式簡單說明 【圖式簡單說明】 第1圖為習知堆疊式半導體封裝件之局部剖視圖； 第2圖為本發明具高散熱高電性之堆疊式半導體晶片 封裝件之第一實施例之剖面示意’圖； 第2 a圖為本發明具高散熱高電性之堆疊式半導體晶片 封裝件之第一實施例之正面示意圖； 弟3a至圖為本發明具南散熱局電性之堆豐式半導體 晶片封裝件之第一實施例之製法示意圖；以及 第4圖為本發明具高散熱高電性之堆疊式半導體晶片 封1件之第二實施例之剖面示意圖。 1 半 導 體 封 裝件 10 基 板 10a 銲 墊 10b 導 電 跡 線 11 第 一 晶 片 12 第 二 晶 片 12a 銲 墊 13 黏 著 層 14 銲 線 15 銲 球 16 封 裝 膠 體 2、2, 半 導 體 封 裝 件 21 晶 片 承 載 件 21a 第 一 表 面 21b 第 二 表 面 211 銲 球 2 Ο 銲 墊 213 銲 線 塾 214 晶 片 接 置 區 215 接 地 區 22〜 22, 第 一 晶 片 221 作 用 表 面 221a 銲 球 2 2 2、 11V 非 作 用 表 面 23 > 23, 散 敎 件 23a 表 面17364s 夕品.ptd Page 17 1297538 Photo I Simple Description [Simplified Drawing] Fig. 1 is a partial cross-sectional view of a conventional stacked semiconductor package; Fig. 2 is a stacked type with high heat dissipation and high electric power according to the present invention FIG. 2 is a front view showing a first embodiment of a stacked semiconductor chip package having high heat dissipation and high electric power according to a first embodiment of the invention; FIG. 2a to FIG. A schematic diagram of a method for fabricating a first embodiment of a stack of semiconductor chip packages having a south heat dissipation system; and a fourth embodiment of the present invention for a stacked semiconductor wafer package having high heat dissipation and high electrical properties Schematic diagram of the section. 1 semiconductor package 10 substrate 10a pad 10b conductive trace 11 first wafer 12 second wafer 12a pad 13 adhesive layer 14 bonding wire 15 solder ball 16 encapsulant 2, 2, semiconductor package 21 wafer carrier 21a first Surface 21b second surface 211 solder ball 2 焊 pad 213 wire bond 214 wafer contact region 215 connection region 22 to 22, first wafer 221 active surface 221a solder ball 2 2 2, 11V non-active surface 23 > 23, Heat sink 23a surface

17364石夕品.ptd 第18頁 129753817364石夕品.ptd Page 18 1297538

17364石夕品.ptd 第19頁17364 Shi Xipin.ptd Page 19

Claims (1)

5?7538 f 年._cf 月 3 曰_____ 1 · 〜種具言丑 包括7巧散熱高電性之堆疊式半導體晶 外 其係用以提供該半導體封裝件與 連挺ί I ~第一晶片，其係藉由覆晶形式接置並電性 得於該晶片承載件上·， 一散熱件，其係跨置於該第一晶片上，並盥該晶 片承載件電性連接； η5?7538 f Year._cf Month 3 曰_____ 1 · ~ A smug type of semiconductor semiconductor including 7-piece heat dissipation and high-powered is used to provide the semiconductor package and the connection of the first chip And being attached to the wafer carrier by a flip chip, and a heat sink is disposed on the first wafer and electrically connected to the wafer carrier; ^ 至少一第二晶片，其具有一透過銲線電性連接該 放熱件與該晶片承載件之作用表面以及一提供該第二 晶片接置於該散熱件上之非作用表面；以及A / 一封裝膠體，其係形成於該晶片承載件上並包覆 住該第一晶片、第二晶片、散熱件及其他構件，並部 分包覆住該晶片承載件。 2.如申請專利範圍第1項之具高散熱高電性之堆疊式半導 體晶片封裝件，其中’該晶片承載件可為一基板及導 線架其中之一者。 3 ·如申請專利範圍第1項之具高散熱高電性之堆疊式半導At least one second wafer having a transmission wire electrically connecting the heat releasing member and an active surface of the wafer carrier and an inactive surface for providing the second wafer to the heat sink; and A / a An encapsulant is formed on the wafer carrier and covers the first wafer, the second wafer, the heat sink and other components, and partially covers the wafer carrier. 2. The stacked semiconductor package of claim 1, wherein the wafer carrier is one of a substrate and a wire frame. 3 · Stacked semi-conductors with high heat dissipation and high electric power as in the first patent application scope 體晶片封裝件，其中，該晶片承載件形成有至"少一用 以接置並電性連接該第一晶片之晶片接置區。 4 ·如申請專利範圍第1項之具同散熱高電性之堆疊式半導 體晶片封裝件，其中，該晶片承載件復形成有少一 接地區，用以與該散熱件電丨生連接’俾將該散熱件所 接收到至接地訊號傳遞至外部裂置。The body chip package, wherein the wafer carrier is formed with a wafer attachment region for connecting and electrically connecting the first wafer. 4) The stacked semiconductor chip package having the same heat dissipation and high electrical conductivity as in the first application of the patent scope, wherein the wafer carrier is formed with a small connection area for electrically connecting with the heat sink. The ground signal received by the heat sink is transmitted to the external crack. 17364(修正版）.ptc 1297538 _案號92119210 €年沙月3日 修正_ 六、申請專利範圍 5. 如申請專利範圍第1項之具高散熱高電性之堆疊式半導 體晶片封裝件，其中，該晶片承載件復形成有複數個 用以連接銲球之鮮墊（solder ball pad)，以及用以 連接銲線之銲線墊（finger)。 6. 如申請專利範圍第1項之具高散熱高電性之堆疊式半導 體晶片封裝件，其中，該晶片承載件復包括有至少一 用以依據該第一晶片與該第二晶片之銲結圖式進行線 路圖案化以佈設有複數之導電跡線的佈線層。 7. 如申請專利範圍第1項之具高散熱高電性之堆疊式半導 體晶片封裝件，其中，該散熱件係透過一導電膠與該 接地區電性連接。 8. 如申請專利範圍第1項之具高散熱高電性之堆疊式半導 體晶片封裝件，復包括一傳導層，其係形成於該第一 晶片與該散熱件之間且具有良好導熱與導電效果，俾 供該第一晶片透過該散熱件逸散熱能並傳導接地訊號 至該晶片承載件之接地區。 9. 如申請專利範圍第8項之具高散熱高電性之堆疊式半導 體晶片封裝件，其中，該傳導層可為一導電散熱膏。 1 0 .如申請專利範圍第1項之具高散熱高電性之堆疊式半導 體晶片封裝件，復具有一黏著層，其係用以接置該第 二晶片於該散熱件上且具有良好導熱效果。 11. 一種具高散熱高電性之堆疊式半導體晶片封裝件，係 包括： 一晶片承載件，其係用以提供該半導體封裝件與17364 (Revised Edition).ptc 1297538 _ Case No. 92192210 €年沙月3日修正_ Six, the scope of application for patents 5. As claimed in the scope of claim 1, the high-heat-dissipation stacked semiconductor chip package, The wafer carrier is formed with a plurality of solder ball pads for connecting solder balls, and a wire bond for connecting the bonding wires. 6. The stacked semiconductor chip package of claim 1, wherein the wafer carrier further comprises at least one soldering layer according to the first wafer and the second wafer. The pattern is patterned to provide a wiring layer of a plurality of conductive traces. 7. The stacked semiconductor package of claim 1, wherein the heat sink is electrically connected to the connection region via a conductive paste. 8. The stacked semiconductor chip package having high heat dissipation and high electrical power according to claim 1 of the patent application, further comprising a conductive layer formed between the first wafer and the heat sink and having good heat conduction and conductivity The effect is that the first wafer is dissipated through the heat dissipating component and conducts a ground signal to the region of the wafer carrier. 9. The stacked semiconductor package of claim 4, wherein the conductive layer is a conductive thermal paste. 10. A stacked semiconductor chip package having high heat dissipation and high electrical power according to claim 1 of the patent application, having an adhesive layer for attaching the second wafer to the heat sink and having good heat conduction effect. 11. A stacked semiconductor chip package having high heat dissipation and high electrical power, comprising: a wafer carrier for providing the semiconductor package and 17364(修正版）.ptc 第21頁 1297538 一案號92119210 年彳月^日 修正 申請專利範圍 外部構件電性連接； 至少一第一晶片，其係藉由覆晶形式接置並電性 連接於該晶片承載件上； 該 一散熱件，其係接置於該第一晶片上且未接觸至 曰曰 片承載件，並透過銲線接合之方式與該晶片承載 件電性連接； 至少一第二晶片，其具有一透過銲線電性連接該 散熱件與該晶片承載件之作用表面以及一提供該第二 晶片接置於該散熱件上之非作用表面；以及 >二封裳膠體，其係形成於該晶片承載件上並包覆 ί ΐ:::!片、第二晶片、散熱件及其他構件，並部 刀包復住該晶片承載件。 1 2 ·如申請專利簕 ^ 導體晶片封穿ΐ 項之具南政熱高電性之堆疊式半 導線架其中者其中，該晶片承载件可為一基板及 1 3 ·如申請專利範# 導體晶片封裴件弟11項之具高散熱高電性之堆疊式半 用以接置並^地，其中，該晶片承载件形成有至少一 14.如申請專利範‘，接該第一晶片之晶片接置區。 導體晶片封巢=弟^項之具高散熱高電性之堆疊式半 一接地區，用以盥ς中，該晶片承栽件復形成有至少 所接收到至每^ ^熱件電性連接，俾將該散埶件 1 5.如申請專利範 f就傳遞至外部裝置。 …、 導體晶片第d:熱高電性之堆疊式半 ’一 #件復形成有複數17364 (Revised).ptc Page 21 1297538 A Case No. 92192210 彳月^日 Revised the patented range of external components electrical connection; at least a first wafer, which is connected by a flip chip and electrically connected On the wafer carrier; the heat sink is attached to the first wafer and is not in contact with the die carrier, and is electrically connected to the wafer carrier by wire bonding; at least one a second wafer having a transmission wire electrically connecting the heat dissipating member and an active surface of the wafer carrier and an inactive surface for providing the second wafer to the heat dissipating member; and a second sealing body, It is formed on the wafer carrier and covers the ΐ:::! sheet, the second wafer, the heat sink and other components, and the slats cover the wafer carrier. 1 2 · If applying for a patent 簕^ Conductor wafer encapsulation, a stacked semi-conductor with a high thermal power of Nanzheng, wherein the wafer carrier can be a substrate and 1 3 · as claimed in the patent # conductor The chip-mounting half of the chip-sealing device has a high heat-dissipating and high-powered stacked-type half for connecting and grounding, wherein the wafer carrier is formed with at least one 14. As claimed in the patent, the first chip is connected Wafer placement area. Conductor wafer encapsulation = the high-heat-dissipation and high-power stacking half-connected area of the device, which is used for the middle of the wafer, and the wafer carrier is formed to have at least the electrical connection received to each of the hot components. , the transfer unit 1 5. is transferred to the external device as in the patent application. ..., conductor wafer d: stacking half of heat and high electricity 17364(修正版）.pt( 第22頁 1297538 92119210 修正 六、申請專利範圍 _ 個用以連接銲球之銲墊， 墊。 及用以連接銲線之銲線 16.如申請專利範圍第21項之呈 導體晶片封裝件，其中，該曰二;阿電性之堆疊式半 -用以依據該第一晶片與心；二7曰載件復包括有至少 線路圖案化以佈設有複數之之銲結圖式進行 1 7.如申請專利範圍第1 1項之具古今、t的佈線層。 導體晶片封裝件，復包括—傳導W電性之堆疊式半 一晶片與該散熱件之間且罝古:，其係形成於該第 :U弟曰曰片透過该散熱 :“呆 號至該晶片承載件之接地區。遇政熱肊並傳導接地訊 1 8.如申請專利範圍第i 7項之且 導體晶片封裝件，盆中，1月:而電性之堆疊式半 膏。 /、中遠傳導層可為-導電散熱 19. 如申請專利範圍第n項之且 導體晶片封裝件，德1 + ^ 月，、、、呵電性之堆疊式半 _ 1卞设具有一黏著層，甘及m 弟二晶片於1亥散熱件上且具有良好墓;;t 接置該 20. —種具高散熱高電性之 v熱效果。 法，係包括： $ ^^體晶片封裝件製 -曰ί f::形式接置並電性連接至少-第”於 一晶片水載件之θμ & ^ 第一晶片於 於該第4;,接置區上； 之傳導層； $成一具有良好導熱與導電效果 連接-導U導熱效果良好之散熱件17364 (Revised).pt (page 22 1297538 92119210 Amendment 6. Patent scope _ solder pads for soldering balls, pads and soldering wires for connecting bonding wires. The conductor chip package, wherein the second stack is used to be based on the first wafer and the core; the second 7 曰 carrier includes at least a line pattern to be provided with a plurality of solders The junction pattern is performed. 1. 7. The wiring layer of the ancient and modern, t, as claimed in claim 11. The conductor chip package further includes a stacked semi-wafer that conducts electricity and is interposed between the heat sink and the heat sink. Ancient: The system is formed in the first section: the U-chip is transmitted through the heat: “Send the number to the area where the wafer carrier is connected. In case of political enthusiasm and conduction of grounding communication, 1. If the patent application scope is item i 7 And the conductor chip package, in the pot, January: and the electrically stacked half-paste. /, the COSCO conductive layer can be - conductive heat sink 19. As claimed in the scope of the nth and the conductor chip package, de 1 + ^ Month,,,, and electricity stacking half _ 1卞 has an adhesive layer Gan and m di two chips on a 1 hai heat sink and have a good tomb; t is connected to the 20. a high thermal and high thermal v thermal effect. The method includes: $ ^ ^ body chip package system -曰ί f:: formally connected and electrically connected to at least -" θμ & ^ on a wafer water carrier ^ first wafer on the fourth;, the junction region; the conductive layer; Good thermal conductivity and conductive connection - heat sink with good thermal conductivity 17364(修正版）.ptc 第23頁 接置並電性遠 1297538 六、申請專利範圍 修也 於4傳導層及該接地區上 替人赛 一晶片運作時错以透過該散熱件逸竑1^ 地區；，所產生的熱能，並傳導接地訊號裏該接 ^^ — 具有良好導執二：f晶片非作用表面與該散熱件且 件上，其著層接置該第二晶片於該散熱 式分別盥嗲1^曰曰片之作用表面係藉由銲線之方 形成-封裝膠體，俾包覆兮裳电ra ,一 s 件。牛及其他構件，並部分包覆住該晶另承載 2ΐ.η:ϊ圍第20項之具高散熱高電性之堆疊式半 ¥體日日片封裝件製法，其中， 板及導線架其中之—者。月承載件了為基 22t: ?專利範圍第2〇項之具高散熱高電性之堆疊式半 ;重體:曰片封裳件製法，其中，該晶片承載件復形 ΐ Ϊ 以連接輝球之㈣，以及用以連接鮮線之銲 23.如申請專利範圍第2〇項之具高散熱高電性之堆疊 導體晶片封裝件製法，其中，該晶片承載件1 至卜用以依據該第一晶片與該第二晶；：以： 進行線路圖案化以佈設有複數之導電跡線的佈線層= 2 4 ·如申請專利範圍第2 〇項之具咼散熱高電性之堆最气“ 導體晶片封裝件製法，其中’該散熱件係跨置於令= 一晶片上並透過一導電膠與該接地區電性連接 弟17364 (Revised Edition).ptc Page 23 is connected and electrically far away from 1297538. VI. The scope of the patent application is also modified in the 4th conductive layer and in the area where the chip is operated, and the fault is transmitted through the heat sink. The generated thermal energy, and the conductive grounding signal, has a good guide: the f-inactive surface of the f-chip and the heat-dissipating member are connected to the second wafer in the heat-dissipating manner. The surface of the 盥嗲1^ 曰曰 系 形成 形成 形成 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用 作用Cattle and other components, and partially covered with the crystal carrying 2ΐ. η: 第 第 第 第 第 第 第 第 第 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠 堆叠- the one. The carrier of the month is based on 22t: the second half of the patent scope has a high heat dissipation and high electric stacking half; the heavy body: the cymbal sealing device, wherein the wafer carrier is shaped to 连接 连接(4), and a welding method for connecting a fresh wire. The method of manufacturing a stacked conductor chip package having high heat dissipation and high electric power according to the second aspect of the patent application, wherein the wafer carrier 1 is used according to the method a first wafer and the second crystal; the following: a wiring layer patterned by wiring to form a plurality of conductive traces = 2 4 · The most efficient stack of heat and high electric power according to the second aspect of the patent application "Conductor chip package manufacturing method, in which the heat dissipating member is placed on a wafer and electrically connected to the connection region through a conductive adhesive 17364(修正版）.ptc 1297538 _案號 92119210 六、申請專利範圍 年/月3曰 修正 2 5 .如申請專利範圍第2 0項之具高散熱高電性之堆疊式半 導體晶片封裝件製法，其中，該散熱件係接置於該第 一晶片上並透過銲線接合之方式與該接地區電性連 接。 2 6 .如申請專利範圍第2 0項之具高散熱高電性之堆疊式半 導體晶片封裝件製法，其中，該傳導層可為一導電散 熱膏。17364 (Revised Edition).ptc 1297538 _ Case No. 92119210 VI. Patent Application Scope/Month 3 曰 Amendment 2 5 . For the method of manufacturing a stacked semiconductor chip package with high heat dissipation and high electrical power according to the patent application No. 20, The heat dissipating member is electrically connected to the first wafer and connected to the connecting region by wire bonding. 2 6. A method for manufacturing a stacked semiconductor chip package having high heat dissipation and high electrical power according to claim 20, wherein the conductive layer is a conductive heat-dissipating paste. 17364(修正版）.ptc 第25頁17364 (Revised Edition).ptc Page 25
TW092119210A 2003-07-15 2003-07-15 Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof TWI297538B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092119210A TWI297538B (en) 2003-07-15 2003-07-15 Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092119210A TWI297538B (en) 2003-07-15 2003-07-15 Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof

Publications (2)

Publication Number Publication Date
TW200503210A TW200503210A (en) 2005-01-16
TWI297538B true TWI297538B (en) 2008-06-01

Family

ID=45069133

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092119210A TWI297538B (en) 2003-07-15 2003-07-15 Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof

Country Status (1)

Country Link
TW (1) TWI297538B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230238349A1 (en) * 2022-01-27 2023-07-27 Airoha Technology (HK) Limited Semiconductor package with conductive adhesive that overflows for return path reduction and associated method

Also Published As

Publication number Publication date
TW200503210A (en) 2005-01-16

Similar Documents

Publication Publication Date Title
TWI255532B (en) Flip-chip ball grid array semiconductor package with heat-dissipating device and method for fabricating the same
TWI235469B (en) Thermally enhanced semiconductor package with EMI shielding
TW579581B (en) Semiconductor device with chip separated from substrate and its manufacturing method
TW502406B (en) Ultra-thin package having stacked die
TWI529878B (en) Hybrid thermal interface material for ic packages with integrated heat spreader
TW498516B (en) Manufacturing method for semiconductor package with heat sink
TWI671861B (en) Semiconductor package structure and method of making the same
JP2004031607A (en) Semiconductor device and method of manufacturing the same
TW200416787A (en) Semiconductor stacked multi-package module having inverted second package
TW565918B (en) Semiconductor package with heat sink
TWI391084B (en) Pcb structure having heat-dissipating member
TW201123402A (en) Chip-stacked package structure and method for manufacturing the same
US7659620B2 (en) Integrated circuit package employing a flexible substrate
TW201227916A (en) Multi-chip stack package structure and fabrication method thereof
TW200828527A (en) Chip package and method of manufacturing the same
WO2023241304A1 (en) Chip packaging methods and chip
TWI536515B (en) Semiconductor package device with a heat dissipation structure and the packaging method thereof
JP3547303B2 (en) Method for manufacturing semiconductor device
TW200529387A (en) Chip package structure
TW577153B (en) Cavity-down MCM package
JPH10335577A (en) Semiconductor device and its manufacture
TW201110250A (en) Package substrate structure and method of forming same
TWI297538B (en) Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof
JP3628991B2 (en) Semiconductor device and manufacturing method thereof
TW200845354A (en) Multi-chip semiconductor device having leads and method for fabricating the same

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent