TW201110250A - Package substrate structure and method of forming same - Google Patents

Package substrate structure and method of forming same Download PDF

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Publication number
TW201110250A
TW201110250A TW098129809A TW98129809A TW201110250A TW 201110250 A TW201110250 A TW 201110250A TW 098129809 A TW098129809 A TW 098129809A TW 98129809 A TW98129809 A TW 98129809A TW 201110250 A TW201110250 A TW 201110250A
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Taiwan
Prior art keywords
layer
dielectric layer
package structure
carrier
semiconductor wafer
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TW098129809A
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Chinese (zh)
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TWI417970B (en
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Lin-Yin Wong
Mao-Hua Yeh
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Unimicron Technology Corp
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Publication of TWI417970B publication Critical patent/TWI417970B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A package substrate is proposed, including a carrier having two opposing surfaces; two semiconductor chips each disposed on the two opposing surfaces of the carrier respectively, each semiconductor chip having an active surface and a non-active surface, wherein a plurality of electrode pads are formed on the active surface thereof and the non-active surface is connected with the carrier; a first dielectric layer covering both the carrier and the semiconductor chips; and a first circuit layer disposed on the first dielectric layer and comprised of a plurality of first conductive blind vias that are formed in the first dielectric layer for electrically connecting to the electrode pads. By covering the chips with the first dielectric layer, the deformation caused by heat can be prevented to avoid delamination therebetween, and the package structure having semiconductor chips embedded therein enhances electrical performance while maintaining compactness of the overall structure. The invention further provides a method for fabricating the package substrate as described above.

Description

201110250 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種半導體裝置及其製法，尤指一種能 提升電性功能之封裝結構及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦朝著輕、薄、 短、小、高積集度、多功能化方向發展。而為滿足封裝結 構高積集度（Integration)以及微型化（Miniaturization) 的封裝需求’封裝形式逐漸由單一晶片之球柵陣列（bga) 封裝或覆晶式（Flip Chip, FC)封裝演進到3D封裝和模組 化封裝形態，使得封裝結構有SiP(System in Package)、 SIP(Sys1:em Integrated Package)及 SiB(System in Board) 等多種形式。 惟’該些3D及模組化封裝形癌係以覆晶技術（f 1 i p chip)或打線技術（wire bonding)，而將複數半導體元件平 面排列接置於一個基板上，亦或以表面黏貼技術（SMT)黏貼 於基板表面。然而，該些元件係全部分佈於基板表面，因 而不利於模組化結構尺寸之縮小及性能的提高。 為此，遂有業界提出將半導體晶片埋入南密度電路才反 之結構；如第1圖所示，係先提供一具有開口 1〇〇之承載 板10 ’於該開口 100中容置有一半導體晶片11，而該半導 體晶片11具有一作用面11a及非作用面lib’於該作用面 11a上具有複數電極墊110，並於該承載板10與半導體晶 片11之作用面11a及非作用面lib上形成至少一介電層 1Π341 4 201110250 12 ’且該介電層12形成於該開口 loo與半導體晶片^ 間的間隙中’以將該半導體晶片n固定於該開口 _中之 又於該介電層丨2上形成線路層13，且該線路層a係藉由 形成於該介電層12中之複數導電盲孔13〇以電性連接^誃 二黾通墊110，又於該承載板1〇及介電層12中形成導^ 通孔101，以電性連接該承載板1〇兩側之線路層13，且於 泫取外層之線路層13具有複數電性接觸墊131。復於最外 層之介電層12及線路層13上形成防焊層14，且該防焊層 Μ中具有複數開孔140，供各該之電性接觸墊131對應外 露於各該開孔140。 “ 准，該肷埋有半導體晶片之高密度電路板結構僅有單 一半導體晶片11嵌埋於該承載板1〇中，而單一半導體晶 片11之電性功能有限，因而不敷現今多功能、高功效之電 子產品之使用需求。 此外’該介電層12與半導體晶片丨丨間之熱膨脹係數 籲（Coefficient of Thermal Expansion ; CTE)不同，於熱循 環製転中易受熱應力影響而產生翹曲變形，因而容易產生 分層的情況；或是因為半導體晶片u嵌埋於該承載板1〇 中，於該半導體晶片11作動中產生大量熱累積，因而發生 电路板爆板等問題；因此，產品良率及品質穩定性較差。 因此，如何提出一種封裝結構，以避免習知電路板結 構因熱應力導致分層的情況，且具有多功能、高功效之特 性結構’實以成為目«界祕克服之課題。 【發明内容】 5 Π134] 201110250 鑑於上述習知技術之種種缺失，本發明之一目的係提 供一種能避免習知技術中之半導體晶月與介電層分層或電 路板結構爆板問題之封裝結構及其製法。 本發明之另一目的係提供一種能提升電性功能之封 裝結構及其製法。 為達上述目的及其他目的，本發明揭露一種封裝結 構，係包括：承載片，係具有相對之兩表面；二半導體晶 片，係分別設於該承載片之相對兩表面上，各該半導體晶 片係具有相對之作用面及非作用面，且該作用面上具有複 數電極墊，而該半導體晶片係藉由該非作用面固設於該承 載片上；第一介電層，係包覆該承載片及半導體晶片；以 及第一線路層，係設於該第一介電層表面上，且該第一線 路層具有位於該第一介電層中以電性連接該電極墊之第一 導電盲孔。 前述之封裝結構，復包括黏著層，係設於該半導體晶 片之非作用面與該承載片之間，以將該半導體晶片固設於 該承載片上。 前述之封裝結構復包括複數導熱通孔，係貫穿該承載 片及第一介電層；亦包括複數導電通孔，係貫穿該第一介 電層，以電性連接該第一線路層。 前述之封裝結構復包括增層結構，係設於該第一介電 層及第一線路層上，該增層結構具有至少一第二介電層、 設於該第二介電層上並具有複數導電跡線之第二線路層、 及設於該第二介電層中並電性連接該第一與第二線路層之 6 111341 201110250 第二導電盲孔，且最外層之第二線路層具有複數電性接觸 墊，其中，該第二導電盲孔電性連接該導電通孔，以令其 中一半導體晶片藉由該第一導電盲孔、第二導電盲孔、該 第二線路層之其中一導電跡線及導電通孔電性連接至另一 半導體晶片。又包括絕緣保護層，係設於該增層結構上， 且該絕緣保護層具有複數絕緣保護層開孔，以令各該電性 接觸墊對應外露於各該絕緣保護層開孔，再包括表面處理 層，係設於該電性接觸墊上。 本發明復揭露一種封裝結構之製法，係包括：提供一 具有複數承載片之金屬板，且各該承載片之相對兩表面上 分別設置一半導體晶片，各該半導體晶片係具有相對之作 用面及非作用面，且該作用面上具有複數電極墊，而該半 導體晶片係藉由該非作用面固設於該承載片上；於該金屬 板及各該半導體晶片上形成弟一介電層，以包覆該金屬板 及各該半導體晶片，且該第一介電層上定義有對應各該半 導體晶片之有效區；於該第一介電層表面上形成第一線路 層，且於該第一介電層中形成電性連接該第一線路層及電 極墊之第一導電盲孔；以及移除該有效區以外之部分，以 形成複數封裝結構。 前述之製法中，該金屬板係由框體連結各該承载片所 構成，且該些承載片之間與承載片及框體之間係具有連接 部；該半導體晶片之非作用面與該承載片之間形成黏著 層’以將該半導體晶片固設於該承載片上，該有效區係可 對應各該承載片。 7 111341 201110250 前述之製法中，該第一介電層係以壓合方式形成於該 金屬板之相對兩表面上，且移除該有效區以外之部分係藉 由切割方式。 前述之製法，復包括形成複數貫穿該承載片及第一介 電層之導熱通孔；亦包括形成複數貫穿該第一介電層之導 電通孔，以電性連接該些第一線路層。 前述之製法復包括於移除該有效區以外之部分之 前，於該第一介電層及第一線路層上形成增層結構，該增 層結構具有至少一第二介電層、設於該第二介電層上並具 有複數導電跡線之第二線路層、及設於該第二介電層中並 電性連接該第一與第二線路層之第二導電盲孔，而該第二 導電盲孔電性連接該導電通孔，以令其中一半導體晶片藉 由該第一導電盲孔、第二導電盲孔、該第二線路層之其中 一導電跡線及導電通孔電性連接至另一半導體晶片，且最 外層之第二線路層具有複數電性接觸墊；又於該增層結構 上形成絕緣保護層，且該絕緣保護層具有複數絕緣保護層 開孔，以令各該電性接觸墊對應外露於各該絕緣保護層開 孔，並於該電性接觸墊上形成表面處理層。 由上可知，本發明之封裝結構中嵌埋有複數半導體晶 片’而能增加半導體封裝結構之電性功能’亦能維持結構 輕薄短小之特性，且藉由複數貫穿該承載片及第一介電層 之導熱通孔，以增強該半導體晶片之導熱功能，而能避免 習知技術因為封裝結構中的熱累積導致封裝結構中介電層 分層或封裝結構爆板的問題。 8 111341 201110250 【實施方式】 • 以下藉由特定的具體實施例說明本發明之實施方 • 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2G圖，係為本發明所揭露之一種封裝 結構之製法。 如第2A及2A’圖所示，提供一金屬板20，係具有相對 之兩表面20a ;於本實施例中，該金屬板20係於框體200 • 中設有複數承載片201，且該些承載片201之間及其與框 體200之間具有連接部202，藉由該些接部202以連結各 該承載片201與該框體200。又本實施例所定義之兩表面 20a亦屬該承載片201。 如第2B圖所示，於各該承載片201之相對兩表面20a 上分別設置一半導體晶片21，令各該承載片201之相對兩 表面上各有一半導體晶片21，計各該承載片201接置有兩 I 個半導體晶片21 ;其中，各該半導體晶片21具有相對之 作用面21a及非作用面21b，且該作用面21a上具有複數 電極墊210，而該非作用面21b上形成有黏著層22以將該 半導體晶片21固設於該承載片201之表面20a上。 如第2C及2D圖所示，於該金屬板20之相對兩表面 20a上設置半固態狀之第一初始介電層230及第二初始介 電層231，且該第一初始介電層230具有開口 230a，以供 容置該半導體晶片21，如第2C圖所示；接著，進行壓合 製程，且壓合後之該第一、第二初始介電層230, 231係結 9 111341 201110250 合成一體，而形成固態之第一介電層23;其中，該第一及 第二初始介電層230,231可為相同或不同材質；再者，該 第一初始介電層230係具有對應該半導體晶片21之開口 230a，以令壓合後之第一介電層23均勻包覆該金屬板20 及各該半導體晶片21 ;又該第一介電層23具有相對之第 一及第二表面23a，23b，且該第一介電層23上定義有對應 各該半導體晶片21與承載片201及其周圍之有效區A，如 第2D圖所示。 此外，於該金屬板20之相對兩表面20a上設置該第 一介電層23以包覆該半導體晶片21之製法，除了前述製 程外，亦可直接全面覆蓋該第一介電層23於該半導體晶片 21與該金屬板20表面20a上，並經熱壓以完成前述之結 構，如2D圖所示。 如第2E及2E’圖所示，於該第一介電層23之第一及 第二表面23a，23b上分別形成第一線路層24，且於該第一 介電層23中形成電性連接該第一線路層24及該些電極墊 210之第一導電盲孔240，並形成複數貫穿該第一介電層 23之第一及第二表面23a，23b之導電通孔25,以電性連接 該第一及第二表面23a，23b上之第一線路層24，如第2E 圖所示；又可形成複數貫穿該承載片201、第一介電層23 之第一及第二表面23a，23b之導熱通孔26，如第2E，圖所 示。 如第2F及2F’圖所示，於該第一介電層23及第一線 路層24上形成增層結構'27,該增層結構27具有至少一第 10 111341 201110250 二介電層270、設於該第二介電層270上之第二線路層 * 271、及設於該第二介電層270中並電性連接該第一與第二 • 線路層24, 271之第二導電盲孔272，且最外層之第二線路 層271具有複數電性接觸墊273，又該第二線路層271具 有複數導電跡線271a，271a’，271b。 所述之第二導電盲孔272電性連接該導電通孔25,以 令對應該第一表面23a之半導體晶片21、第一導電盲孔 240、第二導電盲孔272與第二線路層271之其中一導電跡 籲線271a’通過該導電通孔25電性連接至對應該第二表面 23b之第二導電盲孔272、第二線路層271之其中一導電跡 線271a’、第一導電盲孔240與半導體晶片21，俾以形成 一電性通路。 又於該增層結構27上形成絕緣保護層28，且該絕緣 保護層28中形成複數絕緣保護層開孔280，以令各該電性 接觸墊273對應外露於各該絕緣保護層開孔280中。 I 如第2G及2G’圖所示，沿著切割線S-S，藉由切割方 式移除該有效區A以外之部分，以形成複數封裝結構；請 一併參閱第3及3’圖，係為第2E及2E’圖之局部上視示意 圖。 本發明藉由貫穿該該第一介電層23及承載片201之 導熱通孔26，以令各該半導體晶片21間於製程中或半導 體晶片21於作動後能將累積的熱迅速逸散，因而不會產生 介電層分層或封裝結構爆板的情況，以有效確保產品之良 率及品質穩定性。 11 11134] 201110250 再者，藉由於該承載片201之兩表面20a上均設置半 導體晶片21，相較於習知技術之單一晶片，本發明之封裝 單元因同時具有兩半導體晶片21，因而能大幅提升電性功 能。 如第2H圖所示，可於該電性接觸墊273上形成表面 處理層29，且形成該表面處理層29之材料係選自由化學 鍵鎮/金、化錄浸金（ΕΝ IG)、化鎳Is浸金（ΕΝΕΡIG )、化學鐘 錫（I匪ersion Tin)及有機保焊劑（OSP)所組成之群組中之 其中一者。後續製程中，復可於該電性接觸墊273上形成 銲錫材料30，以於該絕緣保護層28上接置例如半導體元 件40之小型構件或例如電路板50之大型構件。 本發明復揭露一種封裝結構，係包括：具有相對之兩 表面20a之承載片201、分別設於該承載片201之相對兩 表面20a上之兩個半導體晶片21、覆蓋於該承載片201及 該些半導體晶片21之第一介電層23、以及形成於該第一 介電層23上之第一線路層24。 所述之各個半導體晶片21係具有相對之作用面21a 及非作用面21b，且該作用面21a上具有複數電極墊210， 而該非作用面21b係藉由黏著層22以將該半導體晶片21 固設於該承載片201上。 所述之第一介電層23具有相對之第一及第二表面 23a,23b;所述之第一線路層24係設於該第一介電層23 之第一及第二表面23a, 23b上，且該第一線路層24具有位 於該第一介電層23中並電性連接該半導體晶片21之電極 111341 201110250 墊210的第一導電盲孔240。 * 該封裝結構復包括複數貫穿該承載片201及第一介電 ' 層23之導熱通孔26 ;亦包括複數貫穿該第一介電層23之 導電通孔25,以電性連接該第一及第二表面23a，23b上之 第一線路層24。 所述之封裝結構復包括設於該第一介電層23及第一 線路層24上之增層結構27,該增層結構27係具有至少一 第二介電層270、設於該第二介電層270上之第二線路層 _ 271、及設於該第二介電層270中並電性連接該第一與第二 線路層24, 271之第二導電盲孔272，且最外層之第二線路 層271具有複數電性接觸墊273，又該第二線路層271具 有複數導電跡線271a, 271a’，271b ;其中，該第二導電盲 孔272電性連接該導電通孔25，以令該第一表面23a下方 之半導體晶片21藉由該第一導電盲孔240、第二導電盲孔 272、第二線路層271之其中一導電跡線271a’及導電通孔 φ 25電性連接至該第二表面23b下方之半導體晶片21。 又包括設於該增層結構27上之絕緣保護層’28，該絕 緣保護層28具有複數絕緣保護層開孔280，以令各該電性 接觸墊273對應外露於各該絕緣保護層開孔280，且可包 括設於該電性接觸墊273上之表面處理層29。 綜上所述，本發明之封裝結構藉由貫穿該第一介電層 及承載片之導熱通孔，以令該第一介電層與各該半導體晶 片間於製程中或半導體晶片於作動後不易受熱變形能將累 積的熱迅速逸散，因而不會產生介電層分層或封裝結構爆 13 111341 201110250 板的情況’以有效確保產品之良率及品質穩定性。 丄—再者’該封裝單元因同時具有兩半導體晶片，且各該 :導fea日片之非作用面結合於該承载片上，並藉由貫穿該 ^载片及第-介電層之導熱通孔，以增強該半導體晶片之 ¥熱功能，俾能有效提升該封裝結構之功能性。 上地貫施例係用以例示性說明本發明之原理及其功 ^，=_於_本發明。任何熟習此項技藝之人士均可 改二:2及範訂，對上述實施例進行修 圍所列。發明之權郝護範® ’應如後述之申請專利範 【圖式簡單說明】 第1圖係為習知封裝結構之剖視示意圖； 中，=，ί2Η圖係為本發明封裝結構之製法示意圖；^ :弟，系為第^圖之上視示意圖，第2 # 為弟f至2G圖之另—態樣；以及 意圖弟3至3,圖係為本發明封裝結構之不同態樣之上視开 【主要元件符號說明】 10 承載板 1〇1，25導電通孔 11a，21a作用面 110, 210電極墊 13 線路層 131，273電性接觸墊 100, 230a :開ο 11, 21 半導體晶片 lib, 21b 非作用面 12 介電層 130 導電盲孔 14 防焊層 1Π341 ]4 201110250 140 開孔 20 金屬板 20a 表面 200 框體 201 承載片 202 連接部 22 黏著層 23 第一介電層 230 第一初始介電層 231 第二初始介電層 23a 第一表面 23b 第二表面 24 第一線路層 240 第一導電盲孔 26 導熱通孔 27 增層結構 270 第二介電層 271 第二線路層 271a, 271a’，271b 導電跡線 272 第二導電盲孔 28 絕緣保護層 280 絕緣保護層開孔 29 表面處理層 30 銲錫材料 40 半導體元件 50 電路板 A 有效區 S 切割線 15 川341201110250 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a package structure capable of improving electrical functions and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, electronic products are also developing in the direction of light, thin, short, small, high integration and multi-functionality. In order to meet the packaging requirements of the integration and miniaturization of the package structure, the package form is gradually evolved from a single-chip ball grid array (bga) package or flip chip (FC) package to 3D. The package and the modular package form have various forms such as SiP (System in Package), SIP (Sys1: em Integrated Package), and SiB (System in Board). However, these 3D and modular packaged cancers are based on f1 ip chip or wire bonding, and the plurality of semiconductor elements are arranged in a planar arrangement on a substrate, or surface-bonded. Technology (SMT) adheres to the surface of the substrate. However, these components are all distributed on the surface of the substrate, which is disadvantageous for the size reduction of the modular structure and the improvement of performance. For this reason, the industry has proposed to embed a semiconductor wafer in a south density circuit, and vice versa; as shown in FIG. 1, a carrier board 10 having an opening 1 ′ is first provided, and a semiconductor wafer is accommodated in the opening 100. 11. The semiconductor wafer 11 has an active surface 11a and an inactive surface lib' having a plurality of electrode pads 110 on the active surface 11a, and on the active surface 11a and the non-active surface lib of the carrier 10 and the semiconductor wafer 11. Forming at least one dielectric layer 1 Π 341 4 201110250 12 ′ and the dielectric layer 12 is formed in the gap between the opening loo and the semiconductor wafer ′ to fix the semiconductor wafer n in the opening _ to the dielectric layer 丨 2 A circuit layer 13 is formed thereon, and the circuit layer a is electrically connected to the plurality of conductive vias 13 formed in the dielectric layer 12, and is further connected to the carrier board 1 and The conductive layer 101 is formed in the electrical layer 12 to electrically connect the circuit layers 13 on both sides of the carrier board 1 and the circuit layer 13 on the outer layer has a plurality of electrical contact pads 131. A solder resist layer 14 is formed on the outermost dielectric layer 12 and the circuit layer 13 , and the solder resist layer has a plurality of openings 140 in the solder mask layer for each of the electrical contact pads 131 to be exposed to each of the openings 140 . . "The high-density circuit board structure in which the semiconductor wafer is buried is only a single semiconductor wafer 11 embedded in the carrier board, and the electrical function of the single semiconductor wafer 11 is limited, so that it is not suitable for today's versatility and high. The use of electronic products for efficacy. In addition, the thermal conductivity coefficient (CTE) between the dielectric layer 12 and the semiconductor wafer is different, and is susceptible to thermal stress and warp deformation in the thermal cycle. Therefore, it is easy to cause delamination; or because the semiconductor wafer u is embedded in the carrier plate 1 , a large amount of heat is accumulated in the operation of the semiconductor wafer 11 , and thus a problem such as a board explosion occurs; therefore, the product is good. The rate and quality stability are poor. Therefore, how to propose a package structure to avoid the delamination of the conventional circuit board structure due to thermal stress, and the multi-functional, high-efficiency characteristic structure SUMMARY OF THE INVENTION [Invention] 5 Π 134] 201110250 In view of the above-mentioned various deficiencies of the prior art, one of the objects of the present invention is to provide a A package structure and a method for manufacturing the same are disclosed in the prior art. A further object of the present invention is to provide a package structure capable of improving electrical functions and a method of fabricating the same. To achieve the above and other objects, the present invention discloses a package structure comprising: a carrier sheet having opposite surfaces; and two semiconductor wafers respectively disposed on opposite surfaces of the carrier sheet, each of the semiconductor wafer systems The working surface has a plurality of electrode pads, and the semiconductor wafer is fixed on the carrier by the non-active surface; the first dielectric layer covers the carrier and And a first circuit layer disposed on the surface of the first dielectric layer, and the first circuit layer has a first conductive via hole in the first dielectric layer to electrically connect the electrode pad. The package structure includes an adhesive layer disposed between the inactive surface of the semiconductor wafer and the carrier to fix the semiconductor wafer on the carrier. The package structure includes a plurality of thermal vias extending through the carrier and the first dielectric layer, and a plurality of conductive vias extending through the first dielectric layer to electrically connect the first circuit layer. The structure includes a build-up structure disposed on the first dielectric layer and the first circuit layer, the build-up structure having at least one second dielectric layer disposed on the second dielectric layer and having a plurality of conductive traces a second circuit layer of the line, and a second conductive blind hole disposed in the second dielectric layer and electrically connected to the first and second circuit layers, and the second circuit layer of the outermost layer has a plurality of wires And the second conductive via is electrically connected to the conductive via such that one of the semiconductor wafers is electrically conductive by the first conductive via, the second conductive via, and the second wiring layer The traces and the conductive vias are electrically connected to another semiconductor wafer. In addition, an insulating protective layer is disposed on the layered structure, and the insulating protective layer has a plurality of insulating protective layer openings, so that each of the electrical contact pads is exposed to each of the insulating protective layer openings, and further includes a surface The treatment layer is disposed on the electrical contact pad. The present invention discloses a method for manufacturing a package structure, comprising: providing a metal plate having a plurality of carrier sheets, and each of the opposite surfaces of the carrier sheets is respectively provided with a semiconductor wafer, each of the semiconductor wafers having a relative active surface and The non-active surface has a plurality of electrode pads, and the semiconductor wafer is fixed on the carrier by the non-active surface; a dielectric layer is formed on the metal plate and each of the semiconductor wafers And covering the metal plate and each of the semiconductor wafers, wherein the first dielectric layer defines an active region corresponding to each of the semiconductor wafers; forming a first circuit layer on the surface of the first dielectric layer, and in the first dielectric layer Forming a first conductive via hole electrically connected to the first circuit layer and the electrode pad; and removing a portion other than the effective region to form a plurality of package structures. In the above method, the metal plate is formed by the frame connecting the carrier sheets, and the carrier sheets have a connection portion between the carrier sheets and the frame; the non-active surface of the semiconductor wafer and the carrier An adhesive layer is formed between the sheets to fix the semiconductor wafer on the carrier sheet, and the effective area can correspond to each of the carrier sheets. In the above method, the first dielectric layer is formed on the opposite surfaces of the metal plate by press-fitting, and the portion other than the effective area is removed by cutting. The method of the present invention includes forming a plurality of thermal vias extending through the carrier and the first dielectric layer, and forming a plurality of conductive vias extending through the first dielectric layer to electrically connect the first circuit layers. The method further includes forming a build-up structure on the first dielectric layer and the first circuit layer before removing the portion other than the active region, the build-up structure having at least one second dielectric layer disposed thereon a second circuit layer having a plurality of conductive traces on the second dielectric layer, and a second conductive via hole disposed in the second dielectric layer and electrically connecting the first and second circuit layers, and the The two conductive blind vias are electrically connected to the conductive vias to make one of the semiconductor wafers electrically conductive by the first conductive via, the second conductive via, the conductive trace of the second wiring layer, and the conductive via Connecting to another semiconductor wafer, and the outermost second circuit layer has a plurality of electrical contact pads; and an insulating protective layer is formed on the build-up structure, and the insulating protective layer has a plurality of insulating protective layer openings to The electrical contact pads are exposed to the openings of the insulating protective layers, and a surface treatment layer is formed on the electrical contact pads. It can be seen from the above that the package structure of the present invention is embedded with a plurality of semiconductor wafers, and the electrical function of the semiconductor package structure can be increased, and the structure can be kept light, thin and short, and the carrier and the first dielectric are penetrated through the plurality of carriers. The thermal via of the layer enhances the thermal conductivity of the semiconductor wafer, and the prior art can avoid the problem of dielectric layer delamination or package rupture of the package structure due to heat accumulation in the package structure. 8111341 201110250 [Embodiment] The following embodiments of the present invention are described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. Please refer to Figures 2A to 2G, which are a method of fabricating a package structure disclosed in the present invention. As shown in FIGS. 2A and 2A', a metal plate 20 is provided with opposite surfaces 20a. In this embodiment, the metal plate 20 is provided with a plurality of carrier sheets 201 in the frame 200. A connecting portion 202 is disposed between the supporting sheets 201 and the frame 200. The connecting portions 202 are used to connect the supporting sheets 201 and the frame 200. The two surfaces 20a defined in this embodiment are also the carrier sheets 201. As shown in FIG. 2B, a semiconductor wafer 21 is disposed on each of the opposite surfaces 20a of each of the carrier sheets 201, such that each of the opposite surfaces of the carrier sheet 201 has a semiconductor wafer 21, and each of the carrier sheets 201 is connected. There are two semiconductor wafers 21; wherein each of the semiconductor wafers 21 has an opposite active surface 21a and an inactive surface 21b, and the active surface 21a has a plurality of electrode pads 210, and the non-active surface 21b is formed with an adhesive layer. 22 is to fix the semiconductor wafer 21 on the surface 20a of the carrier sheet 201. As shown in FIGS. 2C and 2D, a first initial dielectric layer 230 and a second initial dielectric layer 231 are disposed on the opposite surfaces 20a of the metal plate 20, and the first initial dielectric layer 230 is disposed. An opening 230a is provided for accommodating the semiconductor wafer 21, as shown in FIG. 2C; then, a pressing process is performed, and the first and second initial dielectric layers 230, 231 are bonded after pressing 9 111341 201110250 The first and second initial dielectric layers 230, 231 may be the same or different materials; further, the first initial dielectric layer 230 has a corresponding semiconductor. The opening 230a of the wafer 21 is such that the pressed first dielectric layer 23 uniformly covers the metal plate 20 and each of the semiconductor wafers 21; the first dielectric layer 23 has opposite first and second surfaces 23a And 23b, and the first dielectric layer 23 defines an effective area A corresponding to each of the semiconductor wafer 21 and the carrier sheet 201 and its surroundings, as shown in FIG. 2D. In addition, the first dielectric layer 23 is disposed on the opposite surfaces 20a of the metal plate 20 to cover the semiconductor wafer 21, and the first dielectric layer 23 may be directly covered in the entire process except the foregoing process. The semiconductor wafer 21 and the surface 20a of the metal plate 20 are hot pressed to complete the foregoing structure, as shown in Fig. 2D. As shown in FIGS. 2E and 2E', a first wiring layer 24 is formed on the first and second surfaces 23a, 23b of the first dielectric layer 23, and electrical properties are formed in the first dielectric layer 23. Connecting the first conductive layer 24 and the first conductive vias 240 of the electrode pads 210, and forming a plurality of conductive vias 25 extending through the first and second surfaces 23a, 23b of the first dielectric layer 23 to electrically The first circuit layer 24 on the first and second surfaces 23a, 23b is connected as shown in FIG. 2E; and the first and second surfaces of the carrier sheet 201 and the first dielectric layer 23 are formed in plurality. The thermal vias 26 of 23a, 23b are as shown in Fig. 2E. As shown in FIGS. 2F and 2F', a build-up structure '27 is formed on the first dielectric layer 23 and the first circuit layer 24, and the build-up structure 27 has at least a 10th 111341 201110250 dielectric layer 270, a second circuit layer * 271 disposed on the second dielectric layer 270, and a second conductive layer disposed in the second dielectric layer 270 and electrically connected to the first and second circuit layers 24, 271 The hole 272, and the outermost second circuit layer 271 has a plurality of electrical contact pads 273, and the second circuit layer 271 has a plurality of conductive traces 271a, 271a', 271b. The second conductive via 272 is electrically connected to the conductive via 25 to make the semiconductor wafer 21, the first conductive via 240, the second conductive via 272 and the second wiring layer 271 corresponding to the first surface 23a. One of the conductive traces 271a' is electrically connected to the second conductive via 272 corresponding to the second surface 23b, one of the conductive traces 271a' of the second wiring layer 271, and the first conductive The blind vias 240 and the semiconductor wafer 21 are formed to form an electrical path. An insulating protective layer 28 is formed on the build-up structure 27, and a plurality of insulating protective layer openings 280 are formed in the insulating protective layer 28, so that the electrical contact pads 273 are correspondingly exposed to the insulating protective layer openings 280. in. I, as shown in Figures 2G and 2G', along the cutting line SS, remove portions other than the effective area A by cutting to form a plurality of package structures; please refer to Figures 3 and 3' together. A partial top view of the 2E and 2E' figures. The present invention can quickly dissipate the accumulated heat between the semiconductor wafers 21 during the process or after the semiconductor wafers 21 are actuated by the heat conducting vias 26 extending through the first dielectric layer 23 and the carrier sheet 201. Therefore, the dielectric layer delamination or the package structure explosion is not generated, so as to effectively ensure the yield and quality stability of the product. 11 11134] 201110250 Furthermore, since the semiconductor wafer 21 is disposed on both surfaces 20a of the carrier sheet 201, the package unit of the present invention can have a large number of semiconductor wafers 21 due to the single wafer of the prior art. Improve electrical function. As shown in FIG. 2H, a surface treatment layer 29 may be formed on the electrical contact pad 273, and the material forming the surface treatment layer 29 is selected from the group consisting of chemical bond/gold, chemical immersion gold (ΕΝIG), and nickel. One of a group consisting of Is Immersion Gold (ΕΝΕΡIG), Chemical Tin Tin (I匪ersion Tin), and Organic Soldering Agent (OSP). In the subsequent process, a solder material 30 is formed on the electrical contact pad 273, so that a small component such as the semiconductor component 40 or a large component such as the circuit board 50 is attached to the insulating protective layer 28. The present invention discloses a package structure comprising: a carrier sheet 201 having opposite surfaces 20a, two semiconductor wafers 21 respectively disposed on opposite surfaces 20a of the carrier sheet 201, covering the carrier sheet 201 and the a first dielectric layer 23 of the semiconductor wafer 21 and a first wiring layer 24 formed on the first dielectric layer 23. Each of the semiconductor wafers 21 has an opposite active surface 21a and an inactive surface 21b, and the active surface 21a has a plurality of electrode pads 210, and the non-active surface 21b is adhered to the semiconductor wafer 21 by the adhesive layer 22. It is disposed on the carrier sheet 201. The first dielectric layer 23 has opposite first and second surfaces 23a, 23b; the first circuit layer 24 is disposed on the first and second surfaces 23a, 23b of the first dielectric layer 23. The first circuit layer 24 has a first conductive blind via 240 located in the first dielectric layer 23 and electrically connected to the electrode 111341 201110250 pad 210 of the semiconductor wafer 21 . The package structure includes a plurality of thermal vias 26 extending through the carrier 201 and the first dielectric layer 23; and a plurality of conductive vias 25 extending through the first dielectric layer 23 to electrically connect the first And a first circuit layer 24 on the second surface 23a, 23b. The package structure includes a build-up structure 27 disposed on the first dielectric layer 23 and the first circuit layer 24. The build-up structure 27 has at least one second dielectric layer 270 disposed on the second a second circuit layer 271 on the dielectric layer 270, and a second conductive via 272 disposed in the second dielectric layer 270 and electrically connected to the first and second circuit layers 24, 271, and the outermost layer The second circuit layer 271 has a plurality of electrical contact pads 273, and the second circuit layer 271 has a plurality of conductive traces 271a, 271a', 271b; wherein the second conductive vias 272 are electrically connected to the conductive vias 25 The semiconductor wafer 21 under the first surface 23a is electrically connected to one of the first conductive via 240, the second conductive via 272, the second conductive layer 271, and the conductive via φ 25 The semiconductor wafer 21 is connected to the second surface 23b. In addition, the insulating protective layer 28 is disposed on the build-up structure 27, and the insulating protective layer 28 has a plurality of insulating protective layer openings 280, so that the electrical contact pads 273 are correspondingly exposed to the insulating protective layer openings. 280, and may include a surface treatment layer 29 disposed on the electrical contact pad 273. In summary, the package structure of the present invention passes through the thermal vias of the first dielectric layer and the carrier to allow the first dielectric layer and the semiconductor wafer to be in the process or after the semiconductor wafer is activated. It is not easy to be subjected to thermal deformation, and the accumulated heat is quickly dissipated, so that the dielectric layer delamination or the package structure is not generated to effectively ensure the yield and quality stability of the product.丄 - Furthermore, the package unit has two semiconductor wafers at the same time, and each of the non-active surfaces of the fea day film is bonded to the carrier sheet, and the heat conduction through the carrier sheet and the first dielectric layer The hole is used to enhance the heat-suppressing function of the semiconductor wafer, and the function of the package structure can be effectively improved. The above embodiments are used to exemplify the principles of the present invention and its work. Anyone who is familiar with the art can change the two: 2 and the specifications, and the above examples are listed. The right to invent the invention Hao Fanfan® 'should be as described later in the patent application form [simplified description of the drawings] Figure 1 is a schematic cross-sectional view of a conventional package structure; in the middle, =, ί2Η is a schematic diagram of the manufacturing process of the package structure of the present invention ;^ :弟, is the top view of the ^ figure, the second # is the other aspect of the brother f to 2G; and the intention of the brother 3 to 3, the figure is the different aspects of the package structure of the invention视开[Main component symbol description] 10 carrier board 1〇1, 25 conductive vias 11a, 21a active surface 110, 210 electrode pad 13 circuit layer 131, 273 electrical contact pad 100, 230a: open 11, 11, semiconductor wafer Lib, 21b Inactive surface 12 Dielectric layer 130 Conductive blind hole 14 Solder mask 1Π341 ]4 201110250 140 Opening 20 Metal plate 20a Surface 200 Frame 201 Carrier sheet 202 Connection portion 22 Adhesive layer 23 First dielectric layer 230 An initial dielectric layer 231 a second initial dielectric layer 23a a first surface 23b a second surface 24 a first circuit layer 240 a first conductive blind hole 26 a thermal via 27 a build-up structure 270 a second dielectric layer 271 a second circuit layer 271a, 271a', 271b conductive trace 272 second Blind hole 28 electrically insulating protective layer 280 insulating protective layer surface treatment layer 30 openings 29 solder material 40 semiconductor element active region 50 of the circuit board A cut line 15 Chuan S 341

Claims (1)

201110250 七、申請專利範圍： 1. 一種封裝結構，係包括： 承載片，係具有相對之兩表面； 二半導體晶片’係分別設於該承載片之相對兩衣面 上，且各該半導體晶片係具有相對之作用面及非作用 面，該作用面上具有複數電極墊，而該半導體晶片係藉 由該非作用面固設於該承載片上； 第一介電層’係包覆該承載片及半導體晶片；以及 第一線路層，係設於該第一介電層表面上，且該第 一線路層具有位於該第一介電層中以電性連接該電極 墊之第一導電盲孔。 2. 如申請專利範圍第1項之封裝結構，復包括黏著層，係 設於該半導體晶片之非作用面與該承載片之間，以將該 半導體晶片固設於該承載片上。 3. 如申請專利範圍第1項之封裝結構，復包括複數導熱通 孑L，係貫穿該承載片及第一介電層。 4. 如申請專利範圍第1項之封裝結構，復包括複數導電通 孑L，係貫穿該第一介電層，以電性連接該些第一線路層。 5. 如申請專利範圍第1項之封裝結構，復包括增層結構， 係設於該第一介電層及第一線路層上，該增層結構具有 至少一第二介電層、設於該第二介電層上並具有複數導 電跡線之第二線路層、及設於該第二介電層中並電性連 接該第一與第二線路層之第二導電盲孔，且最外層之第 二線路層具有複數電性接觸墊。 】6 111341 201110250 6. 如申請專利範圍第5項之封裝結構，復包括導電通孔， 係貫穿該第一介電層，以電性連接對應該承載片相對之 兩表面上方之第一線路層。 7. 如申請專利範圍第6項之封裝結構，其中，該第二導電 盲孔電性連接該導電通孔，以令其中一半導體晶片藉由 該第一導電盲孔、第二導電盲孔、該第二線路層之其中 一導電跡線及導電通孔電性連接至另一半導體晶片。 8. 如申請專利範圍第5項之封裝結構，復包括絕緣保護 層，係設於該增層結構上，且該絕緣保護層具有複數絕 緣保護層開孔，以令各該電性接觸墊對應外露於各該絕 緣保護層開孔。 9. 如申請專利範圍第5項之封裝結構，復包括表面處理 層，係設於該電性接觸塾上。 10. —種封裝結構之製法，係包括： 提供一具有複數承載片之金屬板，且各該承載片之 相對兩表面上分別設置一半導體晶片，各該半導體晶片 係具有相對之作用面及非作用面，且該作用面上具有複 數電極塾，而該半導體晶片係错由該非作用面固設於該 承載片上； 於該金屬板及各該半導體晶片上形成第一介電 層，以包覆該金屬板及各該半導體晶片，且該第一介電 層上定義有對應各該半導體晶片之有效區， 於該第一介電層表面上形成第一線路層，且於該第 一介電層中形成電性連接該第一線路層及電極墊之第 17 111341 201110250 一導電盲孔；以及 移除該有效區以外之部分，以形成複數封裝結構。 11. 如申請專利範圍第10項之封裝結構之製法，其中，該 金屬板係由框體連結各該承載片所構成。 12. 如申請專利範圍第11項之封裝結構之製法，其中，該 些承載片之間與承載片及框體之間具有連接部。 13. 如申請專利範圍第10項之封裝結構之製法，復包括於 該半導體晶片之非作用面與該承載片之間形成黏著 層，以將該半導體晶片固設於該承載片上。 14. 如申請專利範圍第10項之封裝結構之製法，其中，該 第一介電層之有效區係對應各該承載片。 15. 如申請專利範圍第10項之封裝結構之製法，其中，該 第一介電層係以壓合方式形成於該金屬板之相對兩表 面上。 16. 如申請專利範圍第10項之封裝結構之製法，其中，移 除該有效區以外之部分係藉由切割方式。 17. 如申請專利範圍第10項之封裝結構之製法，復包括形 成複數貫穿該承載片及第一介電層之導熱通孔。 18. 如申請專利範圍第10項之封裝結構之製法，復包括形 成複數貫穿該第一介電層之導電通孔，以電性連接該些 第一線路層。 19. 如申請專利範圍第10項之封裝結構之製法，復包括於 移除該有效區以外之部分之前，於該第一介電層及第一 線路層上形成增層結構，該增層結構具有至少一第二介 18 1Π341 201110250 電層、設於該第二介電層上並具有複數導電跡線之第二 ' 線路層、及設於該第二介電層中並電性連接該第一與第 二線路層之第二導電盲孔，且最外層之第二線路層具有 複數電性接觸墊。 20.如申請專利範圍第19項之封裝結構之製法，復包括於 形成該增層結構之前，形成貫穿該第一介電層之導電通 孔，以電性連接對應該承載片相對之兩表面上方之第一 線路層。 鲁21.如申請專利範圍第20項之封裝結構之製法，其中，該 第二導電盲孔電性連接該導電通孔，以令其中一半導體 晶片藉由該第一導電盲孔、第二導電盲孔、該第二線路 層之其中一導電跡線及導電通孔電性連接至另一半導 體晶片。 22. 如申請專利範圍第19項之封裝結構之製法，復包括於 該增層結構上形成絕緣保護層，且該絕緣保護層具有複 I 數絕緣保護層開孔，以令各該電性接觸墊對應外露於各 該絕緣保護層開孔。 23. 如申請專利範圍第19項之封裝結構之製法，復包括於 該電性接觸墊上形成表面處理層。 19 川341201110250 VII. Patent application scope: 1. A package structure comprising: a carrier sheet having opposite surfaces; two semiconductor wafers respectively disposed on opposite garment surfaces of the carrier sheet, and each of the semiconductor wafer systems The working surface has a plurality of electrode pads, and the semiconductor wafer is fixed on the carrier by the non-active surface; the first dielectric layer covers the carrier and the semiconductor And a first circuit layer disposed on the surface of the first dielectric layer, and the first circuit layer has a first conductive via hole in the first dielectric layer to electrically connect the electrode pad. 2. The package structure of claim 1, further comprising an adhesive layer disposed between the inactive surface of the semiconductor wafer and the carrier to secure the semiconductor wafer to the carrier. 3. The package structure of claim 1 of the patent application, comprising a plurality of thermal conduction ports L, extending through the carrier sheet and the first dielectric layer. 4. The package structure of claim 1, wherein the plurality of conductive vias L extend through the first dielectric layer to electrically connect the first circuit layers. 5. The package structure of claim 1 , further comprising a build-up structure disposed on the first dielectric layer and the first circuit layer, the build-up structure having at least one second dielectric layer disposed on a second circuit layer having a plurality of conductive traces on the second dielectric layer, and a second conductive via hole disposed in the second dielectric layer and electrically connecting the first and second circuit layers, and The second circuit layer of the outer layer has a plurality of electrical contact pads. 6 111341 201110250 6. The package structure of claim 5, further comprising a conductive via extending through the first dielectric layer to electrically connect the first circuit layer above the opposite surfaces of the corresponding carrier sheet . 7. The package structure of claim 6, wherein the second conductive via is electrically connected to the conductive via such that the semiconductor wafer passes through the first conductive via, the second conductive via, One of the conductive traces and the conductive via of the second circuit layer is electrically connected to another semiconductor wafer. 8. The package structure of claim 5, wherein the insulating protective layer is provided on the build-up structure, and the insulating protective layer has a plurality of insulating protective layer openings, so that the electrical contact pads correspond to each Exposed to each of the insulating protective layer openings. 9. The package structure of claim 5, further comprising a surface treatment layer disposed on the electrical contact port. 10. A method of fabricating a package structure, comprising: providing a metal plate having a plurality of carrier sheets, and each of the opposite surfaces of the carrier sheet is respectively provided with a semiconductor wafer, each of the semiconductor wafers having a relative action surface and a non- The active surface has a plurality of electrodes 塾, and the semiconductor wafer is erected on the carrier by the non-active surface; a first dielectric layer is formed on the metal plate and each of the semiconductor wafers to cover The metal plate and each of the semiconductor wafers, and the first dielectric layer defines an active region corresponding to each of the semiconductor wafers, forming a first circuit layer on the surface of the first dielectric layer, and the first dielectric layer A conductive blind via 17 111341 201110250 electrically connected to the first wiring layer and the electrode pad is formed in the layer; and a portion other than the active region is removed to form a plurality of package structures. 11. The method of fabricating a package structure according to claim 10, wherein the metal plate is formed by connecting the carrier sheets to each of the carrier sheets. 12. The method of claim 11, wherein the carrier sheets have a connection between the carrier sheet and the frame. 13. The method of fabricating a package structure according to claim 10, further comprising forming an adhesive layer between the inactive surface of the semiconductor wafer and the carrier sheet to fix the semiconductor wafer on the carrier sheet. 14. The method of fabricating a package structure according to claim 10, wherein the effective area of the first dielectric layer corresponds to each of the carrier sheets. 15. The method of fabricating a package structure according to claim 10, wherein the first dielectric layer is formed on the opposite surfaces of the metal plate in a press-fit manner. 16. The method of manufacturing a package structure according to claim 10, wherein the portion other than the effective area is removed by cutting. 17. The method of fabricating a package structure of claim 10, comprising forming a plurality of thermally conductive vias extending through the carrier and the first dielectric layer. 18. The method of fabricating a package structure according to claim 10, further comprising forming a plurality of conductive vias extending through the first dielectric layer to electrically connect the first circuit layers. 19. The method of fabricating a package structure according to claim 10, further comprising forming a build-up structure on the first dielectric layer and the first circuit layer before removing the portion other than the effective region, the build-up structure An electric layer having at least one second dielectric layer 18 Π 341 201110250, a second 'circuit layer disposed on the second dielectric layer and having a plurality of conductive traces, and disposed in the second dielectric layer and electrically connected to the second dielectric layer A second conductive via of the first and second circuit layers, and the second circuit layer of the outermost layer has a plurality of electrical contact pads. 20. The method of fabricating a package structure according to claim 19, further comprising forming a conductive via extending through the first dielectric layer prior to forming the buildup structure to electrically connect the opposite surfaces of the corresponding carrier sheet The first line layer above. The method of manufacturing a package structure according to claim 20, wherein the second conductive via is electrically connected to the conductive via to enable one of the semiconductor wafers by the first conductive via and the second conductive The blind via, one of the conductive traces of the second circuit layer, and the conductive via are electrically connected to another semiconductor wafer. 22. The method of fabricating a package structure according to claim 19, further comprising forming an insulating protective layer on the build-up structure, and the insulating protective layer has a plurality of insulating insulating layer openings to make each of the electrical contacts The pad is correspondingly exposed to each of the insulating protective layer openings. 23. The method of fabricating a package structure according to claim 19, further comprising forming a surface treatment layer on the electrical contact pad. 19 Chuan 341
TW098129809A 2009-09-04 2009-09-04 Package substrate structure and method of forming same TWI417970B (en)

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