TW577153B - Cavity-down MCM package - Google Patents

Cavity-down MCM package Download PDF

Info

Publication number
TW577153B
TW577153B TW091138170A TW91138170A TW577153B TW 577153 B TW577153 B TW 577153B TW 091138170 A TW091138170 A TW 091138170A TW 91138170 A TW91138170 A TW 91138170A TW 577153 B TW577153 B TW 577153B
Authority
TW
Taiwan
Prior art keywords
cavity
chip package
package structure
type multi
down type
Prior art date
Application number
TW091138170A
Other languages
Chinese (zh)
Other versions
TW200411850A (en
Inventor
Yi-Chuan Ding
Yung-I Yeh
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW091138170A priority Critical patent/TW577153B/en
Priority to US10/747,191 priority patent/US20040150099A1/en
Application granted granted Critical
Publication of TW577153B publication Critical patent/TW577153B/en
Publication of TW200411850A publication Critical patent/TW200411850A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A cavity-down multi-chips package mainly comprises a substrate, a heat sink, a plurality of chips and a trace-redistributed carrier, wherein the substrate has an opening and the sink is connected to the substrate. In such manner, a cavity is defined, and the trace-redistributed carrier is disposed therein. A plurality of chips are attached onto the substrate via its back surfaces and electrically connected with the trace-redistributed carrier via a plurality of first conductive wires. In addition, the substrate is electrically connected with the trace-redistributed carrier via a plurality of second conductive wires. The signals are transmitted from the chips to the trace-redistributed carrier via the first conductive wires and then transmitted from the trace-redistributed carrier to the substrate via the second conductive wires. In such way, the transmission path for the signals will be reduced to improve the signals transmission performance.

Description

577153577153

(一）、【發明所屬之技術領域】 震構造，特 於該凹穴中 別右：：：係有關於一種晶穴朝T型多晶片封 < > a 一種具有一線路重分佈傳輸載板設置 之夕日日片封裝構造。 (二）、【先前技術】 (BGA一，考慮半導體晶片之整合方式，球格陣列 GA)封凌可為凹穴向上（cavity up)及凹穴向下 = vlty d0wn)等型態。請參照圖i所示之凹穴向下之球 二=列（BGA )封裝構造，其主要包含一半導體晶片丨〇、 一土板11及一散熱片12。該基板11具有一開口 lu，並設 置於鑪，熱片表面121上以定義一凹穴（未標示於圖中）。 另外"亥半導體晶片1 0亦同時藉由一黏著層1 7 (如導敎膠） 設置於散熱片表面121上，並容置於該凹穴中。¥ 一 請繼續參考圖1，半導體晶片主動表面1 0 1之晶片銲墊 1〇2另以導電線14(conductivewires)連接至設於該基板 幵 1 111週邊的晶片連接墊（chip bonding pad)113。再 者基板表面11 2設有複數個錫球銲墊11 4，其係位於該複 數個晶片連接塾11 3之週邊並分別電性連接至相對應之晶 片連接塾113。此外，該些錫球銲墊丨14係設有一銲球15用 f與外界電性連接。另有一封膠體丨6，其係包覆該半導體 晶片10、導電線14以及該基板丨丨開口丨丨i (包括該基板表 面11 2之一部分）。 接著’請參照圖2。承上所述，若於凹穴中（未標示於(1), [Technical Field to which the Invention belongs] Seismic structure, especially in the cavity :: Related to a cavity-shaped T-shaped multi-chip seal < > a transmission line with a redistribution transmission line On the eve of the board setting, the chip package structure is used. (2) [Previous technology] (BGA one, considering the integration mode of the semiconductor chip, the ball grid array GA) sealing can be of cavity up (cavity up) and cavity down (vlty d0wn) and other types. Please refer to FIG. I, the sphere-down ball 2 = column (BGA) package structure, which mainly includes a semiconductor wafer, a soil plate 11 and a heat sink 12. The substrate 11 has an opening lu, and is disposed on the surface of the hot plate 121 to define a cavity (not shown in the figure). In addition, the Hai semiconductor wafer 10 is also disposed on the surface 121 of the heat sink through an adhesive layer 17 (such as a conductive adhesive) and is accommodated in the cavity. ¥ Please continue to refer to FIG. 1. The wafer bonding pads 102 of the active surface 1 1 of the semiconductor wafer are connected to the chip bonding pads 113 on the periphery of the substrate 幵 111 by conductive wires 14 (conductive wires). . Furthermore, a plurality of solder ball pads 11 4 are provided on the substrate surface 11 2, which are located around the plurality of wafer connection 晶片 11 3 and are electrically connected to the corresponding wafer connection 塾 113 respectively. In addition, the solder ball pads 14 are provided with a solder ball 15 electrically connected to the outside by f. Another piece of colloid 6 covers the semiconductor wafer 10, the conductive wires 14, and the substrate 丨 opening 丨 i (including a part of the substrate surface 112). Next, 'please refer to FIG. 2. As mentioned above, if in the cavity (not marked in

577153 五、發明說明（2) 圖中）設置複數個半導體晶片2 0，則用以電性連接晶片銲 塾202與基板開口211週邊晶片連接墊（chip b(3ndil^ pad) 2 1 3之導電線24長度勢必加長，且配置也趨於複雜，因而 造成打線封裝技術之難度，且更容易降低電性訊號之傳遞 效能。需說明的是，圖2中各元件之參考符號係與中之 各元件之參考符號相對應。 有鑑於此，為避免前述半導體晶片封裝構造之缺點， 並降低打線封裝技術之複雜度，以提升半導體晶片封裝構 造中電性訊號之傳遞效能，實為一重要的課題。 有 線路重 緣 下型多 數個半 熱片相 重分佈 該些半 上，並 佈傳輸 其 輪載板 基板。 、【發明 鑑於上述 分佈傳輸 是，為了 晶片封裝 導體晶片 接合，且 載板係貼 導體晶片 藉由複數 載板而與 中，第一 ，而第二 由於該些 概要】 課題， 載板之 達成上 本發明之目的 晶穴朝下型多 述目的，本發 構造’其主要包括一 及一線路重分佈傳輸 散熱片與基板之開口 附於散熱片之表面上 背面設置於該 導電線及第二 性連接。 係電連接該些 係電性連接線 訊號先藉由第 係以其 個第一 基板電 導電線 導電線 晶片之 係在於 晶片封 明係提 基板、 載板。 係定義 以容置 線路重 導電線 提供一種具有 裝構造。 供一種晶穴朝 一散熱片、複 該基板係與散 一凹穴，而該 於該凹穴中。 分佈傳輸載板 經該線路重分 晶片與線路重分佈傳 路重分佈傳輸載板與 一導電線傳遞至線路577153 V. Description of the invention (2) In the figure, if a plurality of semiconductor wafers 20 are provided, they are used to electrically connect the wafer bonding pad 202 and the substrate opening 211 around the chip connection pad (chip b (3ndil ^ pad) 2 1 3 conductive). The length of the line 24 is bound to be longer, and the configuration is also becoming more complicated, which makes the packaging technology difficult and reduces the transmission efficiency of electrical signals. It should be noted that the reference symbols of each component in FIG. 2 are different from each other. The reference symbols of the components correspond. In view of this, in order to avoid the aforementioned shortcomings of the semiconductor chip packaging structure and reduce the complexity of wire packaging technology, in order to improve the transmission efficiency of electrical signals in the semiconductor chip packaging structure, it is an important issue. . The majority of the semi-heated sheets with the circuit heavy edge are redistributing these half halves and transmitting the wheel carrier board substrates. [Invention In view of the above-mentioned distributed transmission, it is for chip packaging conductor chip bonding, and the carrier board is pasted. The conductor chip is made up of a plurality of carrier plates, the first and the second are due to the summary] The problem that the carrier plate achieves the object of the present invention For the purpose of the downward type, the structure of the present invention mainly includes one and one circuit redistribution transmission fins and openings of the substrate attached to the surface of the fins. The back surface is provided on the conductive wire and the second connection. For these electrical connection line signals, the first is to use the first substrate electrically conductive line and the conductive line wafer to lay out the substrate and the carrier board. The system definition is to accommodate a line of heavy conductive lines to provide a mounting structure. A cavity is provided for a heat sink, the substrate system and a cavity, and the cavity is located in the cavity. The distribution transmission carrier board is redistributed by the circuit and the circuit redistribution circuit. Conductive line to line

577153 五、發明說明（3) 重分佈傳輸載板上，之後再經由第二導電線路傳導至基 板’以進一步傳送至外界，如母板（mother board)或其他 電子TL件，故可避免訊號藉由導電線而傳遞，如此經由線 路重分佈傳輸載板之導電線路層以傳遞訊號可提升半導體 晶片封裝構造中電性訊號之傳遞效能。 (四）、【實施方式】 以下將參照相關圖式，以說明本發明較佳實施例之晶 穴朝下型多晶片封裝構造。 如圖3所示，本發明之晶穴朝下型多晶片封裝構造主 要L括複數個半導體晶片3〇、一基板μ、一散熱片μ及一 線路重分佈傳輸載板38。其中，該基板31具有一表面312 及一開口311，而該基板31係設置於該散熱片“上，以藉 ，基板開口311與散熱片32定義一凹穴。又，該基板表面 12具有稷數個設置於基板開口311週邊之晶片連接墊 (chlp bonding pad)313，並分別電性連接至相對應之錫 Ϊΐί3,14 ’而該些錫料墊314係設有—銲祕用以與外 妾。再者’該線路重分佈傳輸載板38可設置於散 :二Λ以容置於該凹穴中。另外，複數個晶片30係以其 ^ t Λ不笛於圖5黏置於該、線路重分佈傳輸載板3 8上， ==弟一導電線341(如金線;㈤“㈣電性連接 ί0第ϊϊ/ΛΙ剛)與該線路重分佈傳輸載板38上 Ϊ L 該線路重分佈傳輪載板38上之 第一重刀佈㈣382係另以複數”m⑽與該基板 第8頁 577153 五、發明說明（4) 一 3 1上之晶片連接墊3 1 3電性連接。此外，另有一封膠體 36，用以包覆該半導體晶片3〇、第一導電線341、第二導 電線342以及該基板開口 31丄（包括該基板表面312之一部 分）。需說明的是’圖3中各元件之參考符號係與圖2中之 各元件之參考符號相對應。 承上所述’線路重分佈傳輸載板3 8可由複數個絕緣層 384及複數個導電線路層385彼此交替疊合形成於一核心板 材383上（如圖4所示），並藉由一黏著層（未標示於圖）與散 熱片相接合。其中，黏著層可為一導熱膠，而絕緣層384 之材質可為雙順丁烯二酸醯亞胺（Bismaleimide-577153 V. Description of the invention (3) Redistribution transmission carrier board, and then conducted to the substrate through the second conductive line for further transmission to the outside world, such as mother board or other electronic TL parts, so signal borrowing can be avoided It is transmitted by conductive lines, so that the signal is transmitted through the conductive circuit layer of the redistribution transmission carrier board to improve the transmission performance of the electrical signals in the semiconductor chip package structure. (IV) [Embodiment] Hereinafter, a cavity-down type multi-chip package structure according to a preferred embodiment of the present invention will be described with reference to related drawings. As shown in FIG. 3, the cavity-down type multi-chip package structure of the present invention mainly includes a plurality of semiconductor wafers 30, a substrate µ, a heat sink µ, and a circuit redistribution transmission carrier 38. Wherein, the substrate 31 has a surface 312 and an opening 311, and the substrate 31 is disposed on the heat sink "so that the substrate opening 311 and the heat sink 32 define a cavity. Furthermore, the substrate surface 12 has A plurality of chlp bonding pads 313 provided around the opening 311 of the substrate are electrically connected to the corresponding tin pads 3,14 ′, respectively. The solder pads 314 are provided—soldering and external妾. Furthermore, the line redistribution transmission carrier plate 38 may be disposed in the scattered: two Λ to be accommodated in the cavity. In addition, a plurality of wafers 30 are placed in the cavity with their ^ t Λ not flute in FIG. 5. 2. On the line redistribution transmission carrier board 38, == di-a conductive line 341 (such as a gold wire; ㈤ “㈣electrically connected ί0 第 ϊϊ / ΛΙ 刚”) and the line redistribution transmission carrier board 38 Ϊ L the line The first heavy knife cloth ㈣382 on the redistribution wheel carrier plate 38 is electrically connected to the substrate with a plurality of "m⑽" on page 8 of the 577153. V. Description of the invention (4) The wafer connection pad 3 1 3 on the 31. In addition, there is another colloid 36 for covering the semiconductor wafer 30, the first conductive line 341, the second conductive line 342, and the The board opening 31 丄 (including a part of the substrate surface 312). It should be noted that the reference symbols of each component in FIG. 3 correspond to the reference symbols of each component in FIG. The carrier board 38 can be formed by alternately overlapping a plurality of insulating layers 384 and a plurality of conductive circuit layers 385 on a core plate 383 (as shown in FIG. 4), and an adhesive layer (not shown in the figure) and heat dissipation The bonding layer can be a thermally conductive adhesive, and the material of the insulating layer 384 can be bismaleimide-imide (Bismaleimide-

Triazine，BT)、FR-4環氧樹脂或聚亞醯胺pj，Triazine, BT), FR-4 epoxy resin or polyimide pj,

Polyimide)，該些導電線路層385之材質可為一銅金屬。 另外，该線路重分佈傳輸載板3 8之第一重分佈銲墊3 8 }及 第二重分佈銲墊382係由複數個導電線路層385所組成且彼 此間係電性導通，以使半導體晶片3〇之訊號能藉由此線路 重分佈傳輸載板38重新份佈導通至基板31上。 另外，該線路重分佈傳輸載板3 8亦可藉由增層法將複 數個絕緣層（如BCB(Benzocyel〇butene)層）及複數個導電 線路層彼此交替疊合直接形成於散熱片32上（未標示於圖 中）。其製程可參考下述步驟：在基板31與散熱片32接合定 義一凹穴33後，將一絕緣層（如苯曱酸環丁烯（BCB)層）設 置於散熱片32表面後，接著設置光阻（可為乾膜（DF))於 絕緣層上，然後再透過曝光、顯影及電鍍等製程並去除光 阻，以形成一圖案化線路層於絕緣層上。重複上述步驟，Polyimide), the material of the conductive circuit layers 385 may be a copper metal. In addition, the first redistribution pads 3 8} and the second redistribution pads 382 of the line redistribution transmission carrier board 38 are composed of a plurality of conductive circuit layers 385 and are electrically connected to each other so that the semiconductor The signal of the chip 30 can be redistributed and conducted to the substrate 31 through the circuit redistribution transmission carrier plate 38. In addition, the circuit redistribution transmission carrier board 38 can also be formed on the heat sink 32 by alternately overlapping a plurality of insulating layers (such as a BCB (BenzocyelObutene) layer) and a plurality of conductive circuit layers by an overlay method. (Not shown in the figure). The process can refer to the following steps: After the substrate 31 and the heat sink 32 are joined to define a cavity 33, an insulating layer (such as a cyclobutene benzoate (BCB) layer) is disposed on the surface of the heat sink 32, and then set A photoresist (which may be a dry film (DF)) is placed on the insulating layer, and then the photoresist is removed through processes such as exposure, development, and electroplating to form a patterned circuit layer on the insulating layer. Repeat the above steps,

第9頁 577153 五、發明說明（5) ----- :f f熱片3 2上形成所需之線路層數。此外，亦可於散熱 朴 接形成一絕緣層，如聚亞醯胺（PI/Poly i mi de)。接 者1於絕緣層表面形成—銅箱層（copper foil layer)， 然後在此mi層上形成—圖案化的光阻層，並以此光阻層 為罩幕#刻除去局部的銅猪，再經過去除光阻層之後， 便可以得到所需之線路層數。 承上所述，請參照圖5，為本發明第二較佳實施例所 不，f導體晶片40係藉複數個導電凸塊441 (如銲錫凸塊） 以覆晶方式（flip chip bonding)與線路重分佈傳輸載板 48之第-重分佈銲墊481電性連接，而該線路重分佈傳輸 載板48上之第二重分佈銲墊482係另以複數個導電線與 該基板41上之晶片連接墊413電性連接。此外，另有一封 膠體46，用以包覆該半導體晶片4〇、導電凸塊441、導電 線442以及該基板開口 411 (包括該基板表面412之一部 分）。需說明的是，圖5中各元件之參考符號係與圖^中之 各元件之參考符號相對應。 於本實施例之詳細說明中所提出之具體的實施例僅 了易於說明本發明之技術内容’而並非將本發明狹義地限 制於該實施例，因此，在不超出本發明之精神及以 專利範圍之情況，可作種種變化實施。 μPage 9 577153 V. Description of the invention (5) -----: f f The number of layers required to form the circuit on the heat sheet 32. In addition, an insulating layer can be formed on the heat sink, such as polyimide (PI / Poly i mi de). The contactor 1 forms a copper foil layer on the surface of the insulation layer, and then forms a patterned photoresist layer on this mi layer, and uses the photoresist layer as a cover to remove the local copper pig, After removing the photoresist layer, the required number of circuit layers can be obtained. As mentioned above, please refer to FIG. 5, which is the second preferred embodiment of the present invention. The f-conductor wafer 40 borrows a plurality of conductive bumps 441 (such as solder bumps) in a flip-chip bonding manner. The first redistribution pad 481 of the redistribution transmission carrier board 48 is electrically connected, and the second redistribution pad 482 on the redistribution transmission carrier board 48 is connected to the substrate 41 by a plurality of conductive wires. The chip connection pad 413 is electrically connected. In addition, there is another piece of glue 46 for covering the semiconductor wafer 40, the conductive bumps 441, the conductive wires 442, and the substrate opening 411 (including a part of the substrate surface 412). It should be noted that the reference symbols of the components in FIG. 5 correspond to the reference symbols of the components in FIG. The specific embodiments proposed in the detailed description of this embodiment are only for easy explanation of the technical content of the present invention, and do not limit the present invention to the embodiment in a narrow sense. Therefore, the spirit of the present invention and the patent are not exceeded. The scope of the situation can be implemented in various changes. μ

577153 圖式簡單說明 (五）、【圖式之簡單說明】 圖1為一示意圖，顯示習知晶穴朝下型之半導體晶片 封裝構造。 圖2為一示意圖，顯示習知晶穴朝下型半導體多晶片 封裝構造。 圖3為一示意圖，顯示本發明第一較佳實施例中之晶 穴朝下型多晶片封裝構造。 圖4為一示意圖，顯示本發明較佳實施例中線路重分 佈傳輸載板之構造。577153 Brief description of the drawings (five), [Simplified description of the drawings] FIG. 1 is a schematic diagram showing a conventional semiconductor chip package structure with a cavity-down type. FIG. 2 is a schematic diagram showing a conventional cavity-down type semiconductor multi-chip package structure. Fig. 3 is a schematic diagram showing a cavity-down type multi-chip package structure in the first preferred embodiment of the present invention. Fig. 4 is a schematic diagram showing the structure of a line redistribution transmission carrier board in a preferred embodiment of the present invention.

圖5為一示意圖，顯示本發明第二較佳實施例中之晶 穴朝下型多晶片封裝構造。 元件符號說明： 10 半導體晶片 101 主動表面 I 0 2晶片銲墊 11 基板 111 基板開口 II 2 基板表面Fig. 5 is a schematic diagram showing a cavity-down type multi-chip package structure in a second preferred embodiment of the present invention. Component symbol description: 10 semiconductor wafer 101 active surface I 0 2 wafer pad 11 substrate 111 substrate opening II 2 substrate surface

11 3晶片連接墊 11 4 錫球銲墊 12 散熱片 1 2 1散熱片表面 14 導電線11 3 Wafer connection pad 11 4 Solder ball solder pad 12 Heat sink 1 2 1 Heat sink surface 14 Conductive wire

第11頁 577153 圖式簡單說明 15 銲 球 16 封 膠 體 17 黏 著 層 20 半 導 體 晶 片 202 晶 片 鮮 墊 211 基 板 開 D 213 晶 片 連 接 塾4 24 導 電 線 30 半 導 體 晶 片 31 基 板 311 基 板 開 Π 312 基 板 表 面 313 晶 片 連 接 墊 314 錫 球 銲 墊 32 散 熱 片 341 第 一 導 電 線 342 第 二 導 電 線 35 銲 球 36 封 膠 體 38 線 路 重 分 佈 381第一重分佈銲墊 3 8 2第二重分佈銲墊 3 8 3核心板材 3 8 4 絕緣層Page 11 577153 Brief description of drawings 15 Solder ball 16 Sealant 17 Adhesive layer 20 Semiconductor wafer 202 Wafer pad 211 Substrate opening D 213 Wafer connection 4 24 Conductive wire 30 Semiconductor wafer 31 Substrate 311 Substrate opening 312 Substrate surface 313 Wafer Connection pad 314 solder ball pad 32 heat sink 341 first conductive wire 342 second conductive wire 35 solder ball 36 sealant 38 circuit redistribution 381 first redistribution pad 3 8 2 second redistribution pad 3 8 3 core Sheet 3 8 4 Insulation

第12頁 577153 圖式簡單說明 3 8 5 導電線路層 40 半導體晶片 41 基板 4 11 基板開口 4 1 2 基板表面 413晶片連接塾 441 導電凸塊 442 導電線 46 封膠體 48 線路重分佈傳輸載板 481第一重分佈銲墊 482第二重分佈銲墊Page 12 577153 Brief description of the drawing 3 8 5 Conductive circuit layer 40 Semiconductor wafer 41 Substrate 4 11 Substrate opening 4 1 2 Substrate surface 413 Wafer connection 441 Conductive bump 442 Conductive wire 46 Sealant 48 Circuit redistribution transmission carrier board 481 First redistribution pad 482 Second redistribution pad

第13頁Page 13

Claims (1)

577153 六、申請專利範圍 1. 一種晶穴朝下型多晶片封裝構造，包含·· 一散熱片， 一基板，該基板具有一上表面、一下表面及一開口，該基 板係設置於該散熱片上，並以其上表面與該散熱片連接 以定義一凹穴； 一線路重分佈傳輸載板，係設置於該散熱X上以容置於該 凹穴中； 複數個半導體晶片，該些半導體晶片係設置於該線路重分 、—佈傳輸載板上並與該線路重分佈傳輸載板電性連接； m請專利範圍第i項之晶穴朝下型多晶片封裝構造， -封膠體’其係覆蓋該些半導體晶片及該些第二導電線。 3 ·如申請專利範圍第 其中該些半導體，i L項之晶穴朝下型多晶片封裝構造， 板電性連接。θ U打線方式與該線路重分佈傳輸載 4.如申請專利範圍 其中該些半導體曰曰項之曰曰八朝下型多晶片封裝構造， 板電性連接。 “以覆晶方式與該線路重分佈傳輪載577153 VI. Application patent scope 1. A cavity-down type multi-chip package structure, including a heat sink, a substrate, the substrate having an upper surface, a lower surface, and an opening, and the substrate is disposed on the heat sink And its upper surface is connected with the heat sink to define a cavity; a line redistribution transmission carrier board is arranged on the heat sink X to be accommodated in the cavity; a plurality of semiconductor wafers, the semiconductor wafers It is installed on the line redistribution and distribution transmission carrier board and is electrically connected to the line redistribution transmission carrier board. M Please call for the cavity-down type multi-chip package structure of item i of the patent scope, It covers the semiconductor wafers and the second conductive lines. 3 · As for the semiconductors in the scope of the application for patents, the i L item has a cavity-down type multi-chip package structure, and the board is electrically connected. θ U wiring method and redistribution of transmission load on this line 4. As the scope of the patent application, the semiconductors are called the multi-chip package structure of the eight-side down type, and the board is electrically connected. "Redistribution of wheel load to the line in a flip-chip manner 第14頁 577153 六、申請專利範圍 — 5 ·如申請專利範圍第 苴中哕绩玖舌八从朝下型多晶片封裝構造， 線複數個絕緣層及複數個導電 m: ί利乾圍第5項之晶穴朝下型多晶片封裝構造’ :、:^包έ 一黏著層設置於該線路重分佈傳輸載板與該基 板上表面間。 7·如申請專利範圍第5項之晶穴朝下型多晶構造， 其中該黏著層可為導熱膠。 8 ·如申請專利範圍第5項之晶穴朝下型多晶片封裝構造， 其中該些絕緣層之材質係雙順丁烯二酸醯亞胺 (Bismaleimide-Triazine， ΒΤ)。 9 ·如申請專利範圍第5項之晶穴朝下型多晶片封裝構造， 其中該些絕緣層之材質係為FR-4環氧樹脂。 I 0.如申請專利範圍第5項之晶穴朝下型多晶片封裝構造， 其中該些絕緣層之材質係為聚亞醯胺（p 〇 1 y i m i d e，P I)。 II ·如申請專利範圍第5項之晶穴朝下型多晶片封裝構造， 其中該些導電線路層之材質係為銅金屬。Page 14 577153 VI. Scope of patent application — 5 · If the scope of patent application is the first one, the multi-chip package structure with a downward-facing structure, a plurality of insulation layers and a plurality of conductive m: ί 利 乾 围 5 Xiang Zhi's cavity-down multi-chip package structure ':,: ^ package An adhesive layer is disposed between the circuit redistribution transmission carrier and the upper surface of the substrate. 7. The cavity-down type polycrystalline structure according to item 5 of the patent application scope, wherein the adhesive layer may be a thermally conductive adhesive. 8. The cavity-down type multi-chip package structure according to item 5 of the application, wherein the material of the insulating layers is bismaleimide-triazine (BT). 9 · If the cavity-down type multi-chip package structure of item 5 of the patent application scope, wherein the material of these insulating layers is FR-4 epoxy resin. I 0. The cavity-down type multi-chip package structure according to item 5 of the scope of the patent application, wherein the material of the insulating layers is polyimide (p 0 1 y i m i d e, PI). II. The cavity-down type multi-chip package structure according to item 5 of the application, wherein the material of the conductive circuit layers is copper metal. 第15頁 577153Page 15 577153 下型多晶片封裝構造， 線路層係以增層法疊合 1 2 ·如申請專利範圍第5項之晶穴朝 其中該複數個絕緣層及複數個導電 形成於該散熱片上。 13·如申請專利範圍第12項之晶穴朝下型多晶片封裝構 造其中該些絕緣層之材質係雙順丁烯二酸醯亞胺 (Bismaleimide-Triazine， BT)。 14. 如申請專利範圍第12項之晶穴朝下型多晶片封裝構 造，其中該些絕緣層之材質係為FR-4環氧樹脂。 15. 如申請專利範圍第12項之晶穴朝下型多晶片封裝構 造，其中s亥些絕緣層之材質係為聚亞醯胺（p〇lyimide， 1 6.如申明專利範圍第1 2項之晶穴朝下型多晶片封裝構 造，其中δ亥些絕緣層之材質係為苯甲酸環丁烯 (Benzocyelobutene，BCB) 〇 1 7 ·如申请專利fe圍第1 2項之晶穴朝下型多晶片封裝構 造，其中該些導電線路層之材質係為銅金屬。 1 8 ·如申印專利範圍第1項之晶穴朝下型多晶片封裝構造， 其中該基板下表面係具有複數個基板銲墊，該複數個基板In the lower-type multi-chip package structure, the circuit layers are superimposed by a build-up method. 1 · If the cavity of item 5 of the patent application is facing, the plurality of insulating layers and the plurality of conductive layers are formed on the heat sink. 13. If the cavity-down type multi-chip package of item 12 in the patent application is used to construct the insulating layer, the material of the insulating layer is bismaleimide-triazine (BT). 14. For example, the cavity-down type multi-chip package structure of item 12 of the patent application scope, wherein the material of these insulating layers is FR-4 epoxy resin. 15. For example, the cavity-down type multi-chip package structure with the scope of patent application No. 12 in which the material of the insulating layers is polyimide (16). The cavity-down-type multi-chip package structure, in which the material of the δ-H insulation layer is Benzocyelobutene (BCB) 〇1 7 · If the patent application for Fe-line No. 12 is the cavity-down type Multi-chip package structure, wherein the material of the conductive circuit layers is copper metal. 1 8 · The cavity-down type multi-chip package structure of item 1 in the scope of the application for printing, wherein the lower surface of the substrate has a plurality of substrates Pads, the plurality of substrates 577153 六、申請專利範圍 銲墊上另形成有複數個導電元件。 1 9·如申請專利範圍第1 8項之晶穴朝下型多晶片封裝構 造，其中該些導電元件係為銲球。 2 0.如申請專利範圍第4項之晶穴朝下型多晶片封裝構造， 其中該些半導體晶片係藉複數個導電凸塊與該線路重分佈 傳輸載板電性連接。577153 VI. Scope of patent application A plurality of conductive elements are formed on the pad. 19. The cavity-down type multi-chip package structure according to item 18 of the patent application scope, wherein the conductive elements are solder balls. 20. The cavity-down type multi-chip package structure according to item 4 of the patent application scope, wherein the semiconductor wafers are electrically connected to the circuit redistribution transmission carrier board by a plurality of conductive bumps. 第17頁Page 17
TW091138170A 2002-12-31 2002-12-31 Cavity-down MCM package TW577153B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW091138170A TW577153B (en) 2002-12-31 2002-12-31 Cavity-down MCM package
US10/747,191 US20040150099A1 (en) 2002-12-31 2003-12-30 Cavity down MCM package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW091138170A TW577153B (en) 2002-12-31 2002-12-31 Cavity-down MCM package

Publications (2)

Publication Number Publication Date
TW577153B true TW577153B (en) 2004-02-21
TW200411850A TW200411850A (en) 2004-07-01

Family

ID=32769101

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091138170A TW577153B (en) 2002-12-31 2002-12-31 Cavity-down MCM package

Country Status (2)

Country Link
US (1) US20040150099A1 (en)
TW (1) TW577153B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7446409B2 (en) 2004-10-21 2008-11-04 Advanced Semiconductor Engineering, Inc. Cavity-down multiple-chip package
US8426958B2 (en) 2005-05-03 2013-04-23 Megica Corporation Stacked chip package with redistribution lines

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004235324A (en) * 2003-01-29 2004-08-19 Mitsubishi Electric Corp Surface-mounting optical component
US7266296B2 (en) * 2003-06-11 2007-09-04 Intel Corporation Architecture and method for framing control and data bursts over 10 Gbit Ethernet with and without WAN interface sublayer support
US9293350B2 (en) * 2008-10-28 2016-03-22 Stats Chippac Ltd. Semiconductor package system with cavity substrate and manufacturing method therefor
US8604602B2 (en) * 2009-05-15 2013-12-10 Stats Chippac Ltd. Integrated circuit packaging system with reinforced encapsulant having embedded interconnect and method of manufacture thereof
CN102623416B (en) * 2012-04-24 2015-09-02 苏州远创达科技有限公司 A kind of power device of radio frequency power amplification modules is without encapsulating structure and assemble method thereof
US9941242B2 (en) 2012-04-24 2018-04-10 Innogration (Suzhou) Co., Ltd. Unpacked structure for power device of radio frequency power amplification module and assembly method therefor
DE102015104956A1 (en) * 2015-03-31 2016-10-06 Infineon Technologies Ag Printed circuit board with a lead frame with inserted packaged semiconductor chips

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
JPH0548000A (en) * 1991-08-13 1993-02-26 Fujitsu Ltd Semiconductor device
JP2642548B2 (en) * 1991-09-26 1997-08-20 株式会社東芝 Semiconductor device and manufacturing method thereof
US5880403A (en) * 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
JP3110922B2 (en) * 1993-08-12 2000-11-20 富士通株式会社 Multi-chip module
US5886408A (en) * 1994-09-08 1999-03-23 Fujitsu Limited Multi-chip semiconductor device
TW373308B (en) * 1995-02-24 1999-11-01 Agere Systems Inc Thin packaging of multi-chip modules with enhanced thermal/power management
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
US5847929A (en) * 1996-06-28 1998-12-08 International Business Machines Corporation Attaching heat sinks directly to flip chips and ceramic chip carriers
DE19632200C2 (en) * 1996-08-09 2002-09-05 Bosch Gmbh Robert Multichip module
US5942795A (en) * 1997-07-03 1999-08-24 National Semiconductor Corporation Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly
JP4529262B2 (en) * 2000-09-14 2010-08-25 ソニー株式会社 High frequency module device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7446409B2 (en) 2004-10-21 2008-11-04 Advanced Semiconductor Engineering, Inc. Cavity-down multiple-chip package
US8426958B2 (en) 2005-05-03 2013-04-23 Megica Corporation Stacked chip package with redistribution lines

Also Published As

Publication number Publication date
US20040150099A1 (en) 2004-08-05
TW200411850A (en) 2004-07-01

Similar Documents

Publication Publication Date Title
TWI773404B (en) Semiconductor package
US11515290B2 (en) Semiconductor package
US8338935B2 (en) Thermally enhanced electronic package utilizing carbon nanocapsules and method of manufacturing the same
TWI225299B (en) Stacked flip chip package
TWI393228B (en) Flip chip and wire bond semiconductor package
TWI671861B (en) Semiconductor package structure and method of making the same
TW200950041A (en) Flip-chip package and semiconductor chip packages
US20240096719A1 (en) Semiconductor device and method of manufacturing the same
TWI733569B (en) Electronic package and manufacturing method thereof
TW200527557A (en) Semiconductor package and method for manufacturing the same
TW577153B (en) Cavity-down MCM package
US20070054439A1 (en) Multi-chip stack structure
TW578282B (en) Thermal- enhance MCM package
TWI733142B (en) Electronic package
TWI706523B (en) Electronic package
TWI282159B (en) Thermally enhanced thin flip-chip package
TWI624016B (en) Electronic package and the manufacture thereof
TWI765601B (en) Semiconductor device and method of manufacture
US11742323B2 (en) Semiconductor structure and method of forming the same
US20220392861A1 (en) Electronic package and carrier thereof and method for manufacturing the same
TW200839984A (en) Multi-chip semiconductor package structure
TW201810458A (en) Package substrate and the manufacture thereof
TWI837021B (en) Electronic package
US20240290701A1 (en) Electronic package and manufacturing method thereof
TWI848629B (en) Electronic package and manufacturing method thereof

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent