1282159 九、發明說明： 【發明所屬之技術領域】 本發明係有關於兼顧薄化與散熱性之半導體封裝技 術，特別係有關於一種薄型散熱覆晶封裝構造。 【先前技術】 /肖耗性電子產品在消費大眾對產品外觀及反應時間 要求越來越嚴格的情形下，能達到縮小體積以及縮短反應 時間的覆晶接合技術越來越受到重視，且覆晶接合方法另 具有咼腳數之優點，故覆晶接合技術目前已廣泛的運用在 封裝7員域^中’然而晶片具有南腳數且運作速度加快時， 散熱需求便相對增加，通常會在晶片背面貼附散熱片以提 南散熱效果，如第丨圖所示，習知薄型散熱覆晶封裝構造 1 00係包含一可撓性基板i丨〇、一凸塊化晶片丨2〇以及一 如底部填充膠之封膠體1 3 0。該基板11 〇之一上表面1 i i 係具有一線路層112以及一覆蓋層113，該覆蓋層113係 形成於該線路層112之上且露出複數個接點114，該些接 點114係為連接墊。該晶片1 2〇係設於該基板丨丨〇上方， 該晶片120係具有一主動面m及一背面122，該主動面 1 21係設置有複數個凸塊123，該些凸塊丨23係用以接合 至該些接點114，以完成該基板11〇與該晶片120之電性 連接’該薄型散熱覆晶封裝構造1〇〇上係可再設置一散熱 片140 ’其係貼附於該晶片120之該背面122，該散熱片 140係藉由一導熱膠15〇貼附於該晶片12〇。該封膠體iS〇 係形成於該基板11 〇與該晶片120之間，以覆蓋並固定該 5 •1282159 些凸塊123。該散熱#14〇裝設於該晶片i2〇之該背面m ’ @然可以增加散熱速度’但該薄型散熱覆晶封裝構造100 - 之整體厚度則會增加，且該晶片12〇之發熱源係來自該主 動面121處的積體電路元件，該散熱片140係熱耦合至該 晶片120之該背面122，其導熱路徑較遠，散熱較差。 【發明内容】 本發明之主要目的係在於提供一種薄型散熱覆晶封 • 裝構造，一基板係具有一絕緣層以及一金屬層，該絕緣層 係具有一穿孔，以顯露該金屬層之一導熱區塊，一晶片之 複數個凸塊係電性連接至該金屬層之複數個線路，一封膠 體係形成於該基板與該晶片之間而不填入至該穿孔，該穿 孔能使熱直接散出，可提高該晶片之散熱效率也可減少散 熱片之設置厚度。 本發明之次一目的係在於提供一種薄型散熱覆晶封 裝構ie ’ 3亥導熱區塊係稱大於該穿孔且完全覆蓋該穿孔， Φ 以利該封膠體形成於該晶片與該基板之間，避免該封膠體 污染該絕緣層。 依據本發明，一種薄型散熱覆晶封裝構造主要包含一 基板、一晶片以及一封膠體。該基板係具有一絕緣層以及 一金屬層，該金屬層係形成於談絕緣層之一上表面並包含 有複數個線路以及一導熱區塊，該絕緣層係具有一穿孔， 以顯露該導熱區塊，該晶片係設於該基板上方並具有複數 個凸塊，以電性連接至該些線路，該封膠體係形成於該基 板與該晶片之間而不填入至該穿孔。 6 1282159 【實施方式】 本發明之一具體實施例係揭示一種薄型散熱覆晶封 裝構造200。請參閱第2圖，該薄型散熱覆晶封裝構造200 係主要包含一基板210、一晶片220以及一封膠體230。 該基板係具有一絕緣層211以及一金屬層212，該基板2 10 係可選自薄膜覆晶封裝（COF package)之可撓性基板，該金 屬層212係形成於該絕緣層211之一上表面213，該金屬 層212係可為一圖案化銅層’其係包含有複數個線路214 以及一導熱區塊215, 一覆蓋層217係形成於該些線路214 上’並於該覆蓋層2 1 7顯露複數個線路開口 2 1 8，用以外 接電路。該絕緣層211係具有一穿孔2 1 6，以顯露該導熱 區塊2 1 5，較佳地，該導熱區塊21 5係稍大於該穿孔216 以使該導熱區塊215完全覆蓋該穿孔216。而該封膠體23 0 係可為一底部填充膠，該封膠體230係形成於該晶片220 與該基板210之該金屬層212之間（如第3圖所示）而不 填入至該穿孔216，避免該封膠體230流佈至該基板210 之該絕緣層211而污染該絕緣層211。 該晶片220係設於該基板210上方，該晶片220之一 主動面221係具有複數個凸塊222，該些凸塊222之材質 係包含金或锡船，可利用熱壓合或回銲之方式使該些凸塊 222電性連接至該金屬層212之該些線路214。較佳地， 該晶片220另具有至少一導熱凸塊223，其係接合至該導 熱區塊215，以增加該晶片220之散熱速度。此外，該薄 型散熱覆晶封裝構造200另包含有一散熱片240，其係貼 7 1282159 設於該基板210之下方，該散熱片24〇係具有一凸部241， ’ 該凸部241係容置於該穿孔216内，以熱_合至該導熱區 鬼215其中該政熱片240之尺寸係可略大於該晶片22〇 之尺寸，由於該散熱片24〇之部分係容置於該基板21〇之 該牙孔2 1 6内，可有效縮小該薄型散熱覆晶封裝構造 之體積’同時具有提高散熱之效果。 請參閱第4圖，本發明係揭示另一種薄型散熱覆晶封 # 裝構造300，該薄型散熱覆晶封裴構造300係包含一基板 310、一晶片320及一封膠體33〇。該基板31〇係具有一絕 緣層311以及一金屬層312，該基板31〇係可選自薄膜覆 晶封裝（COF package)之可撓性基板，該金屬層3丨2係形成 於該絕緣層311之一上表面313並包含有複數個線路314 以及一導熱區塊315, 一覆蓋層317係形成於該些線路314 上並顯露複數個線路開口 3丨8，以外接電路。該絕緣層3 i i 之一穿孔3 16係用以顯露該導熱區塊3丨5，該導熱區塊3工5 • 係稍大於該穿孔3 1 6且該導熱區塊3 1 5係完全覆蓋該穿孔 316，可將該封膠體33〇固定於該晶片32〇與該基板 之間而不填入至該絕緣層3丨丨之該穿孔3丨6，在本實施例 中，該封膠體330係可為一底部填充膠。該晶片32〇係設 於該基板310上方並具有複數個凸塊322，該些凸塊322 係設置於該晶片320之一主動面321上，以電性連接至該 些線路3 14，較佳地，該晶片320另具有至少一導熱凸塊 323,其係接合至該導熱區塊315，藉由該導熱凸塊323接 合至該導熱區塊315，使熱由該穿孔316直接散出，省略 1282159 散熱片之設置，既可提高該晶片320之散熱效率同時具有 降低生產成本之功效。 ^ 附之申請專利範圍所界定 在不脫離本發明之精神和 〆 ’均屬於本發明之保護範 本發明之保護範圍當視後 者為準，任何熟知此項技藝者， 範圍内所作之任何變化與修改 圍。 【圖式簡單說明】1282159 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor packaging technology that combines thinning and heat dissipation, and more particularly relates to a thin heat-dissipation flip-chip package structure. [Prior Art] /Shaw-consuming electronic products have become more and more important, and flip-chip bonding technology, which can reduce the volume and shorten the reaction time, when the consumer demand for product appearance and reaction time becomes more and more strict. The bonding method has the advantage of the number of pins, so the flip chip bonding technology has been widely used in the package 7-member domain. However, when the chip has a south leg number and the operation speed is increased, the heat dissipation requirement is relatively increased, usually in the wafer. The heat sink is attached to the back side to improve the heat dissipation effect of the south. As shown in the figure, the conventional thin heat-dissipation flip-chip package structure 100 includes a flexible substrate, a bumped wafer, and the like. The underfill rubber sealant 1 30. The upper surface 1 ii of the substrate 11 has a circuit layer 112 and a cover layer 113. The cover layer 113 is formed on the circuit layer 112 and exposes a plurality of contacts 114. The contacts 114 are Connection pad. The wafer 120 is disposed above the substrate, and the wafer 120 has an active surface m and a back surface 122. The active surface 21 is provided with a plurality of bumps 123, and the bumps 23 are For bonding to the contacts 114 to complete the electrical connection between the substrate 11 and the wafer 120. The thin heat-dissipation flip-chip package structure 1 can be further provided with a heat sink 140. The back surface 122 of the wafer 120 is attached to the wafer 12 by a thermal conductive adhesive 15 . The encapsulant iS is formed between the substrate 11 〇 and the wafer 120 to cover and fix the 5•1282159 bumps 123. The heat dissipation #14 is mounted on the back surface of the wafer i2, but the heat dissipation speed can be increased. However, the overall thickness of the thin heat-dissipation package 100- is increased, and the heat source of the wafer 12 is increased. From the integrated circuit component at the active surface 121, the heat sink 140 is thermally coupled to the back surface 122 of the wafer 120, and has a long heat conduction path and poor heat dissipation. SUMMARY OF THE INVENTION The main object of the present invention is to provide a thin heat-dissipation flip-chip package structure, a substrate has an insulating layer and a metal layer, the insulating layer has a through hole to reveal a heat conduction of the metal layer a plurality of bumps of a wafer electrically connected to the plurality of lines of the metal layer, and an adhesive system is formed between the substrate and the wafer without filling the through hole, the through hole enabling direct heat Dissipating can improve the heat dissipation efficiency of the wafer and also reduce the thickness of the heat sink. A second object of the present invention is to provide a thin heat-dissipation flip-chip package structure, which is said to be larger than the perforation and completely cover the perforation, so that the encapsulant is formed between the wafer and the substrate. The sealant is prevented from contaminating the insulating layer. According to the present invention, a thin heat-dissipation flip chip package structure mainly comprises a substrate, a wafer and a gel. The substrate has an insulating layer and a metal layer formed on an upper surface of the insulating layer and includes a plurality of lines and a heat conducting block, the insulating layer having a through hole to expose the heat conducting region And the chip is disposed above the substrate and has a plurality of bumps electrically connected to the wires, and the encapsulation system is formed between the substrate and the wafer without filling the through holes. 6 1282159 [Embodiment] One embodiment of the present invention discloses a thin heat sinking flip chip package structure 200. Referring to FIG. 2 , the thin heat-dissipation package structure 200 mainly includes a substrate 210 , a wafer 220 , and a gel 230 . The substrate has an insulating layer 211 and a metal layer 212. The substrate 2 10 is selected from a flexible substrate of a COF package, and the metal layer 212 is formed on one of the insulating layers 211. The surface 213, the metal layer 212 can be a patterned copper layer comprising a plurality of lines 214 and a heat conducting block 215, and a cover layer 217 is formed on the lines 214 and on the cover layer 2 1 7 reveals a plurality of line openings 2 1 8, using an external circuit. The insulating layer 211 has a through hole 216 to expose the heat conducting block 2 15 . Preferably, the heat conducting block 21 5 is slightly larger than the through hole 216 to completely cover the through hole 216 . . The encapsulant 230 can be an underfill, and the encapsulant 230 is formed between the wafer 220 and the metal layer 212 of the substrate 210 (as shown in FIG. 3) without filling the perforation. 216. The encapsulant 230 is prevented from flowing to the insulating layer 211 of the substrate 210 to contaminate the insulating layer 211. The wafer 220 is disposed on the substrate 210. The active surface 221 of the wafer 220 has a plurality of bumps 222. The bumps 222 are made of gold or tin boats and can be hot pressed or reflowed. The bumps 222 are electrically connected to the lines 214 of the metal layer 212. Preferably, the wafer 220 further has at least one heat conducting bump 223 bonded to the heat conducting block 215 to increase the heat dissipation speed of the wafer 220. In addition, the thin heat-dissipation flip-chip package structure 200 further includes a heat sink 240, and the tie 7 1282159 is disposed under the substrate 210. The heat sink 24 has a convex portion 241, and the convex portion 241 is received. In the through hole 216, the heat transfer zone 215 is sized to be slightly larger than the size of the wafer 22, since a portion of the heat sink 24 is placed on the substrate 21 In the tooth hole 2 16 , the volume of the thin heat-dissipating and flip-chip package structure can be effectively reduced, and the heat dissipation effect is improved. Referring to FIG. 4, the present invention discloses another thin heat-dissipation flip-chip structure 300 comprising a substrate 310, a wafer 320 and a colloid 33. The substrate 31 has an insulating layer 311 and a metal layer 312. The substrate 31 can be selected from a flexible substrate of a COF package, and the metal layer 3 is formed on the insulating layer. The upper surface 313 of the 311 includes a plurality of lines 314 and a heat conducting block 315. A cover layer 317 is formed on the lines 314 and exposes a plurality of line openings 3丨8, and is connected to the circuit. One of the insulating layers 3 ii is formed to expose the heat conducting block 3丨5, the heat conducting block 3 is slightly larger than the through hole 3 16 and the heat conducting block 3 1 5 is completely covered. The perforation 316 can fix the encapsulant 33〇 between the wafer 32〇 and the substrate without filling the perforation 3丨6 of the insulating layer 3,. In the embodiment, the encapsulant 330 is Can be an underfill. The chip 32 is disposed on the substrate 310 and has a plurality of bumps 322. The bumps 322 are disposed on one of the active faces 321 of the die 320 to electrically connect to the wires 3 and 14 . The wafer 320 further has at least one heat conducting bump 323 coupled to the heat conducting block 315. The heat conducting bump 323 is bonded to the heat conducting block 315, so that heat is directly discharged from the through hole 316, and is omitted. The 1282159 heat sink is provided to improve the heat dissipation efficiency of the wafer 320 while reducing the production cost. The scope of the invention is defined by the scope of the invention and the scope of the invention is intended to be included in the scope of the invention. Wai. [Simple description of the map]
之截面示意圖。 ’一種薄型散熱覆晶 ’該薄型散熱覆晶封 〇 ’另一種薄型散熱覆 第1圖··習知薄型散熱覆晶封裝構造 第2圖··依據本發明之一具體實施例 封裝構造之截面示意圖。 第3圖：依據本發明之_具體實施例 裝構造點膠時之截面示惫圖 第4圖：依據本發明之-具體實：例 晶封裝構造之截面示意圖。 【主要元件符號說明】 10 點膠器 100 薄型散熱覆晶 封裳構造 110 基板 111 上表面 113 覆蓋層 114 接點 120 晶片 121 主動面 123 凸塊 130 封膠體 140 散熱片 200 薄型散熱覆晶 封裝構造 210 基板 211 絕緣層 112線路層 122背面 15〇導熱膠 212金屬層 9 1282159 213 上表面 214線路 215 216 穿孔 217覆蓋層 218 220 晶片 221主動面 222 223 導熱凸塊 230 封膠體 240散熱片 241 300 薄型散熱覆晶封裝構造 310 基板 311絕緣層 312 313 上表面 314線路 315 316 穿孔 317覆蓋層 318 320 晶片 321主動面 322 323 導熱凸塊 330 封膠體 導熱區塊 開口 凸塊 凸部 金屬層 導熱區塊 開口 凸塊A schematic cross section. 'A thin heat-dissipating flip-chip', the thin heat-dissipating chip-sealing package' is another thin-type heat-dissipating cover. FIG. 1 is a thin-type heat-dissipating flip-chip package structure. FIG. 2 is a cross-sectional view of a package structure according to an embodiment of the present invention. schematic diagram. Fig. 3 is a cross-sectional view showing the structure of the dispensing according to the present invention. Fig. 4 is a cross-sectional view showing the structure of the crystal package according to the present invention. [Main component symbol description] 10 Dispenser 100 Thin heat-dissipation crystal-seal structure 110 Substrate 111 Upper surface 113 Cover layer 114 Contact 120 Wafer 121 Active surface 123 Bump 130 Sealant 140 Heat sink 200 Thin heat-dissipation flip-chip package structure 210 substrate 211 insulating layer 112 circuit layer 122 back surface 15 〇 thermal conductive paste 212 metal layer 9 1282159 213 upper surface 214 line 215 216 perforation 217 cover layer 218 220 wafer 221 active surface 222 223 thermal conductive bump 230 encapsulant 240 heat sink 241 300 thin Heat-dissipation package structure 310 substrate 311 insulation layer 312 313 upper surface 314 line 315 316 perforation 317 cover layer 318 320 wafer 321 active surface 322 323 thermal conductive bump 330 sealant thermal block open bump convex metal layer thermal block opening Bump
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