TW200725841A - Thermally enhanced thin flip-chip package - Google Patents

Thermally enhanced thin flip-chip package

Info

Publication number
TW200725841A
TW200725841A TW094145285A TW94145285A TW200725841A TW 200725841 A TW200725841 A TW 200725841A TW 094145285 A TW094145285 A TW 094145285A TW 94145285 A TW94145285 A TW 94145285A TW 200725841 A TW200725841 A TW 200725841A
Authority
TW
Taiwan
Prior art keywords
chip
substrate
heat
chip package
thermally enhanced
Prior art date
Application number
TW094145285A
Other languages
Chinese (zh)
Other versions
TWI282159B (en
Inventor
Yeh-Shun Chen
Hou-Chang Kuo
Hsuan-Jui Chang
Hung-Pin Shih
Original Assignee
Int Semiconductor Tech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Semiconductor Tech Ltd filed Critical Int Semiconductor Tech Ltd
Priority to TW94145285A priority Critical patent/TWI282159B/en
Application granted granted Critical
Publication of TWI282159B publication Critical patent/TWI282159B/en
Publication of TW200725841A publication Critical patent/TW200725841A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A thermally enhanced thin flip-chip package mainly includes a substrate, a chip and an encapsulant. A metal layer of the substrate is formed on an insulating layer of the substrate and includes a plurality of circuits and a heat conductive region. The insulating layer has a through hole exposing the heat conductive region, a plurality of bumps of the chip electrically connect to the circuits. The encapsulant is formed between the substrate and the chip but not flow in the through hole. Accordingly, the through hole offers a heat-conductive path for increasing the heat dissipation of the chip and reducing an installing thickness of a heat spreader.
TW94145285A 2005-12-20 2005-12-20 Thermally enhanced thin flip-chip package TWI282159B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94145285A TWI282159B (en) 2005-12-20 2005-12-20 Thermally enhanced thin flip-chip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94145285A TWI282159B (en) 2005-12-20 2005-12-20 Thermally enhanced thin flip-chip package

Publications (2)

Publication Number Publication Date
TWI282159B TWI282159B (en) 2007-06-01
TW200725841A true TW200725841A (en) 2007-07-01

Family

ID=38777625

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94145285A TWI282159B (en) 2005-12-20 2005-12-20 Thermally enhanced thin flip-chip package

Country Status (1)

Country Link
TW (1) TWI282159B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777542B (en) * 2009-01-14 2011-08-17 南茂科技股份有限公司 Chip packaging structure and packaging method
US9524946B2 (en) 2013-08-23 2016-12-20 Murata Manufacturing Co., Ltd. Electronic device
CN108735691A (en) * 2018-06-11 2018-11-02 山东超越数控电子股份有限公司 A kind of heat dissipating method and device of portable computer high power chip bga

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111624796A (en) * 2020-07-17 2020-09-04 厦门通富微电子有限公司 Chip on film and display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777542B (en) * 2009-01-14 2011-08-17 南茂科技股份有限公司 Chip packaging structure and packaging method
US9524946B2 (en) 2013-08-23 2016-12-20 Murata Manufacturing Co., Ltd. Electronic device
CN108735691A (en) * 2018-06-11 2018-11-02 山东超越数控电子股份有限公司 A kind of heat dissipating method and device of portable computer high power chip bga

Also Published As

Publication number Publication date
TWI282159B (en) 2007-06-01

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