TW200816422A - Heating dissipating chip on film package - Google Patents

Heating dissipating chip on film package Download PDF

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Publication number
TW200816422A
TW200816422A TW095134655A TW95134655A TW200816422A TW 200816422 A TW200816422 A TW 200816422A TW 095134655 A TW095134655 A TW 095134655A TW 95134655 A TW95134655 A TW 95134655A TW 200816422 A TW200816422 A TW 200816422A
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TW
Taiwan
Prior art keywords
heat
wafer
chip package
package structure
film flip
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Application number
TW095134655A
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Chinese (zh)
Inventor
Yeh-Shun Chen
Hou-Chang Kuo
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Int Semiconductor Tech Ltd
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Application filed by Int Semiconductor Tech Ltd filed Critical Int Semiconductor Tech Ltd
Priority to TW095134655A priority Critical patent/TW200816422A/en
Publication of TW200816422A publication Critical patent/TW200816422A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

A heat dissipating chip on film package mainly includes a flexible substrate, a chip, a thermal conductive material and an encapsulant. The flexible substrate has an insulating layer and a metal layer, the metal layer is formed on an upper surface of the insulating layer. A plurality of bumps of the chip electrically connect to a plurality of contacts of the metal layer, the thermal conductive material is filled in a through hole of insulating layer, the encapsulant is formed between the flexible substrate and the chip, and the heat of the chip is transmitted by the he thermal conductive material, it can thin and enhance the heat dissipation.

Description

200816422 九、發明說明： 【發明所屬之技術領域】 本發明係有關於散熱型薄膜覆晶封裝構造，特別係有 關於一種具有薄化、增加散熱及增強結構強度之薄膜覆晶 封裝構造。 【先别技術】 採用覆晶封裝技術可減低訊號的電感效應，且覆晶封 裝技術對於基板與晶片之間有較短的連接距離以及穩定 的电丨生’使其可以應用到較面頻的頻段，符合未來高效能 和攜帶式產品所需之構裝技術，然而由於覆晶封裝技術具 有上述之優點，因此晶片内之積體電路元件相對較多，在 運算時所產生之熱能也相當高，故封裝結構之散熱非常重 要0BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat-dissipating film flip chip package structure, and more particularly to a film flip chip package structure having thinning, increased heat dissipation, and enhanced structural strength. [Technology] The flip chip packaging technology can reduce the inductance effect of the signal, and the flip chip packaging technology has a short connection distance between the substrate and the wafer and a stable electric power generation, so that it can be applied to the surface frequency. The frequency band meets the packaging technology required for future high-performance and portable products. However, since the flip chip packaging technology has the above advantages, the integrated circuit components in the wafer are relatively large, and the heat energy generated during the operation is also relatively high. Therefore, the heat dissipation of the package structure is very important.

如第1圖所示’習知薄膜覆晶封裝構造1 〇〇係包含一 基板11 0、一凸塊化晶片丨20、一底部填充膠丨3 〇以及一 散熱片140。該基板110之一上表面lu係具有一線路層 112以及一覆蓋層113,該覆蓋層113係形成於該線路層 112之上並顯露複數個凸塊接點114。該凸塊化晶片12〇 係設於該基板110上方，該凸塊化晶片12〇係具有一主動 面121、一背面122以及複數個凸塊123，該些凸塊123 係接合至該些凸塊接點114’以使該基板m與該凸塊化 晶片120之電性連接，該散熱片14〇係藉由一黏膠15〇貼 附於該凸塊化晶片120之該背面122。該底部填充膠13〇 係形成於該基板110與該凸塊化晶片12〇之間，以覆蓋並 200816422 固定該些凸塊123。由於該散熱片14〇係裳設於該凸塊化 晶片120之該背面122， 100之整體厚度。此外， 因此亦增加該散熱覆晶封裝構造 為增加散熱效果，通常會增大該 散熱片140之尺寸，使得該散熱片14〇之散熱面積大於該 凸塊化…20之該背面122 ’然而該散熱片14〇貼附至 該凸塊化晶片.12G之該背面122 _，因壓力不均而使該散 熱片140傾斜貼附在該凸塊化晶片12〇之該背面或As shown in Fig. 1, the conventional thin film flip chip package structure 1 includes a substrate 110, a bumped wafer cassette 20, an underfill film 3, and a heat sink 140. One of the upper surfaces of the substrate 110 has a wiring layer 112 and a cover layer 113. The cladding layer 113 is formed on the wiring layer 112 and exposes a plurality of bump contacts 114. The bumped wafer 12 is mounted on the substrate 110. The bumped wafer 12 has an active surface 121, a back surface 122, and a plurality of bumps 123. The bumps 123 are bonded to the bumps. The bumps 114 ′ are electrically connected to the bumps 120 , and the fins 14 are attached to the back surface 122 of the bump wafers 120 by an adhesive 15 . The underfill 13 is formed between the substrate 110 and the bumped wafer 12A to cover and fix the bumps 123 by 200816422. Since the heat sink 14 is disposed on the entire thickness of the back surface 122, 100 of the bump wafer 120. In addition, the heat-dissipation flip chip package structure is also increased to increase the heat dissipation effect, and the heat sink 140 is generally increased in size such that the heat dissipation area of the heat sink 14 is greater than the back surface 122 of the bumps 20 . The heat sink 14 is attached to the back surface 122 of the bumped wafer .12G, and the heat sink 140 is obliquely attached to the back surface of the bumped wafer 12 due to uneven pressure or

者，因該散熱片140傾斜而觸壓該凸塊化晶片12〇之該背 面122，造成該凸塊化晶片12〇崩裂損壞；再者，由於該 基板1.1。係為薄膜且為可撓性，當該基板11〇彎折結合於 其他電子元件時，係會造成該些凸塊123脫離該些凸塊接 點 11 4。 【發明内容】 、本么明之主要目的係在於提供一種散熱型薄膜覆晶 封裝構造，一可撓性基板係具有一絕緣層以及一金屬層， 該絕緣層係、具有一穿，該金屬I係形成於該絕緣層：一 上表面並包含有複數個接點，一晶.片係設於該可撓性基板 方且該晶片之複數個凸塊係電性連接至該些接點，一導 …、材係填充於該絕緣層之該穿孔，以傳導該晶片所產生之 熱能進而增加散熱效率。 、本赉月之次一目的係在於提供一種散熱型薄膜覆晶 封衣構造，一散熱片係貼設於該可撓性基板之下方，並接 觸，導熱材’以增加該薄膜覆晶封裝構造之散熱效率；且 該散熱片係可增加該可撓性基板之機械強度，以避免該可 200816422 撓性基板彎折結合於其他電子元件時造成該些凸塊脫離 . 該些接點；此外，可避免該散熱片觸壓該晶片，而造成該 晶片崩裂損壞。 依據本發明，一種散熱型薄膜覆晶封裝.構造主要包含 一可撓性基板、一晶片、一導熱材以及一封膠體。該可撓 性基板係具有一絕緣層以及一金屬層，該絕緣層係具有一 穿孔，該金屬層係形成於該絕緣層之一上表面並包含有複 _ 數個接點，該晶片係設於該可撓性基板上方並具有一主動 面以及複數個凸塊，該些凸塊係電性連接至該些接點，該 導熱材係填充於該絕緣層之該穿孔，以傳導該晶片所產生 之熱能’該封膠體係形成於該可撓性基板與該晶片之間。 【實施方式】 依據本發明之笫一具體實施例，請參閱第2圖，其係 揭示一種散熱型薄膜覆晶封裝構造200。該散熱型薄膜覆 晶封裝構造200係至少包含一可撓性基板21〇、一晶片 _ 22〇、一導熱材23〇以及一封膠體24〇。該可撓性基板21〇 係為薄膜覆晶封裝（COF package)之可撓性基板，其係具有 一絕緣層211以及一金屬層212，該絕緣層211係具有一 牙孔213，該金屬層212係形成於該絕緣層211之一上表 面214且該金屬層2 12係為一圖案化之鋼線路層，在本實 施例中，该金屬層212係包含有複數個接點2 1 5、一導熱 區塊216及複數個外接墊218,該絕緣層2Π之該穿孔213 係顯露該導熱區塊216，其中該導熱區塊216係可稍大於 該穿孔2 13且該導熱區塊21 6係完全覆蓋該穿孔213。此 200816422 外，一覆蓋層217係形成於該金屬層212上並顯露出該些 接點2 1 5與該些外接墊2 1 8。該晶片220係設於該可撓性 基板210上方並具有一主動面221以及複數個凸塊222， 该些凸塊222之材質係包含金或錫錯，可利用熱麼合或回 銲之方式使該些凸塊222電性連接至該金屬層212之該些 接點21 5，在本實施例中，該晶片220係另具有至少一導 熱凸塊223，其係接合至該導熱區塊216。該導熱材23〇 • 係填充於該絕緣層211之該穿孔213並與.該導熱區塊216 接觸，以傳導該晶片220所產生之熱能，增加該晶片22〇 之散熱速度，該導熱材23 0係可選自於導熱膠或導熱膏。 該封膠體240係形成於該可撓性基板21〇與該晶片22〇之 間而不填入至该穿孔21 3以保護該些凸塊222以及該導熱 凸塊223，其中該封膠體24〇係為底部填充膠，由於該導 熱材230係為導熱而不導電之材質，因此該晶片22〇所產 生之熱能可藉由該導熱材23〇導出達到散熱之功效，此 外，該散熱型薄膜覆晶封裝構造2〇〇係另包含有一散熱片 〇名政熱片250係貼設於該可撓性基板2 1 0之下方， 並且忒政熱片250係接觸該導熱材23〇，該散熱片25〇之 ^寸係可大於該晶片220之尺寸，藉由該導熱材230將該 曰曰片220之熱能傳導至該散熱片250，以增加該晶片22〇 .政”、、速度，並且由於該散熱片25〇係貼設於該可撓性基 =210之下方，因此可增加該可撓性基板21〇之機械強 =，以避免該可撓性基板21〇彎折結合於其他電子元件 時，造成該些凸塊222脫離該些接點215;此外，可避免 8 200816422 該散熱片250觸壓該晶片2,20，而造成該晶片220崩裂損 壞。 請參閱第3圖，在另一實施例中，一種散熱型薄膜覆 晶封裝構造300係主要包含一可撓性基板3 1 0、一晶片 320、一導熱材330以及一封膠體34〇。該可撓性基板3 1〇 係為薄膜覆晶封裝（COF package)之可撓性基板，其係具有 一絕緣層3 11以及一金屬層3 12，該絕緣層3 11係具有一The bump 122 is pressed against the back surface 122 of the bumped wafer 12, causing the bumped wafer 12 to collapse and damage; further, due to the substrate 1.1. It is a film and is flexible. When the substrate 11 is bent and bonded to other electronic components, the bumps 123 are separated from the bump contacts 11 4 . SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a heat dissipating film flip chip package structure, a flexible substrate having an insulating layer and a metal layer, the insulating layer having a wear, the metal I system Formed on the insulating layer: an upper surface and including a plurality of contacts, a crystal is disposed on the flexible substrate side and a plurality of bumps of the wafer are electrically connected to the contacts, The material is filled in the perforation of the insulating layer to conduct heat generated by the wafer to further increase heat dissipation efficiency. The second objective of the present invention is to provide a heat-dissipating film flip-chip sealing structure, a heat sink is attached under the flexible substrate, and is in contact with the heat-conducting material to increase the film-wrapped package structure. The heat dissipation efficiency of the flexible substrate can be increased to prevent the bumps from being detached when the 200816422 flexible substrate is bent and bonded to other electronic components. The heat sink can be prevented from touching the wafer, causing the wafer to be cracked and damaged. According to the present invention, a heat dissipating film flip chip package is constructed. The structure mainly comprises a flexible substrate, a wafer, a heat conducting material and a gel. The flexible substrate has an insulating layer and a metal layer. The insulating layer has a through hole. The metal layer is formed on one surface of the insulating layer and includes a plurality of contacts. The chip is provided. An active surface and a plurality of bumps are disposed on the flexible substrate, the bumps are electrically connected to the contacts, and the heat conductive material is filled in the through hole of the insulating layer to conduct the wafer The generated thermal energy 'the sealant system is formed between the flexible substrate and the wafer. [Embodiment] In accordance with a specific embodiment of the present invention, reference is made to Fig. 2, which discloses a heat dissipating film flip chip package structure 200. The heat-dissipating film-coated package structure 200 includes at least a flexible substrate 21, a wafer 22, a heat-conducting material 23, and a gel 24 〇. The flexible substrate 21 is a flexible substrate of a COF package, and has an insulating layer 211 and a metal layer 212. The insulating layer 211 has an indentation 213. The 212 is formed on the upper surface 214 of the insulating layer 211 and the metal layer 2 12 is a patterned steel circuit layer. In this embodiment, the metal layer 212 includes a plurality of contacts 2 15 . a heat conducting block 216 and a plurality of outer pads 218, the through hole 213 of the insulating layer 2 is exposed to the heat conducting block 216, wherein the heat conducting block 216 is slightly larger than the through hole 2 13 and the heat conducting block 21 6 The perforations 213 are completely covered. In addition to the 200816422, a cover layer 217 is formed on the metal layer 212 and exposes the contacts 2 15 and the external pads 2 18 . The wafer 220 is disposed above the flexible substrate 210 and has an active surface 221 and a plurality of bumps 222. The bumps 222 are made of gold or tin, and can be thermally or reflowed. The bumps 222 are electrically connected to the contacts 21 5 of the metal layer 212. In the embodiment, the wafer 220 has at least one heat conducting bump 223 coupled to the heat conducting block 216. . The heat conducting material 23 is filled in the through hole 213 of the insulating layer 211 and is in contact with the heat conducting block 216 to conduct heat generated by the wafer 220 to increase the heat dissipation rate of the wafer 22, and the heat conducting material 23 The 0 series may be selected from a thermal conductive paste or a thermal conductive paste. The encapsulant 240 is formed between the flexible substrate 21 and the wafer 22 without filling the through holes 21 3 to protect the bumps 222 and the thermally conductive bumps 223, wherein the encapsulant 24〇 The heat-insulating material 230 is a material that is thermally conductive and non-conductive, so that the heat generated by the wafer 22 can be deducted by the heat-conducting material 23 to achieve heat dissipation. Further, the heat-dissipating film is covered. The crystal package structure 2 further includes a heat sink 250 affixed to the flexible substrate 2 1 0, and the hot foil 250 contacts the heat conductive material 23 〇, the heat sink 25 inches can be larger than the size of the wafer 220, and the heat conductive material 230 conducts the thermal energy of the cymbal 220 to the heat sink 250 to increase the wafer 22, speed, and The heat sink 25 is attached to the flexible base=210, so that the mechanical strength of the flexible substrate 21 can be increased to prevent the flexible substrate 21 from being bent and bonded to other electronic components. When the bumps 222 are separated from the contacts 215; in addition, 8 20 can be avoided 0816422 The heat sink 250 touches the wafer 2, 20, causing the wafer 220 to be cracked and damaged. Referring to FIG. 3, in another embodiment, a heat dissipation type film flip chip package structure 300 mainly includes a flexible portion. a substrate 310, a wafer 320, a heat-conducting material 330, and a gel 34. The flexible substrate 31 is a flexible substrate of a COF package, which has an insulating layer. 3 11 and a metal layer 3 12, the insulating layer 3 11 has one

穿孔3 1 3，該金屬層312係形成於該絕緣層311之一上表 面3 I4且該金屬層312係為一圖案化鋼層，該金屬層312 係包含有複數個接點3 1 5及複數個外接墊3 17。一覆蓋層 3 1 6係形成於該金屬層3丨2上並顯露該些接點3丨5及該些 外接墊317。該晶片320係具有一主動面321以及複數個 凸塊322，該晶片320係設於該可撓性基板31〇上方並以 該些凸塊322電性連接該些接點315，談導熱材33〇係填 充於該絕緣層311之該穿孔313並接觸該晶片32()之該主 動面321該^熱材330係為導熱而不導電之導熱膠或 熱膏。該封膠體34G係為底部填充膠，其係形成於該可 性基板31〇與該晶片32〇之間而不填入至該穿孔313以 護該些凸塊3 2 2，由於該導熱材3 3 Q係填充於該絕緣層3 之該穿孔313並接觸該晶片320之該主動面321，因此 晶片320所產生之熱可藉由該導熱材33()導出散熱。該 熱型溥膜覆晶封裝構造300係另包含有—散熱片州， 散熱片35G係可貼設於該可撓性基板3 1G之下方，今散 片35。之尺寸係大於該晶片32〇之尺寸，藉由該導熱材3: 9 200816422 將該晶片320之熱能傳導至該散熱片35〇，以增加該晶片 320之散熱速度；此外亦可增加該可撓性基板3ι〇之機械 強度以避免該可撓性基板310彎折時，造成該些凸塊322 脫離該些接點315,以及可避免該散熱片35〇觸壓該晶片 320，而造成該晶片32〇崩裂損壞。。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準，任何熟知此項技藝者，在不脫離本發明之精神和a metal layer 312 is formed on the upper surface 3 I4 of the insulating layer 311 and the metal layer 312 is a patterned steel layer. The metal layer 312 includes a plurality of contacts 3 15 and A plurality of external pads 3 17 . A cover layer 3 16 is formed on the metal layer 3丨2 and exposes the contacts 3丨5 and the external pads 317. The wafer 320 has an active surface 321 and a plurality of bumps 322. The wafer 320 is disposed above the flexible substrate 31A and electrically connected to the contacts 315 by the bumps 322. The lanthanum is filled in the perforation 313 of the insulating layer 311 and contacts the active surface 321 of the wafer 32. The thermal material 330 is a thermally conductive non-conductive thermal conductive paste or a thermal paste. The sealant 34G is an underfill, which is formed between the compliant substrate 31 〇 and the wafer 32 而不 without filling the through holes 313 to protect the bumps 32 2 due to the heat conductive material 3 . The Q is filled in the via 313 of the insulating layer 3 and contacts the active surface 321 of the wafer 320. Therefore, the heat generated by the wafer 320 can be dissipated by the heat conducting material 33 (). The thermal enamel flip chip package structure 300 further includes a heat sink state, and the heat sink 35G can be attached to the lower surface of the flexible substrate 3 1G. The size of the wafer is greater than the size of the wafer 32, and the thermal energy of the wafer 320 is transferred to the heat sink 35A by the heat conductive material 3: 9 200816422 to increase the heat dissipation speed of the wafer 320; When the flexible substrate 310 is bent, the bumps 322 are separated from the contacts 315, and the heat sink 35 is prevented from contacting the wafer 320, thereby causing the wafer 32 〇 cracked and damaged. . The scope of the present invention is defined by the scope of the appended claims, and anyone skilled in the art, without departing from the spirit of the invention.

範圍内所作之任何變化與修改，均屬於本發明之保護範 圍。 【圖式簡單說明】 第1圖 第2圖Any changes and modifications made within the scope are within the scope of protection of the present invention. [Simple diagram of the diagram] Figure 1 Figure 2

習知散熱型薄膜覆晶封裝構造之截面示意圖。 依據本發明之第-具體實施例，-種散熱型薄膜 覆晶封装構造之戴面示意圖。 依據本發明之第二具體實施例，另一種散熱型薄 膜覆晶封裝構造之截面示意圖。 【主要元件符號說明】 100 散熱覆晶封裝構造 110 基板 111 上表面 112 線路層 113 覆蓋層 114 凸塊接點 120 晶片 121 主動面 122 背面 123 凸塊 130 底部填充膠 140 散熱片 150 黏膠 200 散熱型薄膜覆晶 封裝構造 ' 210 可撓性基板 211 絕緣層 212 金屬層 213 穿孔 214 上表面 215 接點 10A schematic cross-sectional view of a conventional heat dissipating film flip chip package structure. According to a first embodiment of the present invention, a schematic view of a wear surface of a heat dissipating film flip chip package structure. According to a second embodiment of the present invention, a cross-sectional view of another heat dissipating thin film flip chip package structure is shown. [Main component symbol description] 100 Thermal flip chip package structure 110 Substrate 111 Upper surface 112 Circuit layer 113 Cover layer 114 Bump contact 120 Wafer 121 Active surface 122 Back 123 Bump 130 Underfill 140 Heat sink 150 Adhesive 200 Heat sink Type film flip chip package structure '210 flexible substrate 211 insulating layer 212 metal layer 213 perforation 214 upper surface 215 contact 10

200816422 216導熱區塊 2l?覆蓋層 220晶片 221主動面 223導熱凸塊230導熱材 250散熱片 300散熱型薄膜覆晶封裝構造 3 1 0可撓性基板 3 11絕緣層 3 1 3穿孔 3 14上表面 3 1 6覆蓋層 3 1 7外接塾 321主動面 322凸塊 340封膠體 350散熱片 218外接墊 222凸塊 240封膠體 312金屬層 315接點 320晶片 330導熱材200816422 216 Thermal block 2l? Cover layer 220 Wafer 221 Active surface 223 Thermal bumps 230 Thermally conductive material 250 Heat sink 300 Heat-dissipating film Folding package structure 3 1 0 Flexible substrate 3 11 Insulation layer 3 1 3 Perforation 3 14 Surface 3 1 6 Covering layer 3 1 7 External 塾321 Active surface 322 Bump 340 Sealing body 350 Heat sink 218 External pad 222 Bump 240 Sealing body 312 Metal layer 315 Contact 320 Wafer 330 Thermally conductive material

Claims (1)

200816422 十、申請專利範圍： 1、 一種散熱型薄膜覆晶封裝構造，包含： 一可撓性基板，其係具有一絕緣層以及一金屬層，該 絕緣層係具有一穿孔，該金屬層係形成於該絕緣層之 一上表面並包含有複數個接點； 一晶片’其係設於該可撓性基板上方並具有一主動面 以及複數個凸塊，該些凸塊係電性連接至該些接點； _ 一導熱材，其係填充於該絕緣層之該穿孔，以傳導該 晶片所產生之熱能；以及 一封膠體，其徐形成於該可撓性基板與該晶片之間。 2、 如申請專利範圍第1項所述之散熱型薄膜覆晶封裝構 造’其中該導熱材係接觸至該晶片之該主動面。 3、 如申請專利範圍第1項所述之散熱型薄膜覆晶封裝構 造’其中该金屬層係另包含有一導熱區塊，該絕緣居 之該穿孔係顯露該導熱區塊。 φ 4、如申請專利範圍第3項所述之散熱型薄膜覆晶封裝構 造’其中該導熱區塊係稍大於該穿孔。 5、 如申請專利範圍第3項所述之散熱型薄膜覆晶封裝構 造其中該導熱區塊係完全覆蓋該穿孔。 6、 如申請專利範圍第3項所述之散熱型薄膜覆晶封裝構 造’其中該晶片另具有至少一導熱凸塊，其係接合至 該導熱區塊。 7、 如申請專利範圍第1項所述之散熱型薄膜覆晶封裝構 造’其中該導熱材係選自於導熱膠或導熱膏。 12 200816422 8、 如申請專利範圍第i項所述之散熱型薄膜覆晶封裝構 造’另包含有一散熱片，其係貼設於該可撓性基板之 下方，且該散熱片係接觸該導熱材。 9、 如申請專利範圍第8項所述之散熱型薄膜覆晶封裝構 .造’其中該散熱片之尺寸係大於該晶片之尺寸。 1 〇、如申請專利範圍第1項所述之散熱型薄膜覆晶封裝構 造’其中該封膠體係為底部填充膠。 13200816422 X. Patent Application Range: 1. A heat-dissipating film flip-chip package structure comprising: a flexible substrate having an insulating layer and a metal layer, the insulating layer having a perforation, the metal layer forming The upper surface of the insulating layer includes a plurality of contacts; a wafer is disposed on the flexible substrate and has an active surface and a plurality of bumps electrically connected to the a contact; _ a heat conductive material filled in the perforation of the insulating layer to conduct heat generated by the wafer; and a gel formed between the flexible substrate and the wafer. 2. The heat-dissipating film flip chip package structure of claim 1, wherein the heat conductive material contacts the active surface of the wafer. 3. The heat-dissipating film flip-chip package structure of claim 1, wherein the metal layer further comprises a heat-conducting block, wherein the insulating layer exposes the heat-conducting block. φ 4. The heat-dissipating film flip-chip package structure according to claim 3, wherein the heat-conducting block is slightly larger than the through-hole. 5. The heat-dissipating film flip chip package structure of claim 3, wherein the heat-conducting block completely covers the through-hole. 6. The heat-dissipating film flip-chip package structure of claim 3, wherein the wafer further has at least one thermally conductive bump bonded to the thermally conductive block. 7. The heat-dissipating film flip-chip package structure according to claim 1, wherein the heat conductive material is selected from a thermal conductive paste or a thermal conductive paste. 12 200816422 8. The heat-dissipating film flip chip package structure of claim i further includes a heat sink disposed under the flexible substrate, and the heat sink contacts the heat conductive material . 9. The heat-dissipating film flip-chip package of claim 8 wherein the size of the heat sink is greater than the size of the wafer. The heat-dissipating film flip-chip package structure as described in claim 1 wherein the sealant system is an underfill. 13
TW095134655A 2006-09-19 2006-09-19 Heating dissipating chip on film package TW200816422A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777542B (en) * 2009-01-14 2011-08-17 南茂科技股份有限公司 Chip packaging structure and packaging method
TWI777760B (en) * 2021-08-09 2022-09-11 頎邦科技股份有限公司 Flexible printed circuit board with heat-dissipation plate and heat-dissipation plate thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101777542B (en) * 2009-01-14 2011-08-17 南茂科技股份有限公司 Chip packaging structure and packaging method
TWI777760B (en) * 2021-08-09 2022-09-11 頎邦科技股份有限公司 Flexible printed circuit board with heat-dissipation plate and heat-dissipation plate thereof
US11503698B1 (en) 2021-08-09 2022-11-15 Chipbond Technology Corporation Flexible circuit board and heat spreader thereof

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