WO2018095233A1

WO2018095233A1 - Semiconductor structure and forming method therefor, and packaging structure and forming method therefor

Info

Publication number: WO2018095233A1
Application number: PCT/CN2017/110641
Authority: WO
Inventors: 王之奇; 沈志杰; 罗晓峰
Original assignee: 苏州晶方半导体科技股份有限公司
Priority date: 2016-11-24
Filing date: 2017-11-13
Publication date: 2018-05-31

Abstract

A semiconductor structure and a forming method therefor, and a packaging structure and a forming method therefor. The semiconductor structure comprises a substrate (201) and a chip (203). Welding balls (202) are disposed on the substrate (201). The chip (203) is disposed on the substrate (201), and the chip (203) and the welding balls (202) are disposed on a same surface of the substrate (201). The chip (203) is provided with a first surface and a second surface that are opposite to each other. The first surface is opposite to the substrate (201), and the second surface is provided with a heat conducting layer (204). Heat dissipation effects of the semiconductor structure and the packaging structure are improved, and temperatures in and around the chip are prevented from being excessively high, thereby ensuring reliable and effective operation of the chip.

Description

Semiconductor structure, forming method thereof, package structure and forming method thereof

This application claims priority to Chinese Patent Application No. 201611045346.9, entitled "Semiconductor Structure and Its Forming Method, Package Structure and Method of Forming It", filed on November 24, 2016, and in 2016 Priority is filed on Nov. 24, the entire disclosure of which is hereby incorporated by reference in its entirety in its entirety in the the the the the the the the the the

Technical field

The present invention relates to the field of packaging technologies, and in particular, to a semiconductor structure, a method of forming the same, a package structure, and a method of forming the same.

Background technique

With the rapid development of wireless communications, automotive electronics and other consumer electronics, microelectronic packaging technology is moving toward versatility, miniaturization, portability, high speed, low power consumption and high reliability. Among them, System In a Package (SIP) is a new type of packaging technology that can effectively reduce the package area.

Existing multifunctional SIP packaged chips include one or more chips attached to the surface of the substrate. With the high integration of packaged chips, the power of packaged chips is getting larger and larger, so chip heat dissipation has become a problem that must be considered in the packaging process. The heat generated by the chip itself, except for a small part of the heat dissipation through the bottom substrate and the pad, the main heat is dissipated through the surface of the chip. Therefore, the existing chip package design generally adds a heat dissipation cover on the chip, and the heat dissipation cover is pasted on the chip and the substrate through a heat conductive material to form a sealed package structure.

However, the heat dissipation effect of the package structure provided by the prior art needs to be improved, and the package structure having the heat dissipation function is bulky.

Summary of the invention

The problem to be solved by the present invention is to provide a semiconductor structure, a method for forming the same, a package structure, and a method for forming the same, which effectively reduces heat inside and around the chip and prevents the chip from overheating.

In order to solve the above problems, the present invention provides a semiconductor structure including: a substrate, the base a solder ball is disposed on the board; a chip disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, the chip having opposite first and second sides, the first One side is opposite to the substrate, and the second surface has a heat conducting layer.

Optionally, the heat conducting layer is located on the entire second surface.

Optionally, the second surface has a circuit layer; the heat conductive layer is located on a portion of the second surface and is electrically insulated from the circuit layer.

Optionally, the material of the heat conductive layer is a heat conductive resin material or a metal material.

Optionally, the material of the heat conductive layer is one or more of copper, gold, tungsten or tin.

Optionally, a distance between the top of the solder ball and the substrate is greater than a distance between a top of the heat conductive layer and the substrate.

Optionally, a distance between the top of the solder ball and the substrate is equal to a distance between a top of the heat conductive layer and the substrate.

Optionally, the semiconductor structure further includes: a plurality of spaced-apart conductive layers between the substrate and the first surface of the chip, the conductive layer is used to implement electricity between the chip and the substrate connection.

Optionally, the semiconductor structure further includes: an underfill filled between the substrate and the chip.

Optionally, the chip is an image sensing chip, and the chip has an image sensing area.

Optionally, the substrate has an opening penetrating the substrate, and the image sensing area is located above the opening; the semiconductor structure further includes: a transparent cover plate covering the opening, and the The transparent cover plate and the chip are respectively located on opposite sides of the substrate.

Optionally, the substrate is a light transmissive substrate.

Optionally, the semiconductor structure further includes: a sealant on the substrate and covering the sidewall of the chip.

Optionally, the sealant has thermal conductivity.

The present invention also provides a package structure comprising: the foregoing semiconductor structure; a circuit board having a circuit board functional surface, the solder ball and the functional surface of the circuit board being electrically connected, and the heat conductive layer It is in contact with the functional surface of the circuit board.

Optionally, the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contact.

Optionally, the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer.

Optionally, the material of the functional electrical connection layer is the same as the material of the heat dissipation electrical connection layer.

Optionally, the material of the heat dissipation electrical connection layer is one or more of gold, tungsten or solder paste.

The present invention also provides a method of forming the foregoing semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip, the chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.

Optionally, the thermally conductive layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

Optionally, a part of the second surface is disposed with the heat conductive layer; and the step of forming the heat conductive layer includes: forming a heat conductive film completely covering the second surface on the second surface; The heat conductive film forms the heat conductive layer on a part of the second surface.

Optionally, the chip is disposed on the substrate by a solder bonding process.

Optionally, a plurality of pads are formed on the substrate, and the pads are in one-to-one correspondence with the conductive layer; the pads are soldered to the conductive layer by a solder bonding process.

Optionally, the solder ball is formed on the substrate before the chip is disposed on the substrate; or, after the chip is disposed on the substrate, a substrate is formed on the substrate Said solder balls.

Optionally, the process step of forming the chip includes: providing a wafer; forming a heat conductive film on the wafer; cutting the wafer and the heat conductive film to form a plurality of spaced-apart chips And the heat conducting layer.

The present invention also provides a method of forming the foregoing package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface of the circuit board; and disposing the semiconductor structure on the functional surface of the circuit board such that the soldering The ball is electrically connected to the functional surface of the circuit board, and the heat conducting layer is in contact with the functional surface of the circuit board.

Optionally, the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contacting; using a solder bonding process, the solder balls are electrically connected to the functional electrical connection layer, and the heat conductive layer is bonded to the heat dissipation electrical connection layer.

Optionally, the material of the heat conductive layer is a metal material, and the material of the heat dissipation electrical connection layer is a solder paste; and the heat conductive layer is bonded to the heat dissipation electrical connection layer by a eutectic bonding process.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the semiconductor structure provided by the present invention, the chip is disposed on the substrate, the first surface of the chip is opposite to the substrate, and the second surface of the chip has a heat conducting layer, and the chip can be used by the heat conducting layer The heat inside is transmitted to the external environment or components, thereby effectively reducing the heat inside the chip; in addition, the invention avoids the problem that the heat sink collects the heat generated by the chip, so that the heat generated by the chip can be effectively and timely Export to prevent the chip from overheating. At the same time, since the chip and the solder ball are disposed on the same surface of the substrate, and it is not necessary to provide a heat dissipation cover that occupies a large volume, the semiconductor structure provided by the present invention is small in size.

In the technical solution of the package structure provided by the present invention, the circuit board not only has the function of electrically connecting the substrate and the chip, but also has a heat generated inside the conductive chip due to the contact of the circuit board with the heat conductive layer. Function to prevent overheating inside the chip. In addition, the solder ball and the chip are disposed on the same side of the substrate, so the thickness of the package structure provided by the present invention is significantly reduced, and the package structure has a smaller volume.

DRAWINGS

1 is a schematic cross-sectional structural view of a package structure;

2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

3 to FIG. 5 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a package structure according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.

detailed description

According to the background art, the heat dissipation effect of the package structure provided by the prior art is limited, and the package structure is bulky.

Now combined with a package structure for analysis, Figure 1 is a schematic cross-sectional structure of the package structure.

Referring to FIG. 1, the package structure includes a substrate 101 having opposite front and back surfaces, and a plurality of solder balls 102 disposed on a back surface of the substrate 101. The plurality of solder balls 102 may be BGAs (Ball Grid Array) a ball 103 disposed on a front surface of the substrate 101, the chip 103 having opposite functional and non-functional surfaces, wherein the functional surface is opposite to a front surface of the substrate 101, and the substrate 101 and the substrate An electrical connection is made between the chips 103 through the conductive layer 104; a heat dissipation cover 105 located on the front surface of the substrate 101 and surrounding the chip 103, the chip 103 is located in the heat dissipation cover 105, and the chip 103 is non-functional The heat sink cover 105 is next to the heat sink.

In the above package structure, part of the heat generated by the chip 103 is transmitted to the outside through the heat dissipation cover 105. However, the heat dissipation effect of the above package structure is poor, and the reason for the analysis is mainly that since the chip 103 is surrounded by the heat dissipation cover 105, the chip 103 is in a sealed environment; the heat dissipation cover 105 not only has a heat dissipation effect, The heat dissipation cover 105 also has the function of collecting the heat generated by the chip 103. The heat that is not transmitted to the outside by the heat dissipation cover 105 is concentrated in the sealed environment surrounded by the heat dissipation cover 105, resulting in a high temperature around the chip 103. , affect the performance of the chip.

In addition, in the above package structure, the thickness of the package structure is: the sum of the thickness of the BAG ball, the thickness of the substrate 101, and the height of the heat dissipation cover 105, and the height of the heat dissipation cover 105 is greater than the thickness of the chip 103, so the above The thickness of the package structure is thick. And, the heat dissipation cover 105 It is disposed on the substrate 101, so the substrate 101 also needs to reserve a space position for the heat dissipation cover 105. Therefore, the package structure provided above has a large volume, which is disadvantageous for the miniaturization of the chip and the miniaturization toward miniaturization.

In order to solve the above problems, the present invention provides a semiconductor structure that timely and effectively transfers heat generated by the chip, prevents excessive temperature inside and around the chip, ensures efficient operation of the chip, and reduces the volume of the semiconductor structure.

The above described objects, features, and advantages of the present invention will be more apparent from the aspects of the invention.

FIG. 2 is a schematic view showing the structure of a semiconductor structure provided by the embodiment. Referring to FIG. 2, the semiconductor structure includes:

a substrate 201, the substrate 201 is provided with solder balls 202;

a chip 203 disposed above the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same side of the substrate 201. The chip 203 has opposite first faces (not labeled) and second A face (not shown), the first face is opposite the substrate 201, and the second face has a thermally conductive layer 204.

The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

The substrate 201 is used to fix the chip 203 and electrically connect the chip 203 with other devices or circuits. The substrate 201 is a rigid substrate or a flexible substrate; the substrate 201 may also be a transparent substrate, such as an inorganic glass substrate, an organic glass substrate or a filter glass substrate.

In this embodiment, the substrate 201 is a rigid substrate, and the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.

The substrate 201 may further have a plurality of pads (not shown) thereon, and the pads and the solder balls 202 are located on the same side of the substrate 201. The pads are for electrical connection with the chip 203. Specifically, the first surface of the chip 203 has a plurality of mutually discrete conductive layers 205, that is, the conductive layers 205 are spaced apart, and the pads are used for electrical connection with the conductive layer 205. The location and number of pads can be determined based on the number and location of conductive layers 205 in chip 203.

The substrate 201 may further have a circuit layer (not shown), and the chip 203 is electrically connected to the circuit layer.

The cross-sectional shape of the substrate 201 is a square, a circle, a triangle, a regular polygon, or an irregular shape in a direction parallel to the surface of the substrate 201. In the present embodiment, the cross-sectional shape of the substrate 201 is a square.

The solder balls 202 are used to electrically connect the substrate 201 and other devices or external circuits. For example, electrical connection between the substrate 201 and the circuit board can be achieved by the solder balls 202.

In this embodiment, the cross-sectional shape of the solder ball 202 is spherical. In other embodiments, the cross-sectional shape of the solder ball may also be square.

In order to save space, a reasonable layout of the position of the solder ball 202 on the substrate 201 can be made. In this embodiment, the solder balls 202 are distributed on the substrate 201 on the periphery of the chip 203, and the solder balls 202 are symmetrically distributed on the substrate 201.

The chip 203 is a functional chip, such as an image sensing chip. The chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201. In this embodiment, the chip 203 is located in the area of the substrate 201 surrounded by the solder ball 202.

It should be noted that when the chip 203 is an image sensing chip, the chip 203 has an image sensing area (not shown). Correspondingly, the substrate 201 has an opening penetrating through the substrate 201 (not shown). And the image sensing area is located above the opening, so that external light can be transmitted to the image sensing area via the opening. In addition, in order to protect the image sensing area from being contaminated, the semiconductor structure further includes: a transparent cover plate covering the opening, and the transparent cover plate and the chip 203 They are respectively located on opposite sides of the substrate 201.

It should be noted that, when the chip 203 is an image sensing chip, and the chip 203 has an image sensing area, the substrate 201 may also be a transparent substrate, and the corresponding substrate 201 does not need to be disposed through the substrate. The opening of 201.

The first surface of the chip 203 is opposite to the substrate 201, and the first surface of the chip 203 is fixed to the substrate 201. Specifically, in this embodiment, the semiconductor structure further includes: a plurality of separate conductive layers 205 between the substrate 202 and the first side of the chip 203, the conductive layer 205 is used to achieve electrical connection between the chip 203 and the substrate 201, and through the conductive The layer 205 fixes the chip 203 and the substrate 201 to each other.

The position and number of the conductive layer 205 are determined according to the position and number of electrical connections that need to be made on the first side of the chip 203. The material of the conductive layer 205 is one or more of copper, aluminum, tungsten or tin. In this embodiment, the material of the conductive layer 205 is copper.

The second surface of the chip 203 has a heat conductive layer 204. When the chip 203 works to generate heat inside the chip 203, the heat conducting layer 204 can conduct heat inside the chip 203 to the external environment or other devices, so that the heat inside the chip 203 is reduced, and the chip 203 is prevented from being overheated. The problem.

The material of the heat conductive layer 204 is a heat conductive resin material or a metal material. In this embodiment, the material of the heat conductive layer 204 is a metal material, and the material of the heat conductive layer 204 is one or more of copper, tungsten or tin.

The thickness of the heat conducting layer 204 should not be too thin, and should not be too thick. If the thickness of the heat conducting layer 204 is too thin, the heat conducting layer 204 has a limited heat conduction capability, and the heat conducting layer 204 is susceptible to deformation under the heat generated by the chip 203; if the thickness of the heat conducting layer 204 is excessive If the thickness is thick, the overall thickness of the semiconductor structure is also relatively thick, which is disadvantageous for satisfying the development trend of miniaturization and miniaturization of the semiconductor structure.

To this end, in the embodiment, the heat conductive layer 204 has a thickness of 3 micrometers to 8 micrometers, for example, 3 micrometers, 5 micrometers, and 8 micrometers.

In this embodiment, the heat conducting layer 204 is located on the entire second surface of the chip 203. Because the area of the heat conducting layer 204 is large, the heat conducting capability of the heat conducting layer 204 is strong, so that the heat of the chip 203 is highly extracted, effectively avoiding the problem of overheating of the chip 203, and ensuring that the chip 203 is stable and reliable. work.

It should be noted that, in other embodiments, when the second side of the chip has a circuit layer, the thermal conductive layer may also be located in the second part of the chip in consideration of circuit layout on the second surface of the chip. And electrically insulated from the circuit layer to avoid the heat conductive layer and the chip Unnecessary electrical connections occur between them.

It should be noted that, in other embodiments, the material of the heat conductive layer may also be a heat conductive resin material. Since the heat conductive resin material is an insulating material, unnecessary occurrence of unnecessary heat conduction between the heat conductive layer and the chip is avoided. The problem of electrical connection.

The heat conducting layer 204 has limited ability to conduct heat inside the chip 203 to the external environment. When the heat conducting layer 204 is bonded to other components that absorb heat, the heat conducting layer 204 conducts heat to In the component, the energy of the heat conduction layer 204 to conduct heat inside the chip 203 is significantly improved, and the temperature around the chip 203 is effectively reduced.

In addition, in order to reduce the complexity of the semiconductor structure, the component is also a component that is electrically connected to the solder ball 202, so that the chip 203, the substrate 201 and the component are electrically connected through the solder ball 202; therefore, the semiconductor structure is further improved. At the same time as the heat dissipating energy, the electrical connection between the semiconductor structure and the component can be realized, and a more complicated package structure can be formed.

In particular, the component can be a circuit board. To achieve the above object, the heat conducting layer 204 should be in contact with the circuit board, and the solder balls 202 and the circuit board are electrically connected. In the process of electrically connecting the solder ball 202 and the circuit board, the thickness of the solder ball 202 may be reduced; in order to ensure that the solder ball 202 is electrically connected to the circuit board, The heat conducting layer 204 is in contact with the circuit board, and a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than or equal to a distance L2 between the top of the heat conductive layer 204 and the substrate 201.

In this embodiment, a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than a distance L2 between the top of the heat conductive layer 204 and the substrate 201. If the distance (L1-L2) between the top of the solder ball 202 and the top of the heat conductive layer 204 is too large, when the solder ball 202 is electrically connected to the circuit board, the heat conductive layer 204 is not connected to the circuit board. Contact, therefore, the distance between the top of the solder ball 202 and the top of the thermally conductive layer 204 should not be too large. In this embodiment, the distance between the top of the solder ball 202 and the top of the heat conductive layer 204 may satisfy that the heat conductive layer 204 can be eutectic bonded to the heat dissipation electrical connection layer in other components.

According to the above analysis, the thickness of the solder ball 202 can be adjusted according to the thickness of the chip 203, the thickness of the conductive layer 205, and the thickness of the heat conductive layer 204, so that the heat conductive layer 204 can be electrically connected to other components. The layers achieve eutectic bonding.

In one embodiment, the conductive layer 205 has a thickness of 10 micrometers to 20 micrometers, the chip 203 has a thickness of 150 micrometers, the thermally conductive layer 204 has a thickness of 5 micrometers, and the solder balls 202 have a thickness of 200 micrometers. .

In other embodiments, the distance between the top of the solder ball and the substrate may also be equal to the distance between the top of the thermally conductive layer and the substrate. In addition, it should be noted that when the surface of the provided circuit board is not a flat surface, the distance between the top of the solder ball and the substrate may be smaller than the distance between the top of the heat conductive layer and the substrate. The solder ball is ensured to be electrically connected to the circuit board, and the heat conductive layer is in contact with the circuit board.

In order to further improve the bonding stability between the chip 203 and the substrate 201, the semiconductor structure may further include: an under-fill filled between the substrate 201 and the chip 203. The underfill may have thermal conductivity, so the underfill can not only improve the stability between the chip 203 and the substrate 201, but also generate the inside of the chip 203 because the underfill has a heat dissipation function. The heat can be transferred to the external environment via the underfill, thereby reducing the heat accumulated inside the chip 203 and avoiding the problem of overheating of the chip 203.

It should be noted that, when the chip 203 is an image sensing chip, in order to prevent the underfill from contaminating the image sensing area, the underfill may not be disposed in the semiconductor structure, and in order to improve the chip 203 and The bonding property between the substrates 201 further includes: a sealant (not shown) on the substrate 201 and covering the sidewalls of the chip 203. Also, the sealant has thermal conductivity, so that the sealant can not only improve the sealing performance of the chip 203, but also facilitate heat dissipation.

In the semiconductor structure provided by the embodiment, the chip 203 is disposed on the substrate 201, the first surface of the chip 203 is opposite to the substrate 201, and the second surface of the chip 203 has a heat conductive layer 204 through the heat conduction. The layer 204 can conduct heat inside the chip 203 to the external environment or components, thereby effectively reducing the heat inside the chip 203; in addition, the embodiment avoids the problem that the heat sink collects the heat generated by the chip 203, so that The heat generated by the chip 203 can be efficiently and timely released to prevent the chip 203 from overheating. At the same time, since the chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201, it is not necessary to set a large volume. The heat shield, so the semiconductor structure provided by the embodiment is small in size.

The present invention also provides a method of forming the above semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate. The semiconductor structure formed by the invention has good heat dissipation effect on the chip, and the semiconductor structure has a small volume.

FIG. 3 to FIG. 5 are schematic diagrams showing the structure of a semiconductor structure forming process according to an embodiment of the present invention.

Referring to FIG. 3, a substrate 201 is provided on which a solder ball 202 is disposed.

For a description of the substrate 201 and the solder balls 202, reference may be made to the description of the foregoing embodiments.

The number and position of the solder balls 202 can be determined according to the substrate 201 and the subsequently provided chip 203. In this embodiment, in order to save space and reduce the volume of the formed semiconductor structure, the solder balls 202 are symmetrically disposed on the substrate 201 such that the subsequently provided chips are located in the area surrounded by the solder balls 202.

In this embodiment, the solder ball 202 has a spherical shape in cross section, and a solder ball 202 is formed on the substrate 201 by a ball bonding process. In other embodiments, the solder balls may also be formed using a screen printing process and a reflow process.

It should be noted that, in other embodiments, the solder ball may be formed on the substrate after the chip is subsequently disposed on the substrate.

Referring to FIG. 4, a chip 203 is provided having opposing first and second faces, the second face having a thermally conductive layer 204.

The material of the heat conductive layer 204 is a heat conductive resin material or a metal material.

In this embodiment, the material of the heat conductive layer 204 is a metal material, such as one or more of copper, gold, tungsten or tin.

The heat conducting layer 204 is located on the entire second surface of the chip 203. The thermally conductive layer 204 may be formed using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In other embodiments, the thermally conductive layer may also be located on a portion of the second side of the chip; the step of forming the thermally conductive layer includes: forming a thermally conductive film over the entire second side of the chip; The heat conductive film forms a heat conductive layer on the second surface of the chip portion.

In this embodiment, a conductive layer 205 is also formed on the first surface of the chip 203, and the conductive layer 205 is used to realize electrical connection between the chip 203 and the substrate 201. In this embodiment, the conductive layer 205 is formed by a screen printing process. In other embodiments, the conductive layer may also be formed using a deposition process and an etching process.

It should be noted that, in this embodiment, the process step of forming the chip 203 includes: providing a wafer; forming a heat conductive film on the wafer, and forming a heat conductive film on the wafer by using a sputtering process; The wafer and the heat conductive film form a plurality of discrete chips 203 and the heat conductive layer 204.

Referring to FIG. 5, the chip 203 is disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same surface of the upper substrate 201, and the first surface is opposite to the substrate 201. .

The chip 203 is placed on the substrate 201 by a solder bonding process, and the chip 203 is fixedly bonded to the substrate 201.

Specifically, the substrate 201 is connected to the conductive layer 205 such that the chip 203 is disposed on the substrate 201. Pads (not shown) are formed on the substrate 201, and each pad corresponds to a discrete conductive layer 205. The pads are solder bonded to the conductive layer 205 using a solder bonding process.

The solder bonding process is eutectic bonding, ultrasonic hot pressing, hot press welding, ultrasonic pressure welding, or the like. For example, when the material of the conductive layer 205 is Al, the material of the pad on the substrate 201 is Au, the solder bonding process is ultrasonic hot pressing; when the material of the conductive layer 205 is Au, The material of the pad on the substrate 201 is Sn, and the solder bonding process is a eutectic bonding method.

In this embodiment, the chip 203 is located in a region surrounded by the solder ball 202. For the positional relationship between the top of the solder ball 202 and the top of the heat conductive layer 204, reference may be made to the corresponding description in the foregoing embodiments, and details are not described herein again.

A step of forming a heat dissipating gel covering the sidewall of the chip 203 on the substrate 201 may also be included. The heat dissipating glue may be formed by a dispensing process or a plastic sealing process. The heat dissipating adhesive not only functions to further fix the chip 203 and the substrate 201, but also functions as a heat sink to further reduce heat inside the chip 203.

The embodiment of the present invention further provides a package structure, and FIG. 6 shows a schematic structural view of a package structure provided by an embodiment of the present invention.

Referring to FIG. 6, the package structure includes:

The semiconductor structure provided by the foregoing embodiment includes: a substrate 201 on which a solder ball 202 is disposed; a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the substrate On the same side of 201, the chip 203 has opposite first and second faces, the first face is opposite to the substrate 201, the second face has a heat conducting layer 204;

The circuit board 301 has a functional surface, and the solder ball 202 is electrically connected to the functional surface of the circuit board 301, and the heat conductive layer 204 is in contact with the functional surface of the circuit board 301.

The package structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

For a description of the semiconductor structure, reference may be made to the corresponding description of the foregoing embodiments, and details are not described herein again.

In this embodiment, the circuit board 301 is a PCB board. The function board 301 has a functional electrical connection layer 311 and a heat dissipation electrical connection layer 312 which are separated from each other. The functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 are spaced apart from each other on the functional surface of the circuit board 301. The solder ball 202 is electrically connected to the functional electrical connection layer 311, and the heat conductive layer 204 is in contact with the heat dissipation electrical connection layer 312.

The solder ball 202 realizes electrical connection between the circuit board 301 and the substrate 201 and the chip 203 through the functional electrical connection layer 311. At the same time, since the heat conducting layer 204 is in contact with the heat dissipation electrical connection layer 312, heat generated inside the chip 203 is transferred to the heat dissipation electrical connection layer 312 via the heat conduction layer 204, so that the chip 203 is internally generated. The heat can be dissipated via the circuit board 301. The heat dissipation effect of the circuit board 301 is good, so that the heat inside the chip 203 is conducted in time and effectively, and the chip 203 is effectively operated.

In this embodiment, the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312. In other embodiments, the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer to ensure the solder ball The electrical connection layer is electrically connected to the functional electrical connection layer, and the thermal conductive layer is in contact with the heat dissipation electrical connection.

The heat conductive layer 204 and the heat dissipation electrical connection layer 312 are bonded to each other. The material of the heat dissipation electrical connection layer 312 is one or more of gold, tungsten or solder paste. In this embodiment, the material of the heat dissipation electrical connection layer 312 is solder paste, and the heat conduction layer 204 is in contact with the heat dissipation electrical connection layer 312 by eutectic bonding.

In this embodiment, the material of the functional electrical connection layer 311 is the same as the material of the heat dissipation electrical connection layer 312. In other embodiments, the material of the functional electrical connection layer may also be different from the material of the heat dissipation electrical connection layer.

In the package structure provided by the embodiment, the circuit board 301 not only has the function of electrically connecting the substrate 201 and the chip 203, but also has the function of generating heat inside the conductive chip 203 to prevent overheating of the chip 203.

And because the solder ball 202 and the chip 203 are disposed on the same surface of the substrate 201, compared with the technical solution that the solder and the chip are disposed on opposite sides of the substrate, the thickness of the package structure provided by the embodiment Significantly reduced, the package structure has a smaller volume.

The embodiment of the present invention further provides a method for forming the above package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface; and disposing the semiconductor structure on the functional surface of the circuit board, so that the soldering The ball is electrically connected to the functional surface of the circuit board, and the thermally conductive layer is in contact with the function of the circuit board. In the package structure formed by the invention, the circuit board can realize the electrical connection with the substrate and the chip, and also can contact the heat conductive layer to timely and effectively transfer the heat generated by the chip, thereby improving the heat dissipation effect of the package structure. And reduce the volume of the package structure.

Referring to Figure 2, a semiconductor structure is provided.

The semiconductor structure includes a substrate 201 on which a solder ball 202 is disposed, a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same side of the substrate 201. The chip 203 has opposite first and second faces, the first face being opposite to the substrate 201, and the second face having a heat conductive layer 204. The first surface and the substrate 201 further have a plurality of conductive layers 205 separated from each other.

Referring to Figure 7, a circuit board 301 having a functional surface is provided.

In this embodiment, the circuit board 301 is a PCB board. The functional surface is a surface that is subsequently bonded to the semiconductor structure.

The circuit board 301 has functional electrical connection layers 311 and heat dissipation electrical connection layers 312 separated from each other. The functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 may be formed on the circuit board 301 by a printing process.

In this embodiment, the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312. In other embodiments, the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer may be flush with the top of the heat dissipation electrical connection layer.

The material of the heat dissipation electrical connection layer 312 is one or more of tin, gold or tungsten. In this embodiment, the material of the heat dissipation electrical connection layer 312 is tin.

In this embodiment, the material of the heat dissipation electrical connection layer 312 is the same as the material of the functional electrical connection layer 311.

Referring to FIG. 6, the semiconductor structure is disposed on a functional surface of the circuit board 301 such that the solder ball 202 is electrically connected to a functional surface of the circuit board 301, and the heat conductive layer 204 and the circuit board are The 301 functional surface is in contact.

Specifically, the solder ball 202 is bonded to the functional electrical connection layer 311 by a solder bonding process such that the heat conductive layer 204 is bonded to the heat dissipation electrical connection layer 312.

In this embodiment, the material of the heat dissipation electrical connection layer 312 is a solder paste, and the material of the heat conduction layer 204 is a metal material; the eutectic bonding process is used to make the heat conduction layer 204 and the heat dissipation electrical connection layer 312 Bond. The bonding interface between the heat conducting layer 204 and the heat dissipating electrical connection layer 312 is such that the heat conducting layer 204 and the heat dissipating electrical connection layer 312 are eutectic bonded. Has excellent thermal conductivity.

It should be noted that, in other embodiments, the thermal conductive layer may be bonded to the functional surface of the circuit board by ultrasonic hot pressing, thermocompression bonding or ultrasonic pressure welding, etc., so that the thermal conductive layer and the thermal conductive layer The heat-dissipating electrical connection layers are in contact.

In this embodiment, before the solder bonding process is performed, the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312, and the top of the solder ball 202 is higher than the top of the thermal conductive layer 204. In the process of bonding the solder ball 202 to the functional electrical connection layer 311 by a solder bonding process, the thickness of the solder ball 202 may be reduced, so when the solder ball 202 and the function When the electrical connection layer 311 is electrically connected, the heat conduction layer 204 and the heat dissipation electrical connection layer 312 can be bonded to each other, that is, the heat conduction layer 204 is in contact with the functional surface of the circuit board 301.

Although the present invention has been disclosed above, the present invention is not limited thereto. Any changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be determined by the scope defined by the appended claims.

Claims

A semiconductor structure, comprising:

a substrate on which a solder ball is disposed;

a chip disposed on the substrate, wherein the chip and the solder ball are disposed on a same side of the substrate, the chip having opposite first and second faces, the first face being opposite to the substrate The second surface has a heat conducting layer.
The semiconductor structure of claim 1 wherein said thermally conductive layer is located throughout said second side.
The semiconductor structure of claim 1 wherein said second side has a wiring layer; said thermally conductive layer being located on said portion of said second side and electrically insulated from said wiring layer.
The semiconductor structure according to claim 1, wherein the material of the heat conductive layer is a thermally conductive resin material or a metal material.
The semiconductor structure according to claim 1 or 4, wherein the material of the heat conductive layer is one or more of copper, gold, tungsten or tin.
The semiconductor structure of claim 1 wherein a distance between said solder ball top and said substrate is greater than a distance between said top of said thermally conductive layer and said substrate.
The semiconductor structure of claim 1 wherein a distance between said solder ball top and said substrate is equal to a distance between said top of said thermally conductive layer and said substrate.
The semiconductor structure of claim 1 further comprising: a plurality of spaced apart conductive layers between said substrate and said first side, said conductive layer for achieving said An electrical connection between the chip and the substrate.
The semiconductor structure of claim 1 further comprising: an underfill filled between said substrate and said chip.
The semiconductor structure of claim 1 wherein said chip is an image sensing chip and said chip has an image sensing area.
The semiconductor structure of claim 10, wherein the substrate has an opening through the substrate, and the image sensing region is located above the opening; the semiconductor structure further comprises: covering the opening a transparent cover plate, and the transparent cover plate and the chip are respectively located on opposite sides of the substrate.
The semiconductor structure of claim 10 wherein said substrate is a light transmissive substrate.
The semiconductor structure of claim 10 wherein said semiconductor structure further comprises: a sealant on said substrate and covering said sidewalls of said chip.
The semiconductor structure of claim 13 wherein said sealant has thermal conductivity.
A package structure, comprising:

A semiconductor structure according to any one of claims 1 to 14;

a circuit board having a circuit board functional surface, the solder ball being electrically connected to the circuit board functional surface, and the heat conductive layer being in contact with the circuit board functional surface.
The package structure as claimed in claim 15 , wherein the functional surface of the circuit board has spaced apart functional electrical connection layers and heat dissipation electrical connection layers; wherein the solder balls are electrically connected to the functional electrical connection layer The heat conductive layer is in contact with the heat dissipation electrical connection layer.
The package structure of claim 16 wherein the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer.
The package structure according to claim 16, wherein the material of the functional electrical connection layer is the same as the material of the heat dissipation electrical connection layer.
The package structure according to claim 16, wherein the material of the heat dissipation electrical connection layer is one or more of gold, tungsten or solder paste.
A method of forming a semiconductor structure according to any one of claims 1 to 14, comprising:

Providing a substrate on which a solder ball is disposed;

Providing a chip having opposite first and second faces, the second face having a thermally conductive layer;

The chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
The method of forming a semiconductor structure according to claim 20, wherein the thermally conductive layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
A method of forming a semiconductor structure according to claim 20, wherein a part of said second surface is provided with said heat conducting layer; and said forming step of said heat conducting layer comprises: forming a complete covering on said second surface a heat conductive film on the second surface; the heat conductive film is patterned to form the heat conductive layer on a portion of the second surface.
A method of forming a semiconductor structure according to claim 20, wherein said chip is disposed on said substrate by a solder bonding process.
The method of forming a semiconductor structure according to claim 23, wherein a plurality of pads are formed on the substrate, and the pads are in one-to-one correspondence with the conductive layer; A pad is solder bonded to the conductive layer.
A method of forming a semiconductor structure according to claim 20, wherein said solder ball is formed on said substrate before said chip is disposed on said substrate; or After the substrate is on, the solder balls are formed on the substrate.
The method of forming a semiconductor structure according to claim 20, wherein the step of forming the chip comprises: providing a wafer; forming a heat conductive film on the wafer; cutting the wafer and a heat conductive film to form A plurality of spaced apart said chips and said thermally conductive layer.
A method of forming a package structure according to any one of claims 15 to 19, comprising:

Providing the semiconductor structure of any one of claims 1 to 14;

Providing a circuit board having a functional surface of the circuit board;

The semiconductor structure is disposed on the functional surface of the circuit board such that the solder ball is electrically connected to the functional surface of the circuit board, and the heat conductive layer is in contact with the functional surface of the circuit board.
The method of forming a package structure according to claim 27, wherein the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the function The layer is electrically connected, the heat conducting layer is in contact with the heat dissipating electrical connection layer; the solder ball is electrically connected to the functional electrical connection layer by a solder bonding process, and the heat conducting layer and the heat dissipating electrical connection layer are Bond.
The method of forming a package structure according to claim 28, wherein the material of the heat conductive layer is a metal material, the material of the heat dissipation electrical connection layer is a solder paste; and the heat conductive layer is formed by a eutectic bonding process. Bonding to the heat dissipation electrical connection layer.