WO2018095233A1 - Structure semiconductrice et son procédé de formation, et structure d'emballage et son procédé de formation - Google Patents

Structure semiconductrice et son procédé de formation, et structure d'emballage et son procédé de formation Download PDF

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Publication number
WO2018095233A1
WO2018095233A1 PCT/CN2017/110641 CN2017110641W WO2018095233A1 WO 2018095233 A1 WO2018095233 A1 WO 2018095233A1 CN 2017110641 W CN2017110641 W CN 2017110641W WO 2018095233 A1 WO2018095233 A1 WO 2018095233A1
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WO
WIPO (PCT)
Prior art keywords
substrate
chip
semiconductor structure
layer
electrical connection
Prior art date
Application number
PCT/CN2017/110641
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English (en)
Chinese (zh)
Inventor
王之奇
沈志杰
罗晓峰
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN201611045346.9A external-priority patent/CN106449551B/zh
Priority claimed from CN201621266619.8U external-priority patent/CN206259339U/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Publication of WO2018095233A1 publication Critical patent/WO2018095233A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to the field of packaging technologies, and in particular, to a semiconductor structure, a method of forming the same, a package structure, and a method of forming the same.
  • SIP System In a Package
  • Existing multifunctional SIP packaged chips include one or more chips attached to the surface of the substrate. With the high integration of packaged chips, the power of packaged chips is getting larger and larger, so chip heat dissipation has become a problem that must be considered in the packaging process. The heat generated by the chip itself, except for a small part of the heat dissipation through the bottom substrate and the pad, the main heat is dissipated through the surface of the chip. Therefore, the existing chip package design generally adds a heat dissipation cover on the chip, and the heat dissipation cover is pasted on the chip and the substrate through a heat conductive material to form a sealed package structure.
  • the problem to be solved by the present invention is to provide a semiconductor structure, a method for forming the same, a package structure, and a method for forming the same, which effectively reduces heat inside and around the chip and prevents the chip from overheating.
  • the present invention provides a semiconductor structure including: a substrate, the base a solder ball is disposed on the board; a chip disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, the chip having opposite first and second sides, the first One side is opposite to the substrate, and the second surface has a heat conducting layer.
  • the heat conducting layer is located on the entire second surface.
  • the second surface has a circuit layer; the heat conductive layer is located on a portion of the second surface and is electrically insulated from the circuit layer.
  • the material of the heat conductive layer is a heat conductive resin material or a metal material.
  • the material of the heat conductive layer is one or more of copper, gold, tungsten or tin.
  • a distance between the top of the solder ball and the substrate is greater than a distance between a top of the heat conductive layer and the substrate.
  • a distance between the top of the solder ball and the substrate is equal to a distance between a top of the heat conductive layer and the substrate.
  • the semiconductor structure further includes: a plurality of spaced-apart conductive layers between the substrate and the first surface of the chip, the conductive layer is used to implement electricity between the chip and the substrate connection.
  • the semiconductor structure further includes: an underfill filled between the substrate and the chip.
  • the chip is an image sensing chip, and the chip has an image sensing area.
  • the substrate has an opening penetrating the substrate, and the image sensing area is located above the opening;
  • the semiconductor structure further includes: a transparent cover plate covering the opening, and the The transparent cover plate and the chip are respectively located on opposite sides of the substrate.
  • the substrate is a light transmissive substrate.
  • the semiconductor structure further includes: a sealant on the substrate and covering the sidewall of the chip.
  • the sealant has thermal conductivity.
  • the present invention also provides a package structure comprising: the foregoing semiconductor structure; a circuit board having a circuit board functional surface, the solder ball and the functional surface of the circuit board being electrically connected, and the heat conductive layer It is in contact with the functional surface of the circuit board.
  • the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contact.
  • the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer.
  • the material of the functional electrical connection layer is the same as the material of the heat dissipation electrical connection layer.
  • the material of the heat dissipation electrical connection layer is one or more of gold, tungsten or solder paste.
  • the present invention also provides a method of forming the foregoing semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip, the chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
  • the thermally conductive layer is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
  • a part of the second surface is disposed with the heat conductive layer; and the step of forming the heat conductive layer includes: forming a heat conductive film completely covering the second surface on the second surface; The heat conductive film forms the heat conductive layer on a part of the second surface.
  • the chip is disposed on the substrate by a solder bonding process.
  • a plurality of pads are formed on the substrate, and the pads are in one-to-one correspondence with the conductive layer; the pads are soldered to the conductive layer by a solder bonding process.
  • the solder ball is formed on the substrate before the chip is disposed on the substrate; or, after the chip is disposed on the substrate, a substrate is formed on the substrate Said solder balls.
  • the process step of forming the chip includes: providing a wafer; forming a heat conductive film on the wafer; cutting the wafer and the heat conductive film to form a plurality of spaced-apart chips And the heat conducting layer.
  • the present invention also provides a method of forming the foregoing package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface of the circuit board; and disposing the semiconductor structure on the functional surface of the circuit board such that the soldering The ball is electrically connected to the functional surface of the circuit board, and the heat conducting layer is in contact with the functional surface of the circuit board.
  • the functional surface of the circuit board has spaced apart functional electrical connection layers and a heat dissipation electrical connection layer; wherein the solder balls are electrically connected to the functional electrical connection layer, and the thermal conduction layer and the heat dissipation electrical connection layer Contacting; using a solder bonding process, the solder balls are electrically connected to the functional electrical connection layer, and the heat conductive layer is bonded to the heat dissipation electrical connection layer.
  • the material of the heat conductive layer is a metal material, and the material of the heat dissipation electrical connection layer is a solder paste; and the heat conductive layer is bonded to the heat dissipation electrical connection layer by a eutectic bonding process.
  • the chip is disposed on the substrate, the first surface of the chip is opposite to the substrate, and the second surface of the chip has a heat conducting layer, and the chip can be used by the heat conducting layer
  • the heat inside is transmitted to the external environment or components, thereby effectively reducing the heat inside the chip; in addition, the invention avoids the problem that the heat sink collects the heat generated by the chip, so that the heat generated by the chip can be effectively and timely Export to prevent the chip from overheating.
  • the semiconductor structure provided by the present invention is small in size.
  • the circuit board not only has the function of electrically connecting the substrate and the chip, but also has a heat generated inside the conductive chip due to the contact of the circuit board with the heat conductive layer. Function to prevent overheating inside the chip.
  • the solder ball and the chip are disposed on the same side of the substrate, so the thickness of the package structure provided by the present invention is significantly reduced, and the package structure has a smaller volume.
  • FIG. 1 is a schematic cross-sectional structural view of a package structure
  • FIG. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • FIG. 3 to FIG. 5 are schematic cross-sectional structural views showing a process of forming a semiconductor structure according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a package structure according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.
  • the heat dissipation effect of the package structure provided by the prior art is limited, and the package structure is bulky.
  • Figure 1 is a schematic cross-sectional structure of the package structure.
  • the package structure includes a substrate 101 having opposite front and back surfaces, and a plurality of solder balls 102 disposed on a back surface of the substrate 101.
  • the plurality of solder balls 102 may be BGAs (Ball Grid Array) a ball 103 disposed on a front surface of the substrate 101, the chip 103 having opposite functional and non-functional surfaces, wherein the functional surface is opposite to a front surface of the substrate 101, and the substrate 101 and the substrate An electrical connection is made between the chips 103 through the conductive layer 104; a heat dissipation cover 105 located on the front surface of the substrate 101 and surrounding the chip 103, the chip 103 is located in the heat dissipation cover 105, and the chip 103 is non-functional
  • the heat sink cover 105 is next to the heat sink.
  • the heat dissipation effect of the above package structure is poor, and the reason for the analysis is mainly that since the chip 103 is surrounded by the heat dissipation cover 105, the chip 103 is in a sealed environment; the heat dissipation cover 105 not only has a heat dissipation effect, The heat dissipation cover 105 also has the function of collecting the heat generated by the chip 103. The heat that is not transmitted to the outside by the heat dissipation cover 105 is concentrated in the sealed environment surrounded by the heat dissipation cover 105, resulting in a high temperature around the chip 103. , affect the performance of the chip.
  • the thickness of the package structure is: the sum of the thickness of the BAG ball, the thickness of the substrate 101, and the height of the heat dissipation cover 105, and the height of the heat dissipation cover 105 is greater than the thickness of the chip 103, so the above The thickness of the package structure is thick.
  • the heat dissipation cover 105 It is disposed on the substrate 101, so the substrate 101 also needs to reserve a space position for the heat dissipation cover 105. Therefore, the package structure provided above has a large volume, which is disadvantageous for the miniaturization of the chip and the miniaturization toward miniaturization.
  • the present invention provides a semiconductor structure that timely and effectively transfers heat generated by the chip, prevents excessive temperature inside and around the chip, ensures efficient operation of the chip, and reduces the volume of the semiconductor structure.
  • FIG. 2 is a schematic view showing the structure of a semiconductor structure provided by the embodiment.
  • the semiconductor structure includes:
  • the substrate 201 is provided with solder balls 202;
  • the chip 203 has opposite first faces (not labeled) and second A face (not shown), the first face is opposite the substrate 201, and the second face has a thermally conductive layer 204.
  • the substrate 201 is used to fix the chip 203 and electrically connect the chip 203 with other devices or circuits.
  • the substrate 201 is a rigid substrate or a flexible substrate; the substrate 201 may also be a transparent substrate, such as an inorganic glass substrate, an organic glass substrate or a filter glass substrate.
  • the substrate 201 is a rigid substrate
  • the rigid substrate is a PCB substrate, a glass substrate, a metal substrate, a semiconductor substrate, or a polymer substrate.
  • the substrate 201 may further have a plurality of pads (not shown) thereon, and the pads and the solder balls 202 are located on the same side of the substrate 201.
  • the pads are for electrical connection with the chip 203.
  • the first surface of the chip 203 has a plurality of mutually discrete conductive layers 205, that is, the conductive layers 205 are spaced apart, and the pads are used for electrical connection with the conductive layer 205.
  • the location and number of pads can be determined based on the number and location of conductive layers 205 in chip 203.
  • the substrate 201 may further have a circuit layer (not shown), and the chip 203 is electrically connected to the circuit layer.
  • the cross-sectional shape of the substrate 201 is a square, a circle, a triangle, a regular polygon, or an irregular shape in a direction parallel to the surface of the substrate 201.
  • the cross-sectional shape of the substrate 201 is a square.
  • the solder balls 202 are used to electrically connect the substrate 201 and other devices or external circuits. For example, electrical connection between the substrate 201 and the circuit board can be achieved by the solder balls 202.
  • the cross-sectional shape of the solder ball 202 is spherical. In other embodiments, the cross-sectional shape of the solder ball may also be square.
  • solder balls 202 are distributed on the substrate 201 on the periphery of the chip 203, and the solder balls 202 are symmetrically distributed on the substrate 201.
  • the chip 203 is a functional chip, such as an image sensing chip.
  • the chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201.
  • the chip 203 is located in the area of the substrate 201 surrounded by the solder ball 202.
  • the chip 203 when the chip 203 is an image sensing chip, the chip 203 has an image sensing area (not shown).
  • the substrate 201 has an opening penetrating through the substrate 201 (not shown). And the image sensing area is located above the opening, so that external light can be transmitted to the image sensing area via the opening.
  • the semiconductor structure further includes: a transparent cover plate covering the opening, and the transparent cover plate and the chip 203 They are respectively located on opposite sides of the substrate 201.
  • the substrate 201 may also be a transparent substrate, and the corresponding substrate 201 does not need to be disposed through the substrate. The opening of 201.
  • the first surface of the chip 203 is opposite to the substrate 201, and the first surface of the chip 203 is fixed to the substrate 201.
  • the semiconductor structure further includes: a plurality of separate conductive layers 205 between the substrate 202 and the first side of the chip 203, the conductive layer 205 is used to achieve electrical connection between the chip 203 and the substrate 201, and through the conductive The layer 205 fixes the chip 203 and the substrate 201 to each other.
  • the position and number of the conductive layer 205 are determined according to the position and number of electrical connections that need to be made on the first side of the chip 203.
  • the material of the conductive layer 205 is one or more of copper, aluminum, tungsten or tin. In this embodiment, the material of the conductive layer 205 is copper.
  • the second surface of the chip 203 has a heat conductive layer 204.
  • the heat conducting layer 204 can conduct heat inside the chip 203 to the external environment or other devices, so that the heat inside the chip 203 is reduced, and the chip 203 is prevented from being overheated. The problem.
  • the material of the heat conductive layer 204 is a heat conductive resin material or a metal material.
  • the material of the heat conductive layer 204 is a metal material, and the material of the heat conductive layer 204 is one or more of copper, tungsten or tin.
  • the thickness of the heat conducting layer 204 should not be too thin, and should not be too thick. If the thickness of the heat conducting layer 204 is too thin, the heat conducting layer 204 has a limited heat conduction capability, and the heat conducting layer 204 is susceptible to deformation under the heat generated by the chip 203; if the thickness of the heat conducting layer 204 is excessive If the thickness is thick, the overall thickness of the semiconductor structure is also relatively thick, which is disadvantageous for satisfying the development trend of miniaturization and miniaturization of the semiconductor structure.
  • the heat conductive layer 204 has a thickness of 3 micrometers to 8 micrometers, for example, 3 micrometers, 5 micrometers, and 8 micrometers.
  • the heat conducting layer 204 is located on the entire second surface of the chip 203. Because the area of the heat conducting layer 204 is large, the heat conducting capability of the heat conducting layer 204 is strong, so that the heat of the chip 203 is highly extracted, effectively avoiding the problem of overheating of the chip 203, and ensuring that the chip 203 is stable and reliable. work.
  • the thermal conductive layer may also be located in the second part of the chip in consideration of circuit layout on the second surface of the chip. And electrically insulated from the circuit layer to avoid the heat conductive layer and the chip Unnecessary electrical connections occur between them.
  • the material of the heat conductive layer may also be a heat conductive resin material. Since the heat conductive resin material is an insulating material, unnecessary occurrence of unnecessary heat conduction between the heat conductive layer and the chip is avoided. The problem of electrical connection.
  • the heat conducting layer 204 has limited ability to conduct heat inside the chip 203 to the external environment. When the heat conducting layer 204 is bonded to other components that absorb heat, the heat conducting layer 204 conducts heat to In the component, the energy of the heat conduction layer 204 to conduct heat inside the chip 203 is significantly improved, and the temperature around the chip 203 is effectively reduced.
  • the component is also a component that is electrically connected to the solder ball 202, so that the chip 203, the substrate 201 and the component are electrically connected through the solder ball 202; therefore, the semiconductor structure is further improved.
  • the electrical connection between the semiconductor structure and the component can be realized, and a more complicated package structure can be formed.
  • the component can be a circuit board.
  • the heat conducting layer 204 should be in contact with the circuit board, and the solder balls 202 and the circuit board are electrically connected. In the process of electrically connecting the solder ball 202 and the circuit board, the thickness of the solder ball 202 may be reduced; in order to ensure that the solder ball 202 is electrically connected to the circuit board, The heat conducting layer 204 is in contact with the circuit board, and a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than or equal to a distance L2 between the top of the heat conductive layer 204 and the substrate 201.
  • a distance L1 between the top of the solder ball 202 and the substrate 201 is greater than a distance L2 between the top of the heat conductive layer 204 and the substrate 201. If the distance (L1-L2) between the top of the solder ball 202 and the top of the heat conductive layer 204 is too large, when the solder ball 202 is electrically connected to the circuit board, the heat conductive layer 204 is not connected to the circuit board. Contact, therefore, the distance between the top of the solder ball 202 and the top of the thermally conductive layer 204 should not be too large. In this embodiment, the distance between the top of the solder ball 202 and the top of the heat conductive layer 204 may satisfy that the heat conductive layer 204 can be eutectic bonded to the heat dissipation electrical connection layer in other components.
  • the thickness of the solder ball 202 can be adjusted according to the thickness of the chip 203, the thickness of the conductive layer 205, and the thickness of the heat conductive layer 204, so that the heat conductive layer 204 can be electrically connected to other components.
  • the layers achieve eutectic bonding.
  • the conductive layer 205 has a thickness of 10 micrometers to 20 micrometers
  • the chip 203 has a thickness of 150 micrometers
  • the thermally conductive layer 204 has a thickness of 5 micrometers
  • the solder balls 202 have a thickness of 200 micrometers. .
  • the distance between the top of the solder ball and the substrate may also be equal to the distance between the top of the thermally conductive layer and the substrate.
  • the distance between the top of the solder ball and the substrate may be smaller than the distance between the top of the heat conductive layer and the substrate. The solder ball is ensured to be electrically connected to the circuit board, and the heat conductive layer is in contact with the circuit board.
  • the semiconductor structure may further include: an under-fill filled between the substrate 201 and the chip 203.
  • the underfill may have thermal conductivity, so the underfill can not only improve the stability between the chip 203 and the substrate 201, but also generate the inside of the chip 203 because the underfill has a heat dissipation function. The heat can be transferred to the external environment via the underfill, thereby reducing the heat accumulated inside the chip 203 and avoiding the problem of overheating of the chip 203.
  • the underfill may not be disposed in the semiconductor structure, and in order to improve the chip 203 and
  • the bonding property between the substrates 201 further includes: a sealant (not shown) on the substrate 201 and covering the sidewalls of the chip 203. Also, the sealant has thermal conductivity, so that the sealant can not only improve the sealing performance of the chip 203, but also facilitate heat dissipation.
  • the chip 203 is disposed on the substrate 201, the first surface of the chip 203 is opposite to the substrate 201, and the second surface of the chip 203 has a heat conductive layer 204 through the heat conduction.
  • the layer 204 can conduct heat inside the chip 203 to the external environment or components, thereby effectively reducing the heat inside the chip 203; in addition, the embodiment avoids the problem that the heat sink collects the heat generated by the chip 203, so that The heat generated by the chip 203 can be efficiently and timely released to prevent the chip 203 from overheating.
  • the chip 203 and the solder ball 202 are disposed on the same surface of the substrate 201, it is not necessary to set a large volume.
  • the heat shield, so the semiconductor structure provided by the embodiment is small in size.
  • the present invention also provides a method of forming the above semiconductor structure, comprising: providing a substrate on which a solder ball is disposed; providing a chip having opposite first and second faces, the second face Having a thermally conductive layer; the chip is disposed on the substrate, and the chip and the solder ball are disposed on a same side of the substrate, and the first surface is opposite to the substrate.
  • the semiconductor structure formed by the invention has good heat dissipation effect on the chip, and the semiconductor structure has a small volume.
  • FIG. 3 to FIG. 5 are schematic diagrams showing the structure of a semiconductor structure forming process according to an embodiment of the present invention.
  • a substrate 201 is provided on which a solder ball 202 is disposed.
  • the number and position of the solder balls 202 can be determined according to the substrate 201 and the subsequently provided chip 203.
  • the solder balls 202 are symmetrically disposed on the substrate 201 such that the subsequently provided chips are located in the area surrounded by the solder balls 202.
  • the solder ball 202 has a spherical shape in cross section, and a solder ball 202 is formed on the substrate 201 by a ball bonding process.
  • the solder balls may also be formed using a screen printing process and a reflow process.
  • the solder ball may be formed on the substrate after the chip is subsequently disposed on the substrate.
  • a chip 203 is provided having opposing first and second faces, the second face having a thermally conductive layer 204.
  • the material of the heat conductive layer 204 is a heat conductive resin material or a metal material.
  • the material of the heat conductive layer 204 is a metal material, such as one or more of copper, gold, tungsten or tin.
  • the heat conducting layer 204 is located on the entire second surface of the chip 203.
  • the thermally conductive layer 204 may be formed using a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
  • the thermally conductive layer may also be located on a portion of the second side of the chip; the step of forming the thermally conductive layer includes: forming a thermally conductive film over the entire second side of the chip; The heat conductive film forms a heat conductive layer on the second surface of the chip portion.
  • a conductive layer 205 is also formed on the first surface of the chip 203, and the conductive layer 205 is used to realize electrical connection between the chip 203 and the substrate 201.
  • the conductive layer 205 is formed by a screen printing process. In other embodiments, the conductive layer may also be formed using a deposition process and an etching process.
  • the process step of forming the chip 203 includes: providing a wafer; forming a heat conductive film on the wafer, and forming a heat conductive film on the wafer by using a sputtering process; The wafer and the heat conductive film form a plurality of discrete chips 203 and the heat conductive layer 204.
  • the chip 203 is disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same surface of the upper substrate 201, and the first surface is opposite to the substrate 201. .
  • the chip 203 is placed on the substrate 201 by a solder bonding process, and the chip 203 is fixedly bonded to the substrate 201.
  • the substrate 201 is connected to the conductive layer 205 such that the chip 203 is disposed on the substrate 201.
  • Pads (not shown) are formed on the substrate 201, and each pad corresponds to a discrete conductive layer 205. The pads are solder bonded to the conductive layer 205 using a solder bonding process.
  • the solder bonding process is eutectic bonding, ultrasonic hot pressing, hot press welding, ultrasonic pressure welding, or the like.
  • the solder bonding process is ultrasonic hot pressing; when the material of the conductive layer 205 is Au, The material of the pad on the substrate 201 is Sn, and the solder bonding process is a eutectic bonding method.
  • the chip 203 is located in a region surrounded by the solder ball 202.
  • the top of the solder ball 202 and the top of the heat conductive layer 204 reference may be made to the corresponding description in the foregoing embodiments, and details are not described herein again.
  • a step of forming a heat dissipating gel covering the sidewall of the chip 203 on the substrate 201 may also be included.
  • the heat dissipating glue may be formed by a dispensing process or a plastic sealing process.
  • the heat dissipating adhesive not only functions to further fix the chip 203 and the substrate 201, but also functions as a heat sink to further reduce heat inside the chip 203.
  • FIG. 6 shows a schematic structural view of a package structure provided by an embodiment of the present invention.
  • the package structure includes:
  • the semiconductor structure provided by the foregoing embodiment includes: a substrate 201 on which a solder ball 202 is disposed; a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the substrate On the same side of 201, the chip 203 has opposite first and second faces, the first face is opposite to the substrate 201, the second face has a heat conducting layer 204;
  • the circuit board 301 has a functional surface, and the solder ball 202 is electrically connected to the functional surface of the circuit board 301, and the heat conductive layer 204 is in contact with the functional surface of the circuit board 301.
  • the circuit board 301 is a PCB board.
  • the function board 301 has a functional electrical connection layer 311 and a heat dissipation electrical connection layer 312 which are separated from each other.
  • the functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 are spaced apart from each other on the functional surface of the circuit board 301.
  • the solder ball 202 is electrically connected to the functional electrical connection layer 311, and the heat conductive layer 204 is in contact with the heat dissipation electrical connection layer 312.
  • the solder ball 202 realizes electrical connection between the circuit board 301 and the substrate 201 and the chip 203 through the functional electrical connection layer 311.
  • the heat conducting layer 204 is in contact with the heat dissipation electrical connection layer 312
  • heat generated inside the chip 203 is transferred to the heat dissipation electrical connection layer 312 via the heat conduction layer 204, so that the chip 203 is internally generated.
  • the heat can be dissipated via the circuit board 301.
  • the heat dissipation effect of the circuit board 301 is good, so that the heat inside the chip 203 is conducted in time and effectively, and the chip 203 is effectively operated.
  • the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312.
  • the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer is flush with the top of the heat dissipation electrical connection layer to ensure the solder ball
  • the electrical connection layer is electrically connected to the functional electrical connection layer, and the thermal conductive layer is in contact with the heat dissipation electrical connection.
  • the heat conductive layer 204 and the heat dissipation electrical connection layer 312 are bonded to each other.
  • the material of the heat dissipation electrical connection layer 312 is one or more of gold, tungsten or solder paste.
  • the material of the heat dissipation electrical connection layer 312 is solder paste, and the heat conduction layer 204 is in contact with the heat dissipation electrical connection layer 312 by eutectic bonding.
  • the material of the functional electrical connection layer 311 is the same as the material of the heat dissipation electrical connection layer 312. In other embodiments, the material of the functional electrical connection layer may also be different from the material of the heat dissipation electrical connection layer.
  • the circuit board 301 not only has the function of electrically connecting the substrate 201 and the chip 203, but also has the function of generating heat inside the conductive chip 203 to prevent overheating of the chip 203.
  • the package structure has a smaller volume.
  • the embodiment of the present invention further provides a method for forming the above package structure, comprising: providing the foregoing semiconductor structure; providing a circuit board having a functional surface; and disposing the semiconductor structure on the functional surface of the circuit board, so that the soldering The ball is electrically connected to the functional surface of the circuit board, and the thermally conductive layer is in contact with the function of the circuit board.
  • the circuit board can realize the electrical connection with the substrate and the chip, and also can contact the heat conductive layer to timely and effectively transfer the heat generated by the chip, thereby improving the heat dissipation effect of the package structure. And reduce the volume of the package structure.
  • FIG. 7 is a schematic structural diagram of a process of forming a package structure according to an embodiment of the present invention.
  • the semiconductor structure includes a substrate 201 on which a solder ball 202 is disposed, a chip 203 disposed on the substrate 201, and the chip 203 and the solder ball 202 are disposed on the same side of the substrate 201.
  • the chip 203 has opposite first and second faces, the first face being opposite to the substrate 201, and the second face having a heat conductive layer 204.
  • the first surface and the substrate 201 further have a plurality of conductive layers 205 separated from each other.
  • circuit board 301 having a functional surface is provided.
  • the circuit board 301 is a PCB board.
  • the functional surface is a surface that is subsequently bonded to the semiconductor structure.
  • the circuit board 301 has functional electrical connection layers 311 and heat dissipation electrical connection layers 312 separated from each other.
  • the functional electrical connection layer 311 and the heat dissipation electrical connection layer 312 may be formed on the circuit board 301 by a printing process.
  • the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312.
  • the top of the functional electrical connection layer may also be lower than the top of the heat dissipation electrical connection layer, or the top of the functional electrical connection layer may be flush with the top of the heat dissipation electrical connection layer.
  • the material of the heat dissipation electrical connection layer 312 is one or more of tin, gold or tungsten. In this embodiment, the material of the heat dissipation electrical connection layer 312 is tin.
  • the material of the heat dissipation electrical connection layer 312 is the same as the material of the functional electrical connection layer 311.
  • the semiconductor structure is disposed on a functional surface of the circuit board 301 such that the solder ball 202 is electrically connected to a functional surface of the circuit board 301, and the heat conductive layer 204 and the circuit board are The 301 functional surface is in contact.
  • solder ball 202 is bonded to the functional electrical connection layer 311 by a solder bonding process such that the heat conductive layer 204 is bonded to the heat dissipation electrical connection layer 312.
  • the material of the heat dissipation electrical connection layer 312 is a solder paste, and the material of the heat conduction layer 204 is a metal material; the eutectic bonding process is used to make the heat conduction layer 204 and the heat dissipation electrical connection layer 312 Bond.
  • the bonding interface between the heat conducting layer 204 and the heat dissipating electrical connection layer 312 is such that the heat conducting layer 204 and the heat dissipating electrical connection layer 312 are eutectic bonded. Has excellent thermal conductivity.
  • the thermal conductive layer may be bonded to the functional surface of the circuit board by ultrasonic hot pressing, thermocompression bonding or ultrasonic pressure welding, etc., so that the thermal conductive layer and the thermal conductive layer The heat-dissipating electrical connection layers are in contact.
  • the top of the functional electrical connection layer 311 is flush with the top of the heat dissipation electrical connection layer 312, and the top of the solder ball 202 is higher than the top of the thermal conductive layer 204.
  • the thickness of the solder ball 202 may be reduced, so when the solder ball 202 and the function
  • the electrical connection layer 311 is electrically connected, the heat conduction layer 204 and the heat dissipation electrical connection layer 312 can be bonded to each other, that is, the heat conduction layer 204 is in contact with the functional surface of the circuit board 301.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne une structure semiconductrice et son procédé de formation, ainsi qu'une structure d'emballage et son procédé de formation. La structure semiconductrice comprend un substrat (201) et une puce (203). Des billes de soudure (202) sont disposées sur le substrat (201). La puce (203) est disposée sur le substrat (201), et la puce (203) et les billes de soudure (202) sont disposées sur une même surface du substrat (201). La puce (203) comprend une première surface et une seconde surface qui sont opposées l'une à l'autre. La première surface est opposée au substrat (201), et la seconde surface comprend une couche conductrice de chaleur (204). Les effets de dissipation de chaleur de la structure semiconductrice et de la structure d'emballage sont améliorés, et les températures dans et autour de la puce sont empêchées d'être excessivement élevées, ce qui permet d'assurer un fonctionnement fiable et efficace de la puce.
PCT/CN2017/110641 2016-11-24 2017-11-13 Structure semiconductrice et son procédé de formation, et structure d'emballage et son procédé de formation WO2018095233A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201611045346.9A CN106449551B (zh) 2016-11-24 2016-11-24 半导体结构及其形成方法、封装结构及其形成方法
CN201621266619.8 2016-11-24
CN201621266619.8U CN206259339U (zh) 2016-11-24 2016-11-24 半导体结构以及封装结构
CN201611045346.9 2016-11-24

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WO2018095233A1 true WO2018095233A1 (fr) 2018-05-31

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EP3723121A4 (fr) * 2018-01-19 2021-01-06 Huawei Technologies Co., Ltd. Dispositif de conditionnement de tranche
CN114585212A (zh) * 2020-11-30 2022-06-03 华为技术有限公司 散热装置和电子设备

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CN104916602A (zh) * 2015-04-22 2015-09-16 华进半导体封装先导技术研发中心有限公司 用于埋入晶圆级球栅阵列封装的散热结构
CN106449551A (zh) * 2016-11-24 2017-02-22 苏州晶方半导体科技股份有限公司 半导体结构及其形成方法、封装结构及其形成方法
CN206259339U (zh) * 2016-11-24 2017-06-16 苏州晶方半导体科技股份有限公司 半导体结构以及封装结构

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CN104538372A (zh) * 2014-12-29 2015-04-22 华进半导体封装先导技术研发中心有限公司 散热型封装结构及其制作方法、散热型封装基板
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EP3723121A4 (fr) * 2018-01-19 2021-01-06 Huawei Technologies Co., Ltd. Dispositif de conditionnement de tranche
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CN114585212B (zh) * 2020-11-30 2024-05-17 华为技术有限公司 散热装置和电子设备

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