CN104916602A - 用于埋入晶圆级球栅阵列封装的散热结构 - Google Patents

用于埋入晶圆级球栅阵列封装的散热结构 Download PDF

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CN104916602A
CN104916602A CN201510193675.7A CN201510193675A CN104916602A CN 104916602 A CN104916602 A CN 104916602A CN 201510193675 A CN201510193675 A CN 201510193675A CN 104916602 A CN104916602 A CN 104916602A
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heat sink
power chip
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radiator structure
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侯峰泽
林挺宇
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National Center for Advanced Packaging Co Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/93—Batch processes
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    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

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Abstract

本发明公开了一种用于埋入晶圆级球栅阵列封装的散热结构，其包括：内部热沉通过高导热的热界面材料贴装在大功率芯片上表面，所述内部热沉上表面有很多盲孔，大功率芯片和内部热沉通过塑封胶塑封，内部热沉的上表面裸露在封装外表面。所述内部热沉厚度为100~300um，通常采用铜材质。本发明的优点是：针对大功率芯片埋入晶圆级球栅阵列封装，本技术的优势是将带很多盲孔的内部热沉通过高导热的热界面材料粘在大功率芯片的上表面上，带有很多盲孔的内部热沉上表面裸露在外表面。这种散热结构有利于提高大功率芯片的散热能力以及消除可能出现的热点。

Description

用于埋入晶圆级球栅阵列封装的散热结构
技术领域
本发明涉及一种用于埋入晶圆级球栅阵列封装的散热结构，属于微电子封装技术领域。
背景技术
大功率芯片，尤其热流密度达到350W/cm2以上的芯片，以及hotspot（热点）达到10KW/cm2以上的芯片，对于eWLB（embedded wafer level ball grid array，埋入晶圆级球栅阵列）封装，如果不采用有效的散热措施，芯片产生的热量很难从封装内传导出去。
目前，针对大功率芯片eWLB封装的散热，通常将大功率芯片裸露在封装外表面，这种封装的缺点是芯片得不到有效保护。
发明内容
本发明的目的是克服现有技术中存在的不足，为eWLB封装提供一种新的散热结构。
按照本发明提供的技术方案，所述的用于埋入晶圆级球栅阵列封装的散热结构包括：内部热沉（heat slug）通过高导热的热界面材料贴装在大功率芯片的上表面，所述内部热沉上表面有很多盲孔，大功率芯片和内部热沉通过塑封胶封装，内部热沉的上表面裸露在封装外表面。
所述内部热沉厚度优选为100~300um，通常采用铜材质。
所述内部热沉形状可以为圆柱体，圆柱体的底面通过高导热的热界面材料贴装在大功率芯片的上表面，内部热沉的底面位于大功率芯片上表面范围内或超出大功率芯片上表面范围。根据芯片功耗及芯片发热区域，内部热沉的直径可大于或等于大功率芯片的长和宽。
本发明的优点是：针对大功率芯片eWLB封装，本发明将带很多盲孔的内部热沉通过高导热的热界面材料表贴装在大功率芯片上表面，内部热沉上表面裸露在封装体外表面。本发明也适用多芯片eWLB封装的散热，在每个大功率芯片上表面分别通过高导热的热界面材料贴装带很多盲孔的内部热沉。这种散热结构有利于提高大功率芯片的散热能力以及消除可能出现的hotspot。
附图说明
图1为一种用于eWLB封装的散热结构图。
图2为隐藏塑封胶的eWLB封装散热结构的俯视图。
图3为一种用于多芯片eWLB封装的散热结构图。
图4为在晶圆硅载板层压一层临时键合胶。
图5为将大功率芯片粘在晶圆硅载板上。
图6为将带很多盲孔的内部热沉通过高导热的热界面材料粘到大功率芯片上。
图7为将大功率芯片和内部热沉通过塑封胶塑封起来。
图8为将硅载板和临时键合胶从系统中分离出来。
图9为制作钝化层和重新布线层。
图10为植BGA球。
具体实施方式
下面结合附图和实施例对本发明作进一步说明。
本发明公开了一种用于eWLB封装的散热结构100，将一个或若干个带很多盲孔102的内部热沉101通过高导热的热界面材料103贴在大功率芯片104上表面上。图1和图2是单芯片的eWLB散热结构，图3是多芯片的eWLB散热结构。内部热沉101上表面有很多盲孔102，大功率芯片104和内部热沉101通过塑封胶105塑装，内部热沉101的上表面裸露在封装外表面。
本发明也适用于多芯片eWLB封装的散热，如图3所示，在每个大功率芯片104的上表面分别通过高导热的热界面材料103贴装带很多盲孔102的内部热沉101。
如图1所示的eWLB封装，其工艺流程如下：
步骤1，在晶圆硅载板001上层压一层临时键合胶002，如图4所示；
步骤2，将大功率芯片104的背面粘在硅载板001上，大功率芯片104的背面有焊盘109，如图5所示；
步骤3，将带很多盲孔102的内部热沉101通过高导热的热界面材料103粘在大功率芯片104上表面上，如图6所示；
步骤4，大功率芯片104和内部热沉101通过塑封胶105封装，内部热沉101的上表面裸露在封装外表面，如图7所示；
步骤5，将硅载板001和临时键合胶002从系统中分离出来，如图8，硅载板001可以重新利用；
步骤6，将系统倒过来，如图9所示，在大功率芯片104背面和塑封胶105表面制作第一钝化层106、第二钝化层107以及重新布线层108，第一钝化层106和第二钝化层107材料可选BCB（苯并环丁烯）、PI（Polyimide，聚酰亚胺）,重新布线层108材料可选铜；
步骤7，如图10所示，在重新布线层108表面植BGA（Ball Grid Array, 球栅阵列）球110；
步骤8，切单后就成图1所示的结构。
根据不同的芯片厚度、功耗，采用不同厚度的内部热沉101。内部热沉101通常采用铜材质；厚度很薄，大约为100~300um；形状为圆柱体，如图1和图2所示，其底面的直径小于大功率芯片104的长和宽。然而，根据芯片功耗及芯片发热区域，内部热沉的直径可大于或等于大功率芯片104的长和宽。
内部热沉101的上表面裸露在封装外表面，这样不会使整个封装体100很厚。这种散热结构不仅可以有效保护芯片，还可以提高eWLB封装的散热能力以及消除可能出现的hotspot，能使整个封装体芯片的温度分布都比较均匀。

Claims (6)

1.用于埋入晶圆级球栅阵列封装的散热结构，其特征是，包括：内部热沉（101）通过高导热的热界面材料（103）贴装在大功率芯片（104）的上表面，所述内部热沉（101）上表面有很多盲孔（102），大功率芯片（104）和内部热沉（101）通过塑封胶（105）塑封，内部热沉（101）的上表面裸露在封装外表面。
2.如权利要求1所述的用于埋入晶圆级球栅阵列封装的散热结构，其特征是，所述内部热沉（101）厚度为100~300um。
3.如权利要求1所述的用于埋入晶圆级球栅阵列封装的散热结构，其特征是，所述内部热沉（101）形状为圆柱体，圆柱体的底面通过高导热的热界面材料（103）贴装在大功率芯片（104）上表面。
4.如权利要求1所述的用于埋入晶圆级球栅阵列封装的散热结构，其特征是，所述内部热沉（101）采用铜材质。
5.如权利要求1，3所述的用于埋入晶圆级球栅阵列封装的散热结构，其特征是，所述内部热沉（101）的底面位于大功率芯片（104）上表面范围内或超出大功率芯片（104）上表面范围。
6.如权利要求1所述的用于埋入晶圆级球栅阵列封装的散热结构，其特征是，对于多芯片的埋入晶圆级球栅阵列封装，若干个带很多盲孔（102）的内部热沉（101）通过高导热的热界面材料（103）贴装在若干个大功率芯片（104）上表面。
CN201510193675.7A 2015-04-22 2015-04-22 用于埋入晶圆级球栅阵列封装的散热结构 Pending CN104916602A (zh)

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CN107946254A (zh) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 集成散热结构的硅基扇出型封装及晶圆级封装方法
WO2018095233A1 (zh) * 2016-11-24 2018-05-31 苏州晶方半导体科技股份有限公司 半导体结构及其形成方法、封装结构及其形成方法
CN110265306A (zh) * 2019-05-20 2019-09-20 芯原微电子(上海)股份有限公司 一种无芯基板封装结构及其制造方法
CN112864108A (zh) * 2019-11-12 2021-05-28 健策精密工业股份有限公司 散热片
CN117276217A (zh) * 2023-11-21 2023-12-22 江苏中科智芯集成科技有限公司 扇出型封装结构和扇出型封装方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018095233A1 (zh) * 2016-11-24 2018-05-31 苏州晶方半导体科技股份有限公司 半导体结构及其形成方法、封装结构及其形成方法
CN107946254A (zh) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 集成散热结构的硅基扇出型封装及晶圆级封装方法
CN110265306A (zh) * 2019-05-20 2019-09-20 芯原微电子(上海)股份有限公司 一种无芯基板封装结构及其制造方法
CN112864108A (zh) * 2019-11-12 2021-05-28 健策精密工业股份有限公司 散热片
CN112864108B (zh) * 2019-11-12 2024-04-02 健策精密工业股份有限公司 散热片
CN117276217A (zh) * 2023-11-21 2023-12-22 江苏中科智芯集成科技有限公司 扇出型封装结构和扇出型封装方法

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