CN221102064U - Packaging structure - Google Patents
Packaging structure Download PDFInfo
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- CN221102064U CN221102064U CN202322318525.7U CN202322318525U CN221102064U CN 221102064 U CN221102064 U CN 221102064U CN 202322318525 U CN202322318525 U CN 202322318525U CN 221102064 U CN221102064 U CN 221102064U
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- heat dissipation
- chip
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- fixed
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- 238000004806 packaging method and process Methods 0.000 title abstract description 12
- 230000017525 heat dissipation Effects 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 75
- 229910000679 solder Inorganic materials 0.000 claims description 30
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 238000005476 soldering Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 36
- 239000011368 organic material Substances 0.000 description 17
- 239000002184 metal Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 229910052738 indium Inorganic materials 0.000 description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 7
- CNQCVBJFEGMYDW-UHFFFAOYSA-N lawrencium atom Chemical compound [Lr] CNQCVBJFEGMYDW-UHFFFAOYSA-N 0.000 description 7
- 239000007791 liquid phase Substances 0.000 description 7
- 239000003822 epoxy resin Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 229920000647 polyepoxide Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 229910000570 Cupronickel Inorganic materials 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- QRJOYPHTNNOAOJ-UHFFFAOYSA-N copper gold Chemical compound [Cu].[Au] QRJOYPHTNNOAOJ-UHFFFAOYSA-N 0.000 description 3
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000013618 particulate matter Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000000741 silica gel Substances 0.000 description 3
- 229910002027 silica gel Inorganic materials 0.000 description 3
- 239000007790 solid phase Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A package structure, comprising: a substrate including a first face and a second face opposite to each other; the chip comprises a functional surface and a non-functional surface, and the functional surface of the chip is fixed on the surface of the first surface of the substrate; the first radiating fin is positioned on the nonfunctional surface of the chip; the second heat dissipation layer is positioned on the nonfunctional surface of the chip, the second heat dissipation layer surrounds the first heat dissipation plate, the material of the second heat dissipation layer is different from that of the first heat dissipation plate, an exhaust port is arranged in the second heat dissipation layer, and the exhaust port is communicated with the first heat dissipation plate and the area outside the chip; the heat dissipation cover is fixed with the first surface of the substrate and comprises a first part and a second part, the first part is fixed with the top surfaces of the first heat dissipation sheet and the second heat dissipation layer, the second part is perpendicular to the first part, the second part is fixed with the first surface of the substrate, and the second part surrounds the chip; the passive element is fixed on the first surface of the substrate and is positioned between the second part of the heat radiating cover and the chip. The yield of the packaging structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor packaging, and particularly to a packaging structure.
Background
The flip chip ball grid array package is suitable for high-density pin count and high-performance chip package, and is mainly applied to microprocessors, image processors, network servers, high-capacity storage devices and the like. The main packaging structure is that micro-bumps arranged in a certain array are formed on the surface of a chip through rewiring and electroplating processes, interconnection between the micro-bumps and an organic substrate is realized through a flip chip technology, and heat conduction between the thermal interface material and a metal heat dissipation cover is realized through coating of a thermal interface material on the back of the chip.
The thermal interface is typically selected from the group consisting of organic heat-dissipating glue and metallic heat-dissipating materials. The metal heat dissipation material is applied to device packaging with high performance and high heat dissipation requirement, and the material is usually selected from indium, wherein the heat conductivity of the indium is 82W/(m.times.k), and the metal heat dissipation material has good heat conduction performance.
However, the existing chip packaging process has yet to be improved.
Disclosure of utility model
The utility model solves the technical problem of providing a packaging structure for improving the existing chip packaging process.
In order to solve the above technical problems, the present utility model provides a packaging structure, including: a substrate comprising opposing first and second faces; the chip comprises a functional surface and a non-functional surface, and the functional surface of the chip is fixed on the surface of the first surface of the substrate; the first radiating fin is positioned on the nonfunctional surface of the chip; the second heat dissipation layer is positioned on the nonfunctional surface of the chip, the second heat dissipation layer surrounds the first heat dissipation sheet, the material of the second heat dissipation layer is different from that of the first heat dissipation sheet, an exhaust port is arranged in the second heat dissipation layer, and the exhaust port is communicated with the first heat dissipation sheet and the area outside the chip; the heat dissipation cover is fixed with the first surface of the substrate and comprises a first part and a second part, the first part is fixed with the top surfaces of the first heat dissipation sheet and the second heat dissipation layer, the second part is perpendicular to the first part, the second part is fixed with the first surface of the substrate, and the second part surrounds the chip; the passive element is fixed on the first surface of the substrate and is positioned between the second part of the heat radiating cover and the chip.
Optionally, the first cooling fin is fixed with the cooling cover in a welding manner; the material of the first heat sink comprises a metal comprising one or more of tin, indium, tin-lead alloy solder, antimony-added solder, cadmium-added solder, silver-added solder, and copper-added solder.
Optionally, the second heat dissipation layer is fixed with the heat dissipation cover by bonding; the material of the second heat dissipation layer includes an organic material including: epoxy, silica gel, or organic material with particulate matter added, including alumina particles.
Optionally, the second portion is fixed to the first surface of the substrate by a first adhesive layer.
Optionally, the material of the first adhesive layer includes an organic material, and the organic material includes an epoxy resin.
Optionally, the chip nonfunctional surface includes a first region and a second region surrounding the first region; the first radiating fin is attached to the surface of the first area, and the second radiating layer is formed on the surface of the second area.
Optionally, the passive element includes: inductance, capacitance, or resistance.
Optionally, the material of the heat dissipating cover includes a metal, and the metal includes: bare copper, copper nickel plating or copper gold plating.
Optionally, the method further comprises: and the second solder ball is positioned on the surface of the second surface of the substrate and is electrically connected with the chip of the first surface.
Optionally, the method further comprises: a filling layer positioned between the chip and the first surface of the substrate and on the surface of a part of the side wall of the chip; the material of the filling layer comprises an organic material, and the organic material comprises epoxy resin.
Compared with the prior art, the technical scheme of the utility model has the following beneficial effects:
According to the packaging structure of the technical scheme, as the second heat dissipation layer is distributed around the first heat dissipation plate, the second heat dissipation layer can prevent the first heat dissipation plate from splashing in a liquid phase state in a vacuum reflow process, so that the packaging yield is improved; meanwhile, the second heat dissipation layer has good filling capacity, so that the coverage rate of the heat dissipation material formed on the nonfunctional surface of the chip is guaranteed, and the heat dissipation capacity is improved.
Drawings
FIG. 1 is a schematic diagram of a package structure in an embodiment;
Fig. 2 to 6 are schematic structural views illustrating a process of forming a package structure according to an embodiment of the utility model.
Detailed Description
As described in the background, the existing chip packaging process is still to be improved. The analysis will now be described with reference to specific examples.
FIG. 1 is a schematic diagram of a package structure according to an embodiment.
Referring to fig. 1, the package structure includes: a substrate 100, the substrate 100 comprising opposing first and second faces; a chip 101 fixed on the first surface of the substrate 100, where the chip 101 is fixed to the first surface of the substrate 100 through a first connection layer 102; a heat sink 107 located on the top surface of the chip 101; a heat dissipation cover 108 fixed to the first surface of the substrate 100, wherein the heat dissipation cover 108 is further attached to the heat dissipation sheet 107, and the heat dissipation cover 108 is fixed to the first surface of the substrate 100 by an adhesive layer 109; the passive element 103 fixed on the first surface of the substrate 100, wherein the passive element 103 is located between the side wall of the heat dissipation cover 108 and the chip, and the passive element 103 is fixed with the first surface of the substrate 100 through the second connection layer 104; a shielding structure 106 disposed on the passive element 103, where the shielding structure 106 is fixed to the first surface of the substrate 100; a filling layer 105 filled between the chip 101 and the substrate 100 and between the passive element 103 and the substrate 100.
In the process of forming the package structure, after the chip 101 and the passive component 103 are fixed on the first surface of the substrate 100, a heat sink 107 is attached to the top surface of the chip 101, then a heat sink cover 108 is attached to the heat sink 107, and finally vacuum reflow is performed to weld the heat sink 107 and the chip 101 together, so that the heat sink cover 108 and the heat sink 107 are welded together. The material of the heat sink 107 includes indium metal, and during the vacuum reflow process, the material of the heat sink 107 may undergo a process of changing from solid phase to liquid phase and then to solid phase, and when the material of the heat sink 107 changes to liquid phase, the material may be easily splashed to damage the passive element 103. Meanwhile, the bonding between the heat sink 107 and the chip 101 needs to meet the coverage requirement of the surface of the chip 101, that is, the larger the coverage area of the heat sink 107 on the surface of the chip 101 is, the better. The requirement of the bonding coverage rate of the heat sink 107 and the chip 101 is met, and the problem that the material of the heat sink 107 cannot overflow and splash outwards in the liquid phase is also met, so that the process operation difficulty is high, and the passive element 103 is often required to be protected by an auxiliary shielding structure 106. This increases the introduction of new materials and new processes, and increases the length of the process flow and the cost of processing.
In order to solve the above problems, the technical solution of the present utility model provides a packaging structure, in which the second heat dissipation layer is distributed around the first heat dissipation sheet, so that the second heat dissipation layer can block splashing of the first heat dissipation sheet in a liquid phase state during a vacuum reflow process, and meanwhile, the second heat dissipation layer has a better filling capability, so that coverage rate of heat dissipation materials formed on a nonfunctional surface of a chip is also ensured, and heat dissipation capability is improved.
In order to make the above objects, features and advantages of the present utility model more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 6 are schematic structural views illustrating a process of forming a package structure according to an embodiment of the utility model.
Referring to fig. 2, a substrate 200 is provided, and the substrate 200 includes a first surface and a second surface opposite to each other.
The materials of the substrate 200 include: a mixed material of glass fiber cloth and resin.
The substrate 200 has a plurality of layers of copper metal wiring, an organic insulating material is arranged between the layers of copper metal wiring, and an organic photoresist material is also arranged on the surface of the substrate 200.
With continued reference to fig. 2, a chip 201 is provided, the chip 201 includes a functional surface and a non-functional surface, and the non-functional surface of the chip 201 includes a first region and a second region surrounding the first region; the functional surface of the chip 201 is fixed to the first surface of the substrate 200.
In this embodiment, the chip 201 is fixed to the first surface of the substrate 200 by the first solder balls 202, and the functional surface of the chip 201 is electrically connected to the circuit in the substrate 200.
The process of fixing the chip 201 to the substrate 200 includes flip-chip bonding with micro bumps, and the bonding method includes reflow soldering or thermocompression bonding.
With continued reference to fig. 2, a passive component 203 is provided, and the passive component 203 is fixed on the first surface of the substrate 200.
The passive element 203 includes: inductance, capacitance, or resistance.
In this embodiment, the passive component 203 is fixed to the substrate 200 by a solder layer 204.
The method for fixing the passive component 203 to the substrate 200 includes: coating a welding layer 204 on the surface of the substrate 200; the passive component 203 is attached to the solder layer 204, so that the passive component 203 is fixed to the substrate 200 through the solder layer 204.
With continued reference to fig. 2, a fill layer 205 is formed between the chip 201 and the first side of the substrate 200 and on a portion of the sidewall surface of the chip 201.
The filler layer 205 is used to protect the strength of the first solder ball 202.
The material of the filling layer 205 includes an organic material including an epoxy resin.
Referring to fig. 3 and 4, fig. 4 is a top view of fig. 3, fig. 3 is a cross-sectional view of fig. 4 taken perpendicular to the surface of chip 201, and a first heat sink 207 is provided.
The first heat sink 207 is used for dissipating heat from the chip 201.
The material of the first heat sink 207 comprises a metal including one or more of tin, indium, tin-lead alloy solder, antimony-added solder, cadmium-added solder, silver-added solder, and copper-added solder.
In this embodiment, the material of the first heat sink 207 includes indium.
With continued reference to fig. 3 and 4, a first heat sink 207 is attached to the surface of the first area of the chip 201, and the area of the first heat sink 207 is smaller than the area of the top surface of the chip 201.
The method for attaching the first heat sink 207 to the first area surface of the chip 201 includes: spraying a first soldering flux on the surface of the first area of the chip 201; the first heat sink 207 is attached to the first zone surface.
The first flux is used to enable the first heat sink 207 and the chip 201 to be tightly soldered together during a subsequent vacuum reflow process.
The material of the first heat sink 207 comprises a metal including one or more of tin, tin-lead alloy solder, antimony-added solder, cadmium-added solder, silver-added solder, and copper-added solder.
With continued reference to fig. 3 and 4, an initial second heat spreader 208 is formed on the surface of the second region of the chip 201 surrounding the first heat spreader 207.
Before forming the initial second heat dissipation layer 208 on the surface of the second region of the chip 201 around the first heat dissipation sheet 207, it further includes: a second flux is sprayed on the top surface of the first heat sink 207. The second flux is used to enable the first heat sink 207 and heat sink cap to be tightly soldered together later in the vacuum reflow process.
The material of the initial second heat dissipation layer 208 includes an organic material including: epoxy, silica gel, or organic material with particulate matter added, including alumina particles.
In this embodiment, the height of the initial second heat dissipation layer 208 is greater than the height of the first heat dissipation fins 207. So as to ensure that the material of the initial second heat dissipation layer 208 can be bonded to the heat dissipation cap during a lamination process, when the initial second heat dissipation layer 208 is pre-cured later.
The process of forming the initial second heat spreader layer 208 includes a dispensing process.
Referring to fig. 5 and 6, fig. 6 is a top view of fig. 5, fig. 5 is a cross-sectional view of fig. 6 along a direction perpendicular to a surface of a chip 201, a heat dissipation cover 209 is provided, and the heat dissipation cover 209 is attached to top surfaces of the first heat dissipation sheet 207 and the initial second heat dissipation layer 208, so that the initial second heat dissipation layer 208 is formed as a second heat dissipation layer 211, and the heat dissipation cover 209 is fixed to top surfaces of the first heat dissipation sheet 207 and the second heat dissipation layer 211.
In this embodiment, the first heat sink 207 is fixed to the heat sink 209 by welding, and the second heat sink 211 is fixed to the heat sink 209 by bonding.
The material of the heat dissipating cover 209 comprises a metal including: bare copper, copper nickel plating or copper gold plating.
In this embodiment, the heat dissipating cover 209 includes a first portion and a second portion, the first portion is located on top surfaces of the first heat sink 207 and the second heat dissipating layer 211, the second portion is perpendicular to the first portion, and the second portion is fixed to the first surface of the substrate 200, and the second portion surrounds the chip 201.
In this embodiment, the passive element 203 is located between the second portion and the chip 201.
In this embodiment, the second portion is fixed to the first surface of the substrate 200 by a first adhesive layer 210. The material of the first adhesive layer 210 includes an organic material including an epoxy resin.
The method for fixing the heat dissipating cover 209 to the top surfaces of the first heat dissipating sheet 207 and the second heat dissipating sheet 211 includes: pressing the heat dissipation cover 209 on the first heat dissipation sheet 207 and the initial second heat dissipation layer 208, and performing pressing pre-curing to fill the material of the initial second heat dissipation layer 208 on the surface of the second area of the chip 201 around the first heat dissipation sheet; the initial second heat dissipation layer 208 is cured to form a second heat dissipation layer 211, so that the heat dissipation cover 209 is adhered and fixed to the top surfaces of the first heat dissipation plate 207 and the second heat dissipation layer 211.
In this embodiment, the method for pressing and pre-curing includes: the heat sink cap 209 is pressed with the first heat sink 207 and the initial second heat sink layer 208 at a fixed pressure and for a fixed time. So that the material of the initial second heat dissipation layer 208 fills the second area of the chip 201, and a certain adhesion force is provided between the initial second heat dissipation layer 208 and the heat dissipation cover 209, so that a stronger adhesion force can be provided between the heat dissipation cover 209 and the second heat dissipation layer 211 when the subsequent curing is performed.
The press-fit pre-curing ensures that the heat dissipating cover 209 forms a bond with both the first heat sink 207 and the initial second heat sink layer 208, and allows the initial second heat sink layer 208 to fill the space of the second area of the chip and allow for a certain overflow.
In this embodiment, the method for curing the initial second heat dissipation layer 208 includes: and (3) high-temperature curing, wherein the technological parameters of the high-temperature curing comprise: the temperature is 110-140 ℃ and the time is 2-4 hours.
The curing process allows the second heat dissipation layer 211 to be formed with sufficient supporting strength.
In this embodiment, the second heat dissipation layer 211 has an air vent (shown in a region a in fig. 6) therein, and the air vent communicates the first heat dissipation plate 207 with a region outside the chip 201. To meet the requirement of exhausting gas when the first heat sink 207 is changed into a liquid phase and then into a solid phase in the subsequent vacuum reflow process, and to avoid forming a closed cavity on the chip 201, so as to avoid the condition of causing explosion of the board in the subsequent vacuum reflow process. In this embodiment, the specific position of the air outlet may be at a corner position.
In this embodiment, after curing the initial second heat dissipation layer 208, the method further includes: the vacuum reflow process makes the bonding and welding of the heat sink cover 209 and the first heat sink 207 sufficient.
The vacuum reflow process is a process under a variable temperature vacuum environment, and the variable temperature process is a process that the temperature is reduced after the temperature is increased to the melting point temperature of the first heat sink 207, so that the physical state of the first heat sink 207 is converted from a solid state to a liquid state for leveling, and then is converted from a liquid state to a solid state, and in this process, the non-functional surfaces of the first heat sink 207 and the chip 201 and the heat sink cover 209 can be tightly welded together.
With continued reference to fig. 5 and 6, after the heat dissipating cover 209 is fixed to the top surfaces of the first heat dissipating fins 207 and the second heat dissipating layer 211, the method further includes: second solder balls 212 are formed on the second surface of the substrate 200, and the second solder balls 212 are used to electrically connect the chip 201 with an external circuit.
In the packaging process, the second heat dissipation layer 211 is distributed around the first heat dissipation plate 207, so that in the vacuum reflow process, the second heat dissipation layer 211 can prevent the first heat dissipation plate 207 from splashing in a liquid phase state, and meanwhile, the second heat dissipation layer 211 has a better filling capability, so that the coverage rate of heat dissipation materials formed on the nonfunctional surface of the chip 201 is also ensured, and the heat dissipation capability is improved.
Accordingly, an embodiment of the present utility model further provides a package structure, please continue to refer to fig. 5 and fig. 6, including:
a substrate 200, the substrate 200 comprising opposing first and second faces;
A chip 201, wherein the chip 201 comprises a functional surface and a non-functional surface, and the functional surface of the chip 201 is fixed on the first surface of the substrate;
A first heat sink 207 located on the non-functional side of the chip 201;
A second heat dissipation layer 211 located on the non-functional surface of the chip 201, the second heat dissipation layer 211 surrounding the first heat dissipation plate 207, the material of the second heat dissipation layer 211 being different from the material of the first heat dissipation plate 207;
A heat dissipation cover 209 fixed to the first surface of the substrate 200, the heat dissipation cover 209 being further fixed to top surfaces of the first heat dissipation sheet 207 and the second heat dissipation layer 211;
The passive component 203 is fixed on the first surface of the substrate 200, and the passive component 203 is located between the heat dissipating cover 209 and the chip 201.
In this embodiment, the material of the first heat sink 207 includes a metal including one or more of tin, indium, tin-lead alloy solder, antimony-added solder, cadmium-added solder, silver-added solder, and copper-added solder.
In this embodiment, the material of the second heat dissipation layer 211 includes an organic material, and the organic material includes: epoxy, silica gel, or organic material with particulate matter added, including alumina particles.
In this embodiment, the heat dissipating cover 209 includes a first portion and a second portion, the first portion is located on top surfaces of the first heat sink 207 and the second heat dissipating layer 211, the second portion is perpendicular to the first portion, and the second portion is fixed to the first surface of the substrate 200, and the second portion surrounds the chip 201; the passive element 203 is located between the second portion and the chip 201.
In this embodiment, the second portion is fixed to the first surface of the substrate 200 by a first adhesive layer 210.
In this embodiment, the material of the first adhesive layer 210 includes an organic material, and the organic material includes an epoxy resin.
In this embodiment, the non-functional surface of the chip 201 includes a first region and a second region surrounding the first region; the first heat sink 207 is attached to the first area surface, and the second heat sink layer 211 is formed on the second area surface.
In this embodiment, the passive element 203 includes: inductance, capacitance, or resistance.
In this embodiment, the chip 201 is fixed to the first surface of the substrate 200 by the first solder balls 202.
In this embodiment, further comprising: and a filler layer 205 located between the chip 201 and the first side of the substrate 200 and on a portion of the sidewall surface of the chip.
In this embodiment, the material of the filling layer 205 includes an organic material, and the organic material includes an epoxy resin.
In this embodiment, the material of the heat dissipating cover 209 includes a metal, and the metal includes: bare copper, copper nickel plating or copper gold plating.
Although the present utility model is disclosed above, the present utility model is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the utility model, and the scope of the utility model should be assessed accordingly to that of the appended claims.
Claims (8)
1. A package structure, comprising:
A substrate comprising opposing first and second faces;
The chip comprises a functional surface and a non-functional surface, and the functional surface of the chip is fixed on the surface of the first surface of the substrate;
the first radiating fin is positioned on the nonfunctional surface of the chip;
The second heat dissipation layer is positioned on the nonfunctional surface of the chip, the second heat dissipation layer surrounds the first heat dissipation sheet, the material of the second heat dissipation layer is different from that of the first heat dissipation sheet, an exhaust port is arranged in the second heat dissipation layer, and the exhaust port is communicated with the first heat dissipation sheet and the area outside the chip;
The heat dissipation cover is fixed with the first surface of the substrate and comprises a first part and a second part, the first part is fixed with the top surfaces of the first heat dissipation sheet and the second heat dissipation layer, the second part is perpendicular to the first part, the second part is fixed with the first surface of the substrate, and the second part surrounds the chip;
The passive element is fixed on the first surface of the substrate and is positioned between the second part of the heat radiating cover and the chip.
2. The package structure of claim 1, wherein the first heat sink is fixed to the heat sink cap by soldering.
3. The package structure of claim 1, wherein the second heat spreader layer is attached to the heat spreader lid by bonding.
4. The package structure of claim 1, wherein the second portion is secured to the first side of the substrate by a first adhesive layer.
5. The package structure of claim 1, wherein the chip nonfunctional surface comprises a first region and a second region surrounding the first region; the first radiating fin is attached to the surface of the first area, and the second radiating layer is formed on the surface of the second area.
6. The package structure of claim 1, wherein the passive element comprises: inductance, capacitance, or resistance.
7. The package structure of claim 1, further comprising: and the second solder ball is positioned on the surface of the second surface of the substrate and is electrically connected with the chip of the first surface.
8. The package structure of claim 1, further comprising: and the filling layer is positioned between the chip and the first surface of the substrate and on the surface of the side wall of the chip part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322318525.7U CN221102064U (en) | 2023-08-28 | 2023-08-28 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322318525.7U CN221102064U (en) | 2023-08-28 | 2023-08-28 | Packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221102064U true CN221102064U (en) | 2024-06-07 |
Family
ID=91304040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322318525.7U Active CN221102064U (en) | 2023-08-28 | 2023-08-28 | Packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221102064U (en) |
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2023
- 2023-08-28 CN CN202322318525.7U patent/CN221102064U/en active Active
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