JP2007281043A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2007281043A
JP2007281043A JP2006102610A JP2006102610A JP2007281043A JP 2007281043 A JP2007281043 A JP 2007281043A JP 2006102610 A JP2006102610 A JP 2006102610A JP 2006102610 A JP2006102610 A JP 2006102610A JP 2007281043 A JP2007281043 A JP 2007281043A
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semiconductor device
heat
semiconductor
semiconductor element
substrate
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Kenji Ueda
賢治 植田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with which stable operation is expected without malfunction of a semiconductor device with low temperature assurance, even if a semiconductor device with high temperature assurance and the semiconductor device with low temperature assurance are stacked. <P>SOLUTION: A thermal conductor 8 is provided in a region except a mounting part of a semiconductor element 1b packaged on a surface of a substrate 3b of a semiconductor device 102 mounted on the uppermost stage among a plurality of stacked stages, and a heat sink 10 is thermally coupled to the substrate 3b via the thermal conductor 8 to dissipate heat. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、複数のチップを用いた半導体装置である積層型半導体装置に関する。   The present invention relates to a stacked semiconductor device that is a semiconductor device using a plurality of chips.

携帯情報機器等の小型、軽量化に伴って、半導体装置パッケージの高密度化、小型化、薄型化が要求されている。これらの要求に応えるために、半導体装置を重ねて多段に搭載した積層型の半導体装置が開発されている。   As portable information devices and the like become smaller and lighter, semiconductor device packages are required to have higher density, smaller size, and thinner thickness. In order to meet these demands, a stacked semiconductor device in which semiconductor devices are stacked in multiple stages has been developed.

さらに、半導体装置の微細プロセス化に伴なうトランジスタ数の増加や半導体素子を高密度で配置することより、半導体素子から発生する熱が半導体装置内に滞留し半導体素子の誤動作が発生やすくなっている。この問題を解消し、半導体素子の安定動作を目的とした放熱構造が提案されている。   Furthermore, the increase in the number of transistors accompanying the miniaturization of semiconductor devices and the high density arrangement of semiconductor elements make it easier for heat generated from the semiconductor elements to stay in the semiconductor device and cause malfunctions of the semiconductor elements. Yes. There has been proposed a heat dissipation structure that solves this problem and aims at stable operation of a semiconductor element.

図５は従来の積層型半導体装置を示す。
従来の積層型半導体装置では、各々の半導体素子２０１，２０３から発生する熱は、モジュール基板２０２，２０４、はんだボール２０６などを介して、マザー基板２０５へと熱を伝達させて放熱している。２０７は放熱用ビア、２０８は熱伝導材である。
特開２０００−１２７６５公報（図１） FIG. 5 shows a conventional stacked semiconductor device.
In the conventional stacked semiconductor device, heat generated from each of the semiconductor elements 201 and 203 is dissipated by transferring heat to the mother substrate 205 via the module substrates 202 and 204, the solder balls 206, and the like. 207 is a heat radiating via, and 208 is a heat conducting material.
Japanese Patent Laid-Open No. 2000-12765 (FIG. 1)

しかしながら、従来の積層した半導体装置では、積層した半導体装置全体に熱が伝わるため、積層した半導体装置の中で、ひとつでも熱の保証温度が低い半導体素子が含まれていると、均一に伝わった半導体装置の熱で、保証温度の低い半導体素子が正常に動作しなくなる。   However, in the conventional stacked semiconductor device, heat is transmitted to the entire stacked semiconductor device. Therefore, even if one of the stacked semiconductor devices includes a semiconductor element having a low guaranteed temperature of heat, it is transmitted uniformly. Due to the heat of the semiconductor device, a semiconductor element having a low guaranteed temperature does not operate normally.

本発明は、前記課題を解決するもので、温度保証が高い半導体装置と温度保証が低い半導体装置を積層させた状態においても、温度保証が低い半導体装置が熱による誤動作を起こさず、安定した動作を期待できる半導体装置を提供することを目的とする。   The present invention solves the above-described problem, and even in a state where a semiconductor device with a high temperature guarantee and a semiconductor device with a low temperature guarantee are stacked, the semiconductor device with a low temperature guarantee does not cause malfunction due to heat and operates stably. An object of the present invention is to provide a semiconductor device that can be expected.

本発明の請求項１記載の半導体装置は、基板の表面側に半導体素子を実装した半導体装置を二つ以上の複数段積層した半導体装置であって、前記複数段積層した最上段に搭載した半導体装置の基板の表面に実装された半導体素子の搭載部を除外した領域に熱伝導体を設け、この熱伝導体を介して放熱体を前記基板に熱結合したことを特徴とする。   The semiconductor device according to claim 1 of the present invention is a semiconductor device in which a semiconductor device having a semiconductor element mounted on the surface side of a substrate is stacked in two or more stages, and is mounted on the uppermost stage in which the plurality of stages are stacked. A heat conductor is provided in a region excluding the mounting portion of the semiconductor element mounted on the surface of the substrate of the apparatus, and a heat radiator is thermally coupled to the substrate via the heat conductor.

本発明の請求項２記載の半導体装置は、請求項１において、前記放熱体と前記半導体素子の表面との間に熱伝導を抑制する断熱層または空気層を設けたことを特徴とする。
本発明の請求項３記載の半導体装置は、請求項１において、前記放熱体と前記半導体素子の表面とが熱伝導を抑制する断熱層を介して接触していることを特徴とする。 According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a heat insulating layer or an air layer for suppressing heat conduction is provided between the heat radiator and the surface of the semiconductor element.
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the heat radiator and the surface of the semiconductor element are in contact with each other through a heat insulating layer that suppresses heat conduction.

本発明の請求項４記載の半導体装置は、基板の表面側に半導体素子を実装した半導体装置を二つ以上の複数段積層した半導体装置であって、最上部に搭載された半導体装置よりも下層に搭載される第１の半導体装置に発熱する第１の半導体素子を実装し、前記第１の半導体素子の直上に搭載される第２の半導体装置の基板の裏面に形成した伝熱用パッドと前記第１の半導体素子とを伝熱層を介して接触させるとともに、前記第１の半導体素子の直上に搭載する第２の半導体装置の基板の裏面に形成した前記伝熱用パッドでない領域で、かつ前記基板と前記伝熱層との間に断熱層を形成したことを特徴とする。   The semiconductor device according to claim 4 of the present invention is a semiconductor device in which a semiconductor device having a semiconductor element mounted on the surface side of a substrate is laminated in two or more stages, and is lower than the semiconductor device mounted on the uppermost part. A heat transfer pad formed on the back surface of the substrate of the second semiconductor device mounted on the first semiconductor element mounted on the first semiconductor device mounted on the first semiconductor device; In a region that is not in contact with the first semiconductor element via the heat transfer layer and that is not the heat transfer pad formed on the back surface of the substrate of the second semiconductor device mounted immediately above the first semiconductor element, In addition, a heat insulating layer is formed between the substrate and the heat transfer layer.

本発明の請求項５記載の半導体装置は、請求項２または請求項３において、最上段に形成した半導体装置よりも下段に搭載した半導体装置の方が、動作時の半導体装置表面の温度が高くなることを特徴とする。   According to a fifth aspect of the present invention, in the semiconductor device according to the second or third aspect, the temperature of the semiconductor device surface during operation is higher in the semiconductor device mounted in the lower stage than in the semiconductor device formed in the uppermost stage. It is characterized by becoming.

本発明の半導体装置は、保証温度の異なる半導体装置を積層させた場合においても、保証温度の低い半導体素子には他の半導体装置からの熱が伝わらないとすることができ、安定した半導体素子の動作を得ることができる。   The semiconductor device of the present invention can prevent heat from other semiconductor devices from being transferred to a semiconductor element having a low guaranteed temperature even when semiconductor devices having different guaranteed temperatures are stacked. You can get action.

以下、本発明の各実施の形態を図１〜図４に基づいて説明する。
（実施の形態１）
図１は本発明の実施の形態１の積層型半導体装置を示している。 Embodiments of the present invention will be described below with reference to FIGS.
(Embodiment 1)
FIG. 1 shows a stacked semiconductor device according to a first embodiment of the present invention.

第１の半導体装置１０１は、保証温度の低い半導体素子１ａが、Ａｕバンプやはんだなどの突起電極２ａを用いてフリップチップ方式にて第１のモジュール基板３ａに実装されている。この第１のモジュール基板３ａの裏面には、はんだボール４ａが設けられており、このはんだボール４ａを用いてマザー基板１２と接合されている。   In the first semiconductor device 101, a semiconductor element 1a having a low guaranteed temperature is mounted on the first module substrate 3a by a flip chip method using a protruding electrode 2a such as an Au bump or solder. Solder balls 4a are provided on the back surface of the first module substrate 3a, and are joined to the mother substrate 12 using the solder balls 4a.

さらに、第１のモジュール基板３ａの上面に形成された電極６ａは、第１のモジュール基板３ａの下面に形成されたはんだボール４ａと貫通ビア５ａを介して接続されている。保証温度の低い半導体素子１ａから発生する熱は、Ａｕバンプやはんだなどの突起電極２ａを介し、第１のモジュール基板３ａ，貫通ビア５ａ、はんだボール４ａ、マザー基板１２へという伝熱経路にて放熱される。   Furthermore, the electrode 6a formed on the upper surface of the first module substrate 3a is connected to the solder ball 4a formed on the lower surface of the first module substrate 3a via the through via 5a. The heat generated from the semiconductor element 1a having a low guaranteed temperature is transmitted through a protruding electrode 2a such as an Au bump or solder through a heat transfer path to the first module substrate 3a, the through via 5a, the solder ball 4a, and the mother substrate 12. Heat is dissipated.

第２の半導体装置１０２は、発熱量の大きい半導体素子１ｂが、Ａｕバンプやはんだなど突起電極２ｂを用いてフリップチップ方式にて第２のモジュール基板３ｂに実装されている。この第２のモジュール基板３ｂの裏面には、はんだボール４ｂが設けられており、このはんだボール４ｂを用いて第１の半導体装置１０１の電極６ａと接合されている。   In the second semiconductor device 102, a semiconductor element 1b having a large calorific value is mounted on the second module substrate 3b by a flip chip method using protruding electrodes 2b such as Au bumps and solder. Solder balls 4b are provided on the back surface of the second module substrate 3b, and are joined to the electrodes 6a of the first semiconductor device 101 using the solder balls 4b.

さらに第２の半導体装置１０２の上面の電極６ｂには、熱伝導ならびに放熱性が良好な放熱体としての金属板１０が、絶縁材で出来た熱伝導度の良い伝熱ボール８を熱伝導体として用いて接合されている。この伝熱ボール８は半導体素子１ｂの搭載部を除外した領域に設けられている。金属板１０は、伝導度の良い伝熱材１１を介して半導体素子１ｂに熱結合されており、半導体素子１ｂから発熱する熱量を金属板１０から放熱する。また、熱の一部は金属板１０から伝熱ボール８へと伝わり、電極６ｂと貫通ビア５ｂを介してはんだボール４ｂなどへと伝わり、さらに第１の半導体装置１０１からマザー基板１２と接続しているはんだボール４ａへと熱が伝わることで、マザー基板１２へ放熱する伝熱経路も有している。   Further, the electrode 6b on the upper surface of the second semiconductor device 102 is provided with a metal plate 10 as a heat radiating member having good heat conduction and heat radiating properties, and a heat transfer ball 8 made of an insulating material and having good heat conductivity. Used as a joint. The heat transfer ball 8 is provided in a region excluding the mounting portion of the semiconductor element 1b. The metal plate 10 is thermally coupled to the semiconductor element 1b via a heat transfer material 11 having good conductivity, and radiates heat generated from the semiconductor element 1b from the metal plate 10. Further, part of the heat is transferred from the metal plate 10 to the heat transfer ball 8, transferred to the solder ball 4 b through the electrode 6 b and the through via 5 b, and further connected to the mother substrate 12 from the first semiconductor device 101. A heat transfer path for radiating heat to the mother board 12 is also provided by transferring heat to the solder balls 4a.

このとき、保証温度の低い半導体素子１ａの裏面には、第２の半導体素子１ｂの熱が伝わらないように断熱材７が設けられている。第２のモジュール基板３ｂの裏面及び内層には、伝熱用パッドとしての金属パターン９などで第２の半導体装置１０２のはんだボール４ｂの電極へと熱が伝わる構造をとることが望ましい。   At this time, the heat insulating material 7 is provided on the back surface of the semiconductor element 1a having a low guaranteed temperature so that the heat of the second semiconductor element 1b is not transmitted. It is desirable that the back surface and the inner layer of the second module substrate 3b have a structure in which heat is transmitted to the electrodes of the solder balls 4b of the second semiconductor device 102 by a metal pattern 9 or the like as a heat transfer pad.

なお、図１は２段積層の積層型半導体装置の放熱構造であるが、これに限らず、３段以上に半導体装置を積層した積層型半導体装置についても同様に放熱構造をとることが可能である。   Note that FIG. 1 shows a heat dissipation structure of a two-layer stacked semiconductor device. However, the present invention is not limited to this, and a heat dissipation structure can be similarly applied to a stacked semiconductor device in which semiconductor devices are stacked in three or more stages. is there.

（実施の形態２）
図２は本発明の実施の形態２の積層型半導体装置を示している。
実施の形態１では保証温度の低い半導体素子１ａが第１層目の第１の半導体装置１０１に実装されており、第２層目の第２の半導体装置１０２に発熱量の大きい半導体素子１ｂが実装されていたが、この実施の形態２では、発熱量の大きい半導体素子１ｂが第１層目の第１の半導体装置１０３に実装され、保証温度の低い半導体素子１ａが第２層目の第２の半導体装置１０４に実装されている点が異なっている。 (Embodiment 2)
FIG. 2 shows a stacked semiconductor device according to the second embodiment of the present invention.
In the first embodiment, the semiconductor element 1a having a low guaranteed temperature is mounted on the first semiconductor device 101 of the first layer, and the semiconductor element 1b having a large calorific value is formed on the second semiconductor device 102 of the second layer. In the second embodiment, the semiconductor element 1b having a large calorific value is mounted on the first semiconductor device 103 in the first layer, and the semiconductor element 1a having a low guaranteed temperature is the second layer in the second layer. The difference is that it is mounted on the second semiconductor device 104.

さらに、第２層目の第２の半導体装置１０４の電極６ｂには、熱伝導ならびに放熱性が良い金属板１０が、絶縁材で出来た熱伝導度の良い伝熱ボール８を用いて接合されている。金属板１０と保証温度の低い半導体素子１ａとの間には、断熱材７ｂが設けられており、第１の半導体装置１０３から金属板１０へと伝わった熱が保証温度の低い半導体素子１ａへ伝わらないように構成されている。またこの断熱材７ｂは、空気層としても有効である。   Further, the metal plate 10 having good heat conduction and heat dissipation is bonded to the electrode 6b of the second semiconductor device 104 of the second layer using a heat transfer ball 8 made of an insulating material and having good heat conductivity. ing. A heat insulating material 7b is provided between the metal plate 10 and the semiconductor element 1a having a low guaranteed temperature, and heat transmitted from the first semiconductor device 103 to the metal plate 10 is transferred to the semiconductor element 1a having a low guaranteed temperature. It is configured not to be transmitted. The heat insulating material 7b is also effective as an air layer.

さらに、半導体素子１ｂの直上に搭載する第２の半導体装置１０４の第２のモジュール基板３ｂの裏面に形成した伝熱用パッドとしての金属パターン９でない領域で、かつ第２のモジュール基板３ｂと伝熱層としての断熱材１１との間に断熱層としての断熱材７ａが設けられている。その他は実施の形態１と同じである。   Further, the region is not the metal pattern 9 as the heat transfer pad formed on the back surface of the second module substrate 3b of the second semiconductor device 104 mounted immediately above the semiconductor element 1b, and is in communication with the second module substrate 3b. A heat insulating material 7a as a heat insulating layer is provided between the heat insulating material 11 as a heat layer. The rest is the same as in the first embodiment.

また、この実施の形態では上層に形成した半導体装置１０４よりも下層に搭載した半導体装置１０３の方が、動作時の半導体装置表面の温度が高い。
（実施の形態３）
図３は本発明の実施の形態３の積層型半導体装置を示している。 In this embodiment, the temperature of the semiconductor device surface during operation is higher in the semiconductor device 103 mounted in the lower layer than in the semiconductor device 104 formed in the upper layer.
(Embodiment 3)
FIG. 3 shows a stacked semiconductor device according to the third embodiment of the present invention.

実施の形態１の第１の半導体装置１０１における半導体素子１ａと第２の半導体装置１０２における半導体素子１ｂとはフリップチップ方式にて実装されていたが、この実施の形態３では、保証温度の低い半導体素子１ａが、第１層目の第１の半導体装置１０５の第１のモジュール基板３ａの上面に実装されて、Ａｕ線１３ａによるワイヤボンド方式などにより電気接続されている。さらに、半導体素子１ａとＡｕ線１３ａとがトランスファー方式や印刷、ポッティング樹脂などで形成した封止材１４ａによって封止されている。第２層目の第２の半導体装置１０６の第２のモジュール基板３ｂと封止材１４ａの間には、断熱材７が介装されており、封止材１４ａは断熱材７を介して第２のモジュール基板３ｂの下面に形成された金属パターン９に接触している。   The semiconductor element 1a in the first semiconductor device 101 of the first embodiment and the semiconductor element 1b in the second semiconductor device 102 are mounted by the flip chip method, but in this third embodiment, the guaranteed temperature is low. The semiconductor element 1a is mounted on the upper surface of the first module substrate 3a of the first semiconductor device 105 in the first layer, and is electrically connected by a wire bonding method using Au wires 13a. Further, the semiconductor element 1a and the Au wire 13a are sealed by a sealing material 14a formed by a transfer method, printing, potting resin or the like. The heat insulating material 7 is interposed between the second module substrate 3b of the second semiconductor device 106 of the second layer and the sealing material 14a, and the sealing material 14a is interposed between the second heat insulating material 7 and the second heat insulating material 7. 2 is in contact with the metal pattern 9 formed on the lower surface of the module substrate 3b.

また、発熱量の大きい半導体素子１ｂが第２層目の第２の半導体装置１０６の第２のモジュール基板３ｂの上面に実装されて、Ａｕ線１３ｂによるワイヤボンド方式などにより電気接続されている。さらに、半導体素子１ｂとＡｕ線１３ｂとがトランスファー方式や印刷、ポッティング樹脂などで形成した封止材１４ｂによって封止されている。封止材１４ｂは伝導度の良い伝熱材１１を介して金属板１０に接触して熱結合されている。その他は実施の形態１と同じである。   Further, the semiconductor element 1b having a large calorific value is mounted on the upper surface of the second module substrate 3b of the second semiconductor device 106 in the second layer, and is electrically connected by a wire bonding method using Au wires 13b. Further, the semiconductor element 1b and the Au wire 13b are sealed by a sealing material 14b formed by a transfer method, printing, potting resin or the like. The sealing material 14b is in thermal contact with the metal plate 10 through the heat transfer material 11 having good conductivity. The rest is the same as in the first embodiment.

（実施の形態４）
図４は本発明の実施の形態４の積層型半導体装置を示している。
実施の形態２の第１の半導体装置１０３における半導体素子１ｂと第２の半導体装置１１０４における半導体素子１ｂとはフリップチップ方式にて実装されていたが、この実施の形態４では、発熱量の大きい半導体素子１ｂが第１層目の第１の半導体装置１０７の第１のモジュール基板３ａの上面に実装されて、Ａｕ線１３ａによるワイヤボンド方式などにより電気接続されている。さらに、半導体素子１ａとＡｕ線１３ａとがトランスファー方式や印刷、ポッティング樹脂などで形成した封止材１４ａによって封止されている。第２のモジュール基板３ｂと封止材１４ａの間には、伝熱材１１が介装されている。 (Embodiment 4)
FIG. 4 shows a stacked semiconductor device according to the fourth embodiment of the present invention.
The semiconductor element 1b in the first semiconductor device 103 of the second embodiment and the semiconductor element 1b in the second semiconductor device 1104 are mounted by a flip chip method. In the fourth embodiment, the amount of heat generated is large. The semiconductor element 1b is mounted on the upper surface of the first module substrate 3a of the first semiconductor device 107 in the first layer, and is electrically connected by a wire bonding method using Au wires 13a. Further, the semiconductor element 1a and the Au wire 13a are sealed by a sealing material 14a formed by a transfer method, printing, potting resin or the like. A heat transfer material 11 is interposed between the second module substrate 3b and the sealing material 14a.

保証温度の低い半導体素子１ａが、第２層目の第２の半導体装置１０８の第２のモジュール基板３ｂの上面に実装されて、Ａｕ線１３ｂによるワイヤボンド方式などにより電気接続されている。さらに、半導体素子１ｂとＡｕ線１３ｂとがトランスファー方式や印刷、ポッティング樹脂などで形成した封止材１４ｂによって封止されている。封止材１４ｂと金属板１０の間には、断熱材７ｂが介装されている。断熱材７ｂは、空気層としても有効である。その他は実施の形態２と同じである。   The semiconductor element 1a having a low guaranteed temperature is mounted on the upper surface of the second module substrate 3b of the second semiconductor device 108 of the second layer, and is electrically connected by a wire bonding method using Au wires 13b. Further, the semiconductor element 1b and the Au wire 13b are sealed by a sealing material 14b formed by a transfer method, printing, potting resin or the like. A heat insulating material 7 b is interposed between the sealing material 14 b and the metal plate 10. The heat insulating material 7b is also effective as an air layer. The rest is the same as in the second embodiment.

上記の各実施の形態において、２段積層の積層型半導体装置を説明したが、これに限らず、３段以上に半導体装置を積層した積層型半導体装置についても同様に放熱構造をとることが可能である。その場合、図１と図２とを組み合わせた場合にも有効である。   In each of the above embodiments, a two-layer stacked semiconductor device has been described. However, the present invention is not limited to this, and a heat dissipation structure can be similarly applied to a stacked semiconductor device in which semiconductor devices are stacked in three or more stages. It is. In that case, it is also effective when FIG. 1 and FIG. 2 are combined.

本発明は、保証温度の低い半導体素子を有する積層型半導体装置の放熱構造として有用である。   The present invention is useful as a heat dissipation structure for a stacked semiconductor device having a semiconductor element with a low guaranteed temperature.

本発明にかかる実施の形態１の積層型半導体装置の断面図Sectional drawing of the laminated semiconductor device of Embodiment 1 concerning this invention. 本発明にかかる実施の形態２の積層型半導体装置の断面図Sectional drawing of the laminated semiconductor device of Embodiment 2 concerning this invention 本発明にかかる実施の形態３の積層型半導体装置の断面図Sectional drawing of the laminated semiconductor device of Embodiment 3 concerning this invention. 本発明にかかる実施の形態４の積層型半導体装置の断面図Sectional drawing of the laminated semiconductor device of Embodiment 4 concerning this invention. 従来の積層型半導体装置の断面図Sectional view of a conventional stacked semiconductor device

符号の説明Explanation of symbols

１ａ 保証温度の低い半導体素子
１ｂ 発熱量の大きい半導体素子
２ａ，２ｂ 突起電極
３ａ，３ｂ 第１，第２のモジュール基板
４ａ，４ｂ はんだボール
５ａ，５ｂ 貫通ビア
６ａ，６ｂ 電極
７，７ａ，７ｂ 断熱材
８ 伝熱ボール
９ 金属パターン
１０ 放熱板
１１ 伝熱材
１２ マザー基板
１３ａ，１３ｂ Ａｕ線
１４ａ，１４ｂ 封止材
１０１，１０３，１０５，１０７ 第１の半導体装置
１０２，１０４，１０６，１０８ 第２の半導体装置 DESCRIPTION OF SYMBOLS 1a Semiconductor element with a low guaranteed temperature 1b Semiconductor element with a large calorific value 2a, 2b Protruding electrodes 3a, 3b First and second module substrates 4a, 4b Solder balls 5a, 5b Through vias 6a, 6b Electrodes 7, 7a, 7b Thermal insulation Material 8 Heat transfer ball 9 Metal pattern 10 Heat sink 11 Heat transfer material 12 Mother substrates 13a, 13b Au wires 14a, 14b Sealing materials 101, 103, 105, 107 First semiconductor devices 102, 104, 106, 108 Second Semiconductor devices

Claims (5)

基板の表面側に半導体素子を実装した半導体装置を二つ以上の複数段積層した半導体装置であって、
前記複数段積層した最上段に搭載した半導体装置の基板の表面に実装された半導体素子の搭載部を除外した領域に熱伝導体を設け、この熱伝導体を介して放熱体を前記基板に熱結合した
半導体装置。 A semiconductor device in which a semiconductor device having a semiconductor element mounted on the surface side of a substrate is laminated in two or more stages,
A heat conductor is provided in a region excluding the mounting portion of the semiconductor element mounted on the surface of the substrate of the semiconductor device mounted on the uppermost layer stacked in a plurality of stages, and the heat radiator is heated to the substrate via the heat conductor. Combined semiconductor device. 前記放熱体と前記半導体素子の表面との間に熱伝導を抑制する断熱層または空気層を設けたことを特徴とする
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein a heat insulating layer or an air layer for suppressing heat conduction is provided between the heat radiator and the surface of the semiconductor element. 前記放熱体と前記半導体素子の表面とが熱伝導を抑制する断熱層を介して接触していることを特徴とする
請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the heat radiator and the surface of the semiconductor element are in contact with each other via a heat insulating layer that suppresses heat conduction. 基板の表面側に半導体素子を実装した半導体装置を二つ以上の複数段積層した半導体装置であって、
最上部に搭載された半導体装置よりも下層に搭載される第１の半導体装置に発熱する第１の半導体素子を実装し、前記第１の半導体素子の直上に搭載される第２の半導体装置の基板の裏面に形成した伝熱用パッドと前記第１の半導体素子とを伝熱層を介して接触させるとともに、
前記第１の半導体素子の直上に搭載する第２の半導体装置の基板の裏面に形成した前記伝熱用パッドでない領域で、かつ前記基板と前記伝熱層との間に断熱層を形成した
半導体装置。 A semiconductor device in which a semiconductor device having a semiconductor element mounted on the surface side of a substrate is laminated in two or more stages,
A first semiconductor element that generates heat is mounted on a first semiconductor device that is mounted below a semiconductor device that is mounted on the top, and a second semiconductor device that is mounted immediately above the first semiconductor element. While bringing the heat transfer pad formed on the back surface of the substrate into contact with the first semiconductor element through the heat transfer layer,
A semiconductor in which a heat insulating layer is formed between the substrate and the heat transfer layer in a region that is not the heat transfer pad formed on the back surface of the substrate of the second semiconductor device mounted immediately above the first semiconductor element apparatus. 最上段に形成した半導体装置よりも下段に搭載した半導体装置の方が、動作時の半導体装置表面の温度が高くなることを特徴とする
請求項２または請求項３に記載の半導体装置。 4. The semiconductor device according to claim 2, wherein the temperature of the semiconductor device surface during operation is higher in the semiconductor device mounted in the lower stage than in the semiconductor device formed in the uppermost stage.
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JP2010153651A (en) * 2008-12-25 2010-07-08 Canon Inc Stacked semiconductor package
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KR20150112861A (en) * 2014-03-28 2015-10-07 가부시키가이샤 제이디바이스 Semiconductor package
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JP2010153651A (en) * 2008-12-25 2010-07-08 Canon Inc Stacked semiconductor package
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US9386685B2 (en) 2010-12-30 2016-07-05 Zycube Co., Ltd. Interposer and semiconductor module using the same
KR20150112861A (en) * 2014-03-28 2015-10-07 가부시키가이샤 제이디바이스 Semiconductor package
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JP2017212286A (en) * 2016-05-24 2017-11-30 ローム株式会社 Intelligent power module, electric vehicle or hybrid car, and method of assembling intelligent power module
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CN110416094B (en) * 2018-04-30 2021-07-13 台湾积体电路制造股份有限公司 Semiconductor device and method of forming the same
US11257715B2 (en) 2018-04-30 2022-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same

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