JP2008004688A - Semiconductor package - Google Patents

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JP2008004688A
JP2008004688A JP2006171477A JP2006171477A JP2008004688A JP 2008004688 A JP2008004688 A JP 2008004688A JP 2006171477 A JP2006171477 A JP 2006171477A JP 2006171477 A JP2006171477 A JP 2006171477A JP 2008004688 A JP2008004688 A JP 2008004688A
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semiconductor chip
case member
substrate
refrigerant
chip
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Japanese (ja)
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Hiroyoshi Ogawa
裕誉 小川
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Noda Screen Co Ltd
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Noda Screen Co Ltd
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Priority to JP2006171477A priority Critical patent/JP2008004688A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package capable of highly efficient heat radiation without increasing its size. <P>SOLUTION: A semiconductor chip 20 is mounted on a printed board 10, and the semiconductor chip 20 is covered with a metallic case member 30. Then, an insulative refrigerant R is sealed into the inside of the case member 30. According to this configuration, heat from the semiconductor chip 20 is transmitted to the case member by heat convection of the refrigerant R, and radiated to an external space via the case member 30. In this case, since the case member 30 is formed of a metal having good thermal conductivity, heat radiation efficiency to the external space can be improved. Also, since the case member 30 has a comparatively high coefficient of thermal expansion and follows the thermal expansion of the refrigerant R, a wall thickness is not necessarily made large in consideration of an expansion pressure. As a result, the semiconductor package 1 can be miniaturized. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体パッケージに関する。   The present invention relates to a semiconductor package.

近年の半導体チップは、高密度化および高速化によって単位面積あたりの発熱量が増大している。このため、半導体パッケージにおける放熱の試みはますます必須の技術となってきている。   In recent semiconductor chips, the amount of heat generated per unit area is increasing due to higher density and higher speed. For this reason, attempts to dissipate heat in semiconductor packages have become increasingly essential technologies.

従来の放熱技術は、(i)半導体チップのシリコン基板側の面（素子が形成される側とは逆側の面）にヒートシンクを設置するもの、(ii)半導体チップの接続素子を介してプリント配線板側に放熱を行わせるもの、(iii）半導体パッケージの内部に冷媒を循環させて放熱を行わせるもの、(iv)半導体チップの表面積を増大させて放射により空冷させるもの、等がある。   Conventional heat dissipation technologies are: (i) a semiconductor chip with a heat sink installed on the silicon substrate side surface (the surface opposite to the side on which the elements are formed), and (ii) printing via the semiconductor chip connection elements. There are those that radiate heat on the wiring board side, (iii) those that circulate a refrigerant inside the semiconductor package and radiate heat, and (iv) those that increase the surface area of the semiconductor chip and cool it by radiation.

なかでも、半導体パッケージの内部に冷媒を循環させて半導体チップと冷媒との熱交換により放熱を行わせる技術は、冷媒の熱対流により、高効率の放熱が可能となるという利点がある（例えば特許文献１参照）。さらに、半導体チップがフリップチップ実装されているものであれば、チップにおいて発熱が生じる側である素子側の面と基板との間に隙間が存在するため、この隙間に冷媒が入り込んで素子側の面に接触し、直接に冷却できる、という利点がある（特許文献２参照）。
特開平５−２２６５２９号公報 特開平６−３１０６２６号公報 Among them, the technology that circulates the coolant inside the semiconductor package and radiates heat by heat exchange between the semiconductor chip and the coolant has an advantage that heat can be radiated with high efficiency by heat convection of the coolant (for example, patents). Reference 1). Furthermore, if the semiconductor chip is flip-chip mounted, there is a gap between the element-side surface, which is the side where heat is generated in the chip, and the substrate. There exists an advantage that it can contact a surface and can cool directly (refer patent document 2).
JP-A-5-226529 JP-A-6-310626

しかし、冷媒を使用する半導体パッケージでは、冷媒の熱膨張による膨張圧に耐えるため、半導体チップをシールするケース部材として剛性の高いセラミック製のものが使用され、また、ケース部材の壁厚として相当の厚さが確保されることが通常である。このため、パッケージが大型化すること、ケース部材を介しての外部への熱伝達効率が低くなってしまうこと、等の問題がある。
本発明は、上記した事情に鑑みてなされたものであり、その目的は、大型化することなく高効率の放熱を可能とする半導体パッケージを提供することにある。 However, in a semiconductor package that uses a refrigerant, in order to withstand the expansion pressure due to the thermal expansion of the refrigerant, a case made of a highly rigid ceramic is used as a case member for sealing a semiconductor chip, and the wall thickness of the case member is considerable. Usually, the thickness is ensured. For this reason, there exist problems, such as a package becoming large and the heat transfer efficiency to the exterior through a case member becoming low.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor package that enables highly efficient heat dissipation without increasing the size.

本発明の半導体パッケージは、基板と、前記基板上に実装された半導体チップと、前記基板上に設けられて前記半導体チップを覆う金属製のケース部材と、前記ケース部材の内部に封入される液状の冷媒と、を備えるものである。   The semiconductor package according to the present invention includes a substrate, a semiconductor chip mounted on the substrate, a metal case member provided on the substrate and covering the semiconductor chip, and a liquid sealed inside the case member. The refrigerant is provided.

本発明において、一の基板にはただ１つの半導体チップが実装され、かつ、基板に設けられるものであって半導体チップに設けられるチップ側端子と接続される第１の基板側接続端子、およびこの第１の基板側接続端子と電気的に接続されて外部基板との接続に使用される第２の基板側接続端子の配列が、チップ側端子の配列と等しくされていることが好ましい。このような構成によれば、半導体パッケージをチップサイズに近いサイズにまで小型化でき、半導体パッケージを半導体チップと同様に取り扱うことができる。また、外部基板側のランド構造を、半導体チップを直接に実装する場合と半導体パッケージを実装する場合とで変更する必要がないから、設計を汎用化できる。   In the present invention, only one semiconductor chip is mounted on one substrate, and the first substrate-side connection terminal is provided on the substrate and is connected to the chip-side terminal provided on the semiconductor chip. It is preferable that the arrangement of the second board-side connection terminals that are electrically connected to the first board-side connection terminals and used for connection to the external board is equal to the arrangement of the chip-side terminals. According to such a configuration, the semiconductor package can be downsized to a size close to the chip size, and the semiconductor package can be handled in the same manner as the semiconductor chip. In addition, it is not necessary to change the land structure on the external substrate side between the case where the semiconductor chip is directly mounted and the case where the semiconductor package is mounted, so that the design can be generalized.

本発明によれば、半導体チップを基板上に搭載し、この半導体チップを金属製のケース部材で覆う。そして、ケース部材の内部には、絶縁性の冷媒（好ましくは不燃性、絶縁性の冷媒）を封入する。このような構成によれば、半導体チップからの熱が冷媒の熱対流によってケース部材まで伝えられ、このケース部材を介して外部空間に放散される。このとき、ケース部材は熱伝導性の良い金属により形成されているので、外部空間へ効率よく熱が放散される。これにより、放熱効率を高めることができる。
また、ケース部材は熱膨張率が比較的大きな金属により形成されており、冷媒の熱膨張に追従するから、冷媒の膨張による内圧の上昇に配慮して壁厚を大きくする必要がない。このため、半導体パッケージの小型化が図れる。 According to the present invention, a semiconductor chip is mounted on a substrate, and the semiconductor chip is covered with a metal case member. An insulating refrigerant (preferably a nonflammable or insulating refrigerant) is sealed inside the case member. According to such a configuration, the heat from the semiconductor chip is transmitted to the case member by the thermal convection of the refrigerant, and is dissipated to the external space through the case member. At this time, since the case member is formed of a metal having good thermal conductivity, heat is efficiently dissipated to the external space. Thereby, heat dissipation efficiency can be improved.
Further, since the case member is made of a metal having a relatively large coefficient of thermal expansion and follows the thermal expansion of the refrigerant, it is not necessary to increase the wall thickness in consideration of an increase in internal pressure due to the expansion of the refrigerant. For this reason, the semiconductor package can be reduced in size.

以下、本発明を具体化した実施形態について、図１および図２を参照しつつ詳細に説明する。
図１には、本発明を具体化した半導体パッケージ１の側断面図を、図２には、この半導体パッケージ１の分解側断面図をを示す。この半導体パッケージ１は、プリント基板１０（本発明の基板に該当する）に半導体チップ２０を実装し、半導体チップ２０の周囲をケース部材３０で封止したハーメチック構造のものである。 DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments embodying the present invention will be described in detail with reference to FIGS. 1 and 2.
FIG. 1 is a side sectional view of a semiconductor package 1 embodying the present invention, and FIG. 2 is an exploded side sectional view of the semiconductor package 1. The semiconductor package 1 has a hermetic structure in which a semiconductor chip 20 is mounted on a printed circuit board 10 (corresponding to a substrate of the present invention) and the periphery of the semiconductor chip 20 is sealed with a case member 30.

プリント基板１０は、絶縁層１１の両面に所定の導体回路が形成された周知の構造のものであって、半導体チップ２０の外形よりも一回り大きく形成されている。導体回路の一部はランド１２とされている。表裏のランド１２のうち、半導体チップ２０が搭載される側の面（図１の上面）に設けられた表面側ランド１２Ａ（本発明の第１の基板側接続端子に該当する）は、半導体チップ２０に設けられた電極パッド２３（本発明のチップ側端子に該当する。詳細は後述する。）との接続のためのものである。一方、これとは逆側の面（図１の下面）に設けられた裏面側ランド１２Ｂは、外部基板（図示せず）との接続のためのものである。表面側ランド１２Ａと裏面側ランド１２Ｂとの間は、絶縁層１１に貫通形成されたビアホール１３によって電気的に接続されている。また、裏面側ランド１２Ｂ上には、外部基板（図示せず）との接続のための基板側バンプ１４が形成されている。   The printed circuit board 10 has a known structure in which predetermined conductor circuits are formed on both surfaces of the insulating layer 11, and is formed slightly larger than the outer shape of the semiconductor chip 20. A part of the conductor circuit is a land 12. Of the front and back lands 12, the front side land 12 </ b> A (corresponding to the first substrate-side connection terminal of the present invention) provided on the surface on which the semiconductor chip 20 is mounted (the upper surface in FIG. 1) 20 for connection with an electrode pad 23 (corresponding to a chip-side terminal of the present invention, details will be described later). On the other hand, the back surface side land 12B provided on the opposite surface (the lower surface in FIG. 1) is for connection to an external substrate (not shown). The front side land 12 </ b> A and the back side land 12 </ b> B are electrically connected by a via hole 13 penetratingly formed in the insulating layer 11. Further, substrate-side bumps 14 for connection to an external substrate (not shown) are formed on the rear surface side land 12B.

このプリント基板１０上に搭載される半導体チップ２０は周知の構成のものであって、シリコン基板２１の一面側（図１の下面側）に半導体素子が形成されたものである。半導体チップ２０において素子が形成された側の面はパッシベーション膜２２によって覆われ、このパッシベーション膜２２の開口からは電極パッド２３が臨んでいる。この電極パッド２３上には、チップ側バンプ２４が形成されている。   The semiconductor chip 20 mounted on the printed circuit board 10 has a well-known configuration, and a semiconductor element is formed on one surface side (the lower surface side in FIG. 1) of the silicon substrate 21. The surface of the semiconductor chip 20 on which elements are formed is covered with a passivation film 22, and an electrode pad 23 faces from the opening of the passivation film 22. Chip-side bumps 24 are formed on the electrode pads 23.

半導体チップ２０は、プリント基板１０上にフリップチップ実装されており、チップ側バンプ２４を介して、電極パッド２３とプリント基板１０における表面側ランド１２Ａとが電気的に接続されている。半導体チップ２０はチップ側バンプ２４の高さ分だけプリント基板１０から浮かせて実装されている。   The semiconductor chip 20 is flip-chip mounted on the printed circuit board 10, and the electrode pad 23 and the front surface land 12 </ b> A on the printed circuit board 10 are electrically connected via the chip-side bump 24. The semiconductor chip 20 is mounted so as to float from the printed board 10 by the height of the chip-side bump 24.

なお、１枚のプリント基板１０上にはただ１つの半導体チップ２０が実装されている。加えて、プリント基板１０において半導体チップ２０側の電極パッド２３と接続される表面側ランド１２Ａ、およびこの表面側ランド１２Ａとビアホール１３を介して接続されて外部基板との接続に使用される裏面側ランド１２Ｂの配列は、電極パッド２３の配列と同一とされている。   Note that only one semiconductor chip 20 is mounted on one printed circuit board 10. In addition, the front surface side land 12A connected to the electrode pad 23 on the semiconductor chip 20 side in the printed circuit board 10, and the back surface side connected to the front surface land 12A via the via hole 13 and used for connection to an external substrate. The arrangement of the lands 12B is the same as the arrangement of the electrode pads 23.

この半導体チップ２０は、ケース部材３０によって覆われている。ケース部材３０は上下に２分割された下ケース部３１と上ケース部３５とで構成されている（図２を併せて参照）。下ケース部３１は、金属により上面側が開放された矩形浅皿状に形成されており、その底壁部３２には、半導体チップ２０を受け入れ可能な開口部３３が形成されている。また、側壁部３４は、それぞれ上側に行くほど外側に傾いて形成されている。この下ケース部３１は、開口部３３の内側に半導体チップ２０を収容するようにして、プリント基板１０上に接着剤により固定されている。一方、上ケース部３５は、金属により、下面側が開放された矩形浅皿状に形成されており、下ケース部３１における上面側の開口に覆い付けられ、接着剤により固定されている。上ケース部３５の側壁部３６は、それぞれ、その下端縁が下ケース部３１における側壁部３４の上縁と整合し、上側に行くほど内側に傾いて形成されている。これにより、下ケース部３１と上ケース部３５とが組み付けられた状態では、その側壁部３４、３６は、上下方向の中央位置が外側に広がる断面Ｖ字状をなす。   The semiconductor chip 20 is covered with a case member 30. The case member 30 is composed of a lower case portion 31 and an upper case portion 35 that are divided into upper and lower portions (see also FIG. 2). The lower case portion 31 is formed in a rectangular shallow dish shape whose upper surface side is opened by metal, and an opening 33 that can receive the semiconductor chip 20 is formed in the bottom wall portion 32 thereof. Further, the side wall portions 34 are formed so as to be inclined outward as they go upward. The lower case portion 31 is fixed on the printed circuit board 10 with an adhesive so as to accommodate the semiconductor chip 20 inside the opening 33. On the other hand, the upper case portion 35 is formed of a metal in a rectangular shallow dish shape whose lower surface side is opened, and is covered with an opening on the upper surface side of the lower case portion 31 and fixed by an adhesive. Each of the side wall portions 36 of the upper case portion 35 is formed such that the lower end edge thereof is aligned with the upper edge of the side wall portion 34 in the lower case portion 31 and is inclined inward as going upward. Thus, in a state where the lower case portion 31 and the upper case portion 35 are assembled, the side wall portions 34 and 36 have a V-shaped cross section in which the center position in the vertical direction extends outward.

このケース部材３０の内部は、液状の冷媒Ｒで満たされている。冷媒Ｒは、絶縁性で半導体チップ２０やプリント基板１０の材料と反応しない液体であれば特に制限はなく、例えば、住友スリーエム（株）製「フロリナート（登録商標）」、ソルベイソレクシス（株）製「ガルデン（登録商標）」等の不燃性であるフッ素系不活性液を使用できる。
なお、冷媒Ｒは、沸点１５０℃以上の液体が好ましく、沸点２００℃以上の液体であればさらに好ましい。 The inside of the case member 30 is filled with a liquid refrigerant R. The refrigerant R is not particularly limited as long as it is an insulating liquid that does not react with the material of the semiconductor chip 20 or the printed circuit board 10. For example, “Fluorinert (registered trademark)” manufactured by Sumitomo 3M Limited, Solvay Solexis Co., Ltd. A non-flammable fluorine-based inert liquid such as “Galden (registered trademark)” manufactured by the Company can be used.
The refrigerant R is preferably a liquid having a boiling point of 150 ° C. or higher, and more preferably a liquid having a boiling point of 200 ° C. or higher.

次に、上記のように構成された本実施形態の作用および効果について説明する。   Next, the operation and effect of the present embodiment configured as described above will be described.

この半導体パッケージ１は、基板側バンプ１４を介して外部基板に接続され、使用される。半導体パッケージ１に給電がなされると、半導体チップ２０上の半導体素子から熱が発生する。ここで、ケース部材３０の内部には冷媒Ｒが封入されているので、この冷媒Ｒが半導体チップ２０から熱を受け取る。本実施形態では、半導体チップ２０はチップ側バンプ２４の高さ分だけプリント基板１０から浮かせて実装されているから、冷媒Ｒが半導体チップ２０とプリント基板１０との隙間に入り込んで、半導体チップ２０における素子側の面（パッシベーション膜２２が形成されている側の面）に直接に接触し、冷却する。   The semiconductor package 1 is used by being connected to an external substrate via a substrate-side bump 14. When power is supplied to the semiconductor package 1, heat is generated from the semiconductor elements on the semiconductor chip 20. Here, since the refrigerant R is sealed inside the case member 30, the refrigerant R receives heat from the semiconductor chip 20. In the present embodiment, the semiconductor chip 20 is mounted so as to float from the printed board 10 by the height of the chip-side bump 24, so that the coolant R enters the gap between the semiconductor chip 20 and the printed board 10, and the semiconductor chip 20. Directly contact the element side surface (the surface on which the passivation film 22 is formed) and cool.

半導体チップ２０の周囲に存在する冷媒Ｒは熱を受け取って温まり、これにより、冷媒Ｒに熱対流が生じる。そして、この熱対流に乗って熱がケース部材３０まで伝えられ、ケース部材３０を介して大気中に放散される。このとき、ケース部材３０は熱伝導性の良い金属により形成されているから、大気中へ効率よく熱が放散される。この放熱により、半導体チップで発生した熱が電極を通じて基板側に伝熱されていた現象が軽減される。   The refrigerant R present around the semiconductor chip 20 receives the heat and warms up, and thereby heat convection occurs in the refrigerant R. Then, the heat is transmitted to the case member 30 by this thermal convection and is dissipated into the atmosphere through the case member 30. At this time, since the case member 30 is made of a metal having good thermal conductivity, heat is efficiently dissipated into the atmosphere. Due to this heat dissipation, the phenomenon that the heat generated in the semiconductor chip is transferred to the substrate side through the electrodes is reduced.

また、冷媒Ｒは半導体チップ２０からの熱を吸収することによって温度が上がり、熱膨張する。ここで、ケース部材３０は熱膨張率が比較的大きな金属により形成されているから、自身も冷媒Ｒから熱を受け取って熱膨張し、冷媒Ｒの熱膨張に追従する。このため、内圧の上昇を考慮してケース部材３０の壁厚を大きくする必要がなく、半導体パッケージ１の小型化が図れる。   In addition, the refrigerant R absorbs heat from the semiconductor chip 20, so that the temperature rises and thermally expands. Here, since the case member 30 is formed of a metal having a relatively large coefficient of thermal expansion, the case member 30 itself receives heat from the refrigerant R and thermally expands to follow the thermal expansion of the refrigerant R. For this reason, it is not necessary to increase the wall thickness of the case member 30 in consideration of an increase in internal pressure, and the semiconductor package 1 can be downsized.

また、１枚のプリント基板１０上にはただ１つの半導体チップ２０が実装されている。加えて、プリント基板１０において半導体チップ２０側の電極パッド２３と接続される表面側ランド１２Ａ、およびこの表面側ランド１２Ａとビアホール１３を介して接続されて外部基板との接続に使用される裏面側ランド１２Ｂの配列は、半導体チップ２０側の電極パッド２３の配列と同一とされている。これにより、半導体パッケージ１をチップサイズに近いサイズにまで小型化でき、半導体パッケージ１を半導体チップ２０と同様に取り扱うことができる。また、外部基板側のランド構造を、半導体チップ２０を直接に実装する場合と半導体パッケージ１を実装する場合とで変更する必要がないから、設計を汎用化できる。   Further, only one semiconductor chip 20 is mounted on one printed board 10. In addition, the front side land 12A connected to the electrode pad 23 on the semiconductor chip 20 side in the printed circuit board 10 and the back side used for connection to the external side substrate connected to the front side land 12A via the via hole 13 The arrangement of the lands 12B is the same as the arrangement of the electrode pads 23 on the semiconductor chip 20 side. Thereby, the semiconductor package 1 can be downsized to a size close to the chip size, and the semiconductor package 1 can be handled in the same manner as the semiconductor chip 20. Moreover, since the land structure on the external substrate side does not need to be changed between the case where the semiconductor chip 20 is directly mounted and the case where the semiconductor package 1 is mounted, the design can be generalized.

本発明の技術的範囲は、上記した実施形態によって限定されるものではなく、例えば、次に記載するようなものも本発明の技術的範囲に含まれる。
（１）上記実施形態では、ケース部材３０は下ケース部３１と上ケース部３５に２分割されたものとなっていたが、ケース部材は必ずしも分割されている必要はなく、全体が一体に形成されたものであっても構わない。
（２）上記実施形態では、プリント基板１０は絶縁層１１の両面に所定の導体回路が形成された単層の基板であったが、複数の絶縁性基板と導体層とが積層された多層プリント配線板であっても構わない。プリント基板１０は、ガラス基板あるいはセラミックス基板に貫通電極を設けた構造であれば、放熱効果が高く、機械剛性も向上するため、更に好適である。
（３）上記実施形態では、ケース部材は熱膨張係数の比較的大きい金属としたが、熱伝導性の高いガラスやセラミックスを使うのも好適である。 The technical scope of the present invention is not limited by the above-described embodiments, and, for example, those described below are also included in the technical scope of the present invention.
(1) In the above embodiment, the case member 30 is divided into the lower case portion 31 and the upper case portion 35. However, the case member does not necessarily need to be divided, and the whole is formed integrally. It may be the one that was made.
(2) In the above embodiment, the printed board 10 is a single-layer board in which predetermined conductor circuits are formed on both surfaces of the insulating layer 11, but a multilayer print in which a plurality of insulating boards and conductor layers are laminated. It may be a wiring board. If the printed circuit board 10 has a structure in which a through electrode is provided on a glass substrate or a ceramic substrate, the heat dissipation effect is high and the mechanical rigidity is improved, which is more preferable.
(3) In the above embodiment, the case member is a metal having a relatively large thermal expansion coefficient, but it is also preferable to use glass or ceramics having high thermal conductivity.

半導体パッケージの側断面図Side sectional view of semiconductor package 半導体パッケージの分解側断面図Exploded side sectional view of semiconductor package

符号の説明Explanation of symbols

１…半導体パッケージ
１０…プリント基板（基板）
１２Ａ…表面側ランド（第１の基板側接続端子）
１２Ｂ…裏面側ランド（第２の基板側接続端子）
２０…半導体チップ
２３…電極パッド（チップ側端子）
３０…ケース部材
Ｒ…冷媒
DESCRIPTION OF SYMBOLS 1 ... Semiconductor package 10 ... Printed circuit board (board | substrate)
12A: Front side land (first board side connection terminal)
12B: Back side land (second board side connection terminal)
20 ... Semiconductor chip 23 ... Electrode pad (chip side terminal)
30: Case member R: Refrigerant

Claims (2)

基板と、
前記基板上に実装された半導体チップと、
前記基板上に設けられて前記半導体チップを覆う金属製のケース部材と、
前記ケース部材の内部に封入される液状の冷媒と、
を備える半導体パッケージ。 A substrate,
A semiconductor chip mounted on the substrate;
A metal case member provided on the substrate and covering the semiconductor chip;
A liquid refrigerant sealed inside the case member;
A semiconductor package comprising: 一の前記基板にはただ１つの前記半導体チップが実装され、
かつ、前記基板に設けられるものであって前記半導体チップに設けられるチップ側端子と接続される第１の基板側接続端子、およびこの第１の基板側接続端子と電気的に接続されて外部基板との接続に使用される第２の基板側接続端子の配列が、前記チップ側端子の配列と等しくされていることを特徴とする請求項１に記載の半導体パッケージ。
Only one semiconductor chip is mounted on one substrate,
A first substrate-side connecting terminal provided on the substrate and connected to a chip-side terminal provided on the semiconductor chip; and an external substrate electrically connected to the first substrate-side connecting terminal. 2. The semiconductor package according to claim 1, wherein an arrangement of the second substrate-side connection terminals used for connection to the chip is equal to an arrangement of the chip-side terminals.
JP2006171477A 2006-06-21 2006-06-21 Semiconductor package Pending JP2008004688A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146497A (en) * 2010-01-14 2011-07-28 Toshiba Design & Manufacturing Service Corp Printed wiring board incorporating semiconductor chip
CN103094227A (en) * 2011-10-28 2013-05-08 中国科学院理化技术研究所 Three-dimensional chip and combination structure and manufacture method of three-dimensional chip
WO2013076909A1 (en) 2011-11-21 2013-05-30 パナソニック株式会社 Resin for electrical components, semiconductor device, and wiring board
CN105206645A (en) * 2015-08-31 2015-12-30 深圳市华星光电技术有限公司 OLED display module set and display thereof
JP2017520933A (en) * 2014-07-14 2017-07-27 マイクロン テクノロジー， インク． Stacked semiconductor die assembly and associated system having high efficiency thermal path

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53135579A (en) * 1977-05-02 1978-11-27 Hitachi Ltd Liquid sealing semiconductor device
JPS5650548A (en) * 1979-10-02 1981-05-07 Nec Corp Manufacture of semiconductor device
JPS5839043A (en) * 1981-09-02 1983-03-07 Mitsubishi Electric Corp Semiconductor device
JPH04315458A (en) * 1991-04-15 1992-11-06 Sony Corp Multilayered wiring board
JPH07161866A (en) * 1993-12-09 1995-06-23 Nec Corp Lsi chip carrier structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53135579A (en) * 1977-05-02 1978-11-27 Hitachi Ltd Liquid sealing semiconductor device
JPS5650548A (en) * 1979-10-02 1981-05-07 Nec Corp Manufacture of semiconductor device
JPS5839043A (en) * 1981-09-02 1983-03-07 Mitsubishi Electric Corp Semiconductor device
JPH04315458A (en) * 1991-04-15 1992-11-06 Sony Corp Multilayered wiring board
JPH07161866A (en) * 1993-12-09 1995-06-23 Nec Corp Lsi chip carrier structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146497A (en) * 2010-01-14 2011-07-28 Toshiba Design & Manufacturing Service Corp Printed wiring board incorporating semiconductor chip
CN103094227A (en) * 2011-10-28 2013-05-08 中国科学院理化技术研究所 Three-dimensional chip and combination structure and manufacture method of three-dimensional chip
WO2013076909A1 (en) 2011-11-21 2013-05-30 パナソニック株式会社 Resin for electrical components, semiconductor device, and wiring board
US9265144B2 (en) 2011-11-21 2016-02-16 Panasonic Intellectual Property Management Co., Ltd. Electrical component resin, semiconductor device, and substrate
JP2017520933A (en) * 2014-07-14 2017-07-27 マイクロン テクノロジー， インク． Stacked semiconductor die assembly and associated system having high efficiency thermal path
CN105206645A (en) * 2015-08-31 2015-12-30 深圳市华星光电技术有限公司 OLED display module set and display thereof

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