JPS5839043A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5839043A JPS5839043A JP56138975A JP13897581A JPS5839043A JP S5839043 A JPS5839043 A JP S5839043A JP 56138975 A JP56138975 A JP 56138975A JP 13897581 A JP13897581 A JP 13897581A JP S5839043 A JPS5839043 A JP S5839043A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- heat
- insulating substrate
- freon
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/427—Cooling by change of state, e.g. use of heat pipes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置、−特にパップを形成した半導体
チップを７リツプチツプ方式で実装する半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor chip on which a pad is formed is mounted using a seven-lip chip method.
従来、この橋の半導体装置は能動菓子とＰｂ−Ｂｎ半田
のパップ（突起電極）とを形成した半導体チップ（以下
単にチップと称す）、それを搭載する絶縁基板及びチッ
プを保鏝しチップからの発熱を放散する蓋から構成され
ていた。チップは絶縁基板にバンクによって固定され、
チップの能ｍｌ子による電気的機能はバングを経由して
絶縁基板内の配線に伝えられ、絶縁基板に取付けられた
外部リード等によって外部に取り出せる様になっていた
。蓋はチップを覆う様にして絶縁基板に取付けられ、蓋
と絶縁基板とによってその中空部分にチップを気密封止
していた。そして、チップと蓋とは例えばバネによる弾
力を有する接触を持たせ、チップからの発熱を蓋に逃が
す構造ｌζなっていた。Conventionally, this bridge semiconductor device consists of a semiconductor chip (hereinafter simply referred to as a chip) on which an active confectionery and Pb-Bn solder pads (protruding electrodes) are formed, an insulating substrate on which it is mounted, and a protective trowel for the chip. It consisted of a lid that dissipated heat. The chip is fixed to an insulating substrate by a bank,
The electrical functions of the chip were transmitted to wiring within the insulating substrate via the bang, and could be taken out to the outside through external leads etc. attached to the insulating substrate. The lid was attached to the insulating substrate so as to cover the chip, and the chip was hermetically sealed in the hollow portion between the lid and the insulating substrate. The chip and the lid are brought into contact with each other with elasticity, for example, by a spring, and the structure is such that heat generated from the chip is released to the lid.
バネを用いる理由は蓋と絶縁基板とを気密封止した時に
、蓋とチップとの間隔を精密に制御するこ、とが暑しい
ためであり、半田付けの様な固定手段が使用出来ないこ
とになる。このことは、′チップからの発熱を蓋に伝達
する率が低下するという欠点を招来していた。これは蓋
に２つの機能（気密封止とチップの放熱）を兼ねさせて
いるために起る欠点である。The reason for using a spring is that when the lid and insulating substrate are hermetically sealed, the distance between the lid and the chip must be precisely controlled, which is hot, and fixing methods such as soldering cannot be used. become. This has resulted in the disadvantage that the rate at which heat from the chip is transmitted to the lid is reduced. This is a drawback because the lid has two functions (hermetic sealing and heat radiation from the chip).
本発明は従来のもののこの様な欠点を除去するものでチ
ップの気密封止と放熱を別々の構成物で機能させようと
するものである。以下に図面を用いて本発明の詳細な説
明する。The present invention aims to eliminate these drawbacks of the prior art, and attempts to make the hermetic sealing and heat dissipation of the chip function as separate structures. The present invention will be described in detail below using the drawings.
３３１図、第２図は本発明の一実施例を示す。第１５！
Ｑにおいて、１１１は一生面上に能動素子（図示せず）
を形成したチップ、（２）は上記−主面上に形成したバ
ンク、＋３１は上記能動素子を取り囲む様に上記−主面
上に形成したシールリングである。バングとシールリン
グはＰｂ−８ｎの半田からなり、その高３ｈは共にほぼ
同じになされている。シールリング（ＩＩはバンク（２
）を形成するのと同じ工程で作ることによって容易に形
成することができる。第２図において、（４）は絶縁基
板でチップ（１１をバンク（２）により固定して搭載し
チップの電気的機能をパンダ（２）を＊、じて外部リー
ド（５目と取り出せる様にしている。（６）は蓋を構成
する放熱フイ／で、チップ（１１を覆う様にして絶縁基
板（４）に歌付けられている。331 and 2 show an embodiment of the present invention. 15th!
In Q, 111 is an active element (not shown) on the surface.
(2) is a bank formed on the negative main surface, and +31 is a seal ring formed on the negative main surface so as to surround the active element. The bang and seal ring are made of Pb-8n solder, and their heights (3h) are approximately the same. Seal ring (II is bank (2)
) can be easily formed by using the same process as for forming. In Figure 2, (4) is an insulating substrate, and the chip (11) is fixed and mounted on the bank (2), and the electrical function of the chip is connected to the panda (2)*, so that the external lead (5) can be taken out. (6) is a heat dissipation fin that constitutes the lid, and is attached to the insulating substrate (4) so as to cover the chip (11).
（７）は液体状のフレイ／で、絶縁基板（４）と放熱フ
イ／【６）との間にできた中空部分にチップ（１１を囲
繞するように封じ込めている。(7) is a liquid flame/, which is sealed so as to surround the chip (11) in a hollow portion formed between the insulating substrate (4) and the heat dissipation fin/[6].
このとき、チップ１１＋と絶縁基板（４）との間番こは
シールリング（３１の高さだけ間隙が形成され、チップ
表面に形成した能動素子は何物にも触れることなく、絶
縁基板（４）とシールリング（３１とチップ（１目こよ
って気密封止することができる。この状態で半導体チッ
プＩＩＩを動作させるとチップ［１１で発熱が起こるが
、チップ（１）に触れている７レオン（７）が蒸発。At this time, a gap is formed between the chip 11+ and the insulating substrate (4) by the height of the seal ring (31), and the active element formed on the chip surface does not touch anything. ) and the seal ring (31 and the chip (1) can be hermetically sealed. If semiconductor chip III is operated in this state, heat will be generated in the chip [11], but the (7) evaporates.
気化しチップの熱を奪う。気化したフレオン蒸気は常に
冷却されている放熱フィン（６）に接触して熱を奪われ
液化して再びチップに触れる。こうして７レオン（７１
はチップの裏面全体から熱を放熱フイ／に伝えることが
できる。一方、チップ（１１の能動素子はシールリング
（３）によって封止されているので、７レオノ【７１そ
れ自身及び７レオノ中の不純物例えばアルカリ金属、腐
食性水分等によって汚染腐食されることはない。It evaporates and takes away the heat from the chip. The vaporized Freon vapor contacts the constantly cooled radiation fins (6), removes heat, liquefies, and contacts the chip again. Thus 7 leons (71
can transfer heat from the entire backside of the chip to the heat sink. On the other hand, since the active elements of the chip (11) are sealed by the seal ring (3), they will not be contaminated or corroded by the 7 leono itself or impurities in the 7 leono, such as alkali metals and corrosive moisture. .
本発明は以上の実施例にとどまることなく、７レオン（
７）からなる熱伝達手段を例えばゲル状の樹脂で置き換
えてもよい。又、放熱フィン（６）は絶縁基板（４）に
直接固定せずに介在物を介して固定しても良い。放熱フ
ィン（６）の形状はどのような形であっても良いし、放
熱フィン（６）はチップ＋１１の機械的保護の役割を兼
ねても良い。チップｉｌ＋の電気的機能はメモリー、ロ
ジックに限ることなく、受光素子等、半導体基板に形成
できる他の全ての機能を含む。バンプ（２）はＰｂ−８
ｎに限らず他の金属又は導体を用い得る。The present invention is not limited to the above-described embodiments;
The heat transfer means consisting of 7) may be replaced with, for example, a gel-like resin. Furthermore, the heat dissipation fins (6) may not be directly fixed to the insulating substrate (4) but may be fixed via an intervening object. The heat radiation fin (6) may have any shape, and the heat radiation fin (6) may also serve as mechanical protection for the chip +11. The electrical functions of the chip il+ are not limited to memory and logic, but include all other functions that can be formed on a semiconductor substrate, such as a light receiving element. Bump (2) is Pb-8
Not limited to n, other metals or conductors can be used.
以上の説明で本明らかな様に、本発明によればチップか
ら放熱フィンに熱を伝える効率が増し、しかもチップの
能動素子を完全に保鰻できる効果がある。又、チップの
能動素子の気路封止をシールリングによって実現してい
るので、蓋の寸法精度が要求されないため蓋の加工が容
易である。As is clear from the above description, the present invention has the effect of increasing the efficiency of transmitting heat from the chip to the radiation fins and completely protecting the active elements of the chip. Furthermore, since the air passages of the active elements of the chip are sealed by the seal ring, dimensional accuracy of the lid is not required, and the processing of the lid is easy.
ＩＩ１図（ａ）は本発明の一実施例による半導体チップ
を示す斜視図、第１図（１））はＩＩ１図（−）のＩｔ
）−Ｉｂｉｉによる断面図％ｇｇｇ図は本発明の一実施
例による半導体装置を示す断面図である。
図中、【１１は半導体チップ、（２）はバンク、（３Ｊ
はシールリング、（４）は絶＃基板、（５）はリード、
（６］は放熱フィン、（７）は液体である。
代理人 ４ 釘 信 −FIG. II1(a) is a perspective view showing a semiconductor chip according to an embodiment of the present invention, FIG. 1(1)) is a perspective view of FIG. II1(-).
)-Ibii %ggg is a sectional view showing a semiconductor device according to an embodiment of the present invention. In the figure, [11 is a semiconductor chip, (2) is a bank, (3J
is the seal ring, (4) is the absolute board, (5) is the lead,
(6) is a heat dissipation fin, and (7) is a liquid. Agent 4 Nagi Shin -
Claims (1)
導体チップの電気的機能を導出し得る絶縁基板、上記半
導体チップを機うように上記絶縁基板に取付けられ上°
記半導体チップの発熱を外部に放散し得る蓋、上記半導
体チップと絶縁基板との間に設けられ上記能動系子を気
密封止するシールリング、上記半導体チップを囲繞する
ように封入され上記半導体チップの発熱を上記蓋に伝達
する熱伝達手段を備えた半導体装置。[Claims] A semi-integrated chip in which active elements and banks are formed. This semiconductor chip is fixed via the bank, and an insulating substrate capable of deriving the electrical function of the semiconductor chip is attached to the insulating substrate so as to function as the semiconductor chip.
a lid capable of dissipating heat generated by the semiconductor chip to the outside; a seal ring provided between the semiconductor chip and the insulating substrate to hermetically seal the active device; and a sealing ring enclosed to surround the semiconductor chip. A semiconductor device comprising a heat transfer means for transferring heat generated by the above to the lid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138975A JPS5839043A (en) | 1981-09-02 | 1981-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56138975A JPS5839043A (en) | 1981-09-02 | 1981-09-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5839043A true JPS5839043A (en) | 1983-03-07 |
Family
ID=15234540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56138975A Pending JPS5839043A (en) | 1981-09-02 | 1981-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5839043A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163843A (en) * | 1983-03-09 | 1984-09-14 | Nippon Denso Co Ltd | Semiconductor device |
| JPS6128612U (en) * | 1984-07-27 | 1986-02-20 | 周平 渡辺 | Mold |
| JP2008004688A (en) * | 2006-06-21 | 2008-01-10 | Noda Screen:Kk | Semiconductor package |
-
1981
- 1981-09-02 JP JP56138975A patent/JPS5839043A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163843A (en) * | 1983-03-09 | 1984-09-14 | Nippon Denso Co Ltd | Semiconductor device |
| JPS6128612U (en) * | 1984-07-27 | 1986-02-20 | 周平 渡辺 | Mold |
| JP2008004688A (en) * | 2006-06-21 | 2008-01-10 | Noda Screen:Kk | Semiconductor package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4746283B2 (en) | Method of connecting a heat sink to a circuit assembly and integrated circuit device | |
| US6853069B2 (en) | Packaged die on PCB with heat sink encapsulant and methods | |
| JPH07147466A (en) | Electronic component unit and manufacture thereof | |
| IT1143676B (en) | PROCESS FOR THE MANUFACTURE OF MICROMINIATURIZED INTEGRATED CIRCUIT DEVICES | |
| JPS6373650A (en) | Semiconductor device | |
| JPH0217659A (en) | Package for protecting circuit chip form emi, esd, heat and mechanical impact | |
| JPH08264674A (en) | Semiconductor device | |
| JPH05160312A (en) | Module for electronic package | |
| JPS5839043A (en) | Semiconductor device | |
| JPS6221249A (en) | Semiconductor device | |
| JPH04326557A (en) | Cooling structure of semiconductor chip | |
| JPH0773122B2 (en) | Sealed semiconductor device | |
| US6548759B1 (en) | Pre-drilled image sensor package | |
| JPH03182397A (en) | Ic card | |
| JP2000059003A (en) | Hybrid module | |
| JPH05206320A (en) | Multi-chip module | |
| JPS5810840A (en) | Semiconductor device | |
| TWI625833B (en) | Packaging structure | |
| JP2828385B2 (en) | IC package structure | |
| JP2765242B2 (en) | Integrated circuit device | |
| JPH06104355A (en) | Cooling liquid enclosing type semiconductor device | |
| JPS6144450Y2 (en) | ||
| JPS61225848A (en) | Semiconductor rectifier | |
| JPH08222652A (en) | Semiconductor device and production thereof | |
| JPH03104142A (en) | Resin sealed type semiconductor device |