JP2011146497A - Printed wiring board incorporating semiconductor chip - Google Patents

Printed wiring board incorporating semiconductor chip Download PDF

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Publication number
JP2011146497A
JP2011146497A JP2010005617A JP2010005617A JP2011146497A JP 2011146497 A JP2011146497 A JP 2011146497A JP 2010005617 A JP2010005617 A JP 2010005617A JP 2010005617 A JP2010005617 A JP 2010005617A JP 2011146497 A JP2011146497 A JP 2011146497A
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printed wiring
substrate
wiring board
semiconductor chip
metal case
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JP5601447B2 (en
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Eiichi Harada
田 栄 一 原
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Toshiba Design and Manufacturing Service Corp
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Toshiba Design and Manufacturing Service Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board incorporating a semiconductor chip having no adverse effect by an interlayer adhesive material, and to provide a method of manufacturing the same. <P>SOLUTION: The printed wiring board 10 incorporating a semiconductor chip includes: a first substrate 100 formed with a plurality of connection pads; a semiconductor chip 400 connected onto the plurality of connection pads 160 on the first substrate 100; a metal case 500 covering the semiconductor chip in cooperation with the first substrate 100; and a second substrate 200, 300 having the same height as an exposed surface of the metal case 500 in a state where it is laminated to the first substrate 100 and formed with a notch in a position where the metal case 500 is located. The exposed surface of the metal case 500 is exposed, and the second substrate 200, 300 is laminated to the first substrate 100. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、ベアチップ等の半導体チップを内蔵するプリント配線板およびその製造方法に関する。   The present invention relates to a printed wiring board incorporating a semiconductor chip such as a bare chip and a method for manufacturing the same.

プリント配線板上にベアチップ等の半導体チップを実装する場合、プリント配線板の厚さにベアチップの厚さが加算されるため、ベアチップを実装する基板の厚さが厚くなると言う問題があった。   When a semiconductor chip such as a bare chip is mounted on the printed wiring board, the thickness of the bare chip is added to the thickness of the printed wiring board.

これを解決するために、多層プリント配線板にベアチップを内蔵して実装する構造が発明されている（例えば、特許文献１、特許文献２を参照）。しかしながら、多層プリント配線板では、基板層間を接続するための層間接着材料（例えば、エポキシ系樹脂）がベアチップに流れ込むことになり、層間接着材料によってベアチップが覆れることになってしまう虞があった。この場合、ベアチップに接着された層間接着材料が温度変化により悪影響を及ぼし、例えば層間接着材料とベアチップの熱膨張の差による応力がベアチップ及び、ベアチップとプリント配線板の接続部に加わり、亀裂等の破壊が生じる問題があった。   In order to solve this, a structure in which a bare chip is built in and mounted on a multilayer printed wiring board has been invented (see, for example, Patent Document 1 and Patent Document 2). However, in the multilayer printed wiring board, an interlayer adhesive material (for example, epoxy resin) for connecting between the substrate layers flows into the bare chip, and the bare chip may be covered with the interlayer adhesive material. . In this case, the interlayer adhesive material bonded to the bare chip has an adverse effect due to temperature change.For example, stress due to the difference in thermal expansion between the interlayer adhesive material and the bare chip is applied to the bare chip and the connection part between the bare chip and the printed wiring board, and cracks, etc. There was a problem that caused destruction.

特開２００５−１０１９７３号公報JP 2005-101973 A 特開２００２−１８４９３１号公報JP 2002-184931 A

本発明は、上記の問題を解決するためになされたもので、層間接着材料による悪影響のない半導体チップを内蔵するプリント配線板およびその製造方法を提供することを目的とする。   The present invention has been made to solve the above problems, and an object of the present invention is to provide a printed wiring board containing a semiconductor chip that is not adversely affected by an interlayer adhesive material, and a method for manufacturing the same.

上記目的を達成するために、本発明の半導体チップを内蔵するプリント配線板は、複数の接続パッドが形成される第１基板と、前記第１基板の前記複数の接続パッド上に接続される半導体チップと、前記第１基板と共同して前記半導体チップを覆う金属ケースと、前記第１基板に積層された状態では前記金属ケースの露出面と同じ高さを有し、かつ前記金属ケースが位置する箇所に切り欠き部が形成され、前記第１基板に積層される第２基板と、を有することを特徴とする。   In order to achieve the above object, a printed wiring board incorporating a semiconductor chip of the present invention includes a first substrate on which a plurality of connection pads are formed, and a semiconductor connected on the plurality of connection pads of the first substrate. A chip, a metal case that covers the semiconductor chip in cooperation with the first substrate, and the same height as the exposed surface of the metal case when stacked on the first substrate, and the metal case is positioned And a second substrate that is laminated on the first substrate.

また、本発明の半導体チップを内蔵するプリント配線板の製造方法は、複数の接続パッドが形成される第１基板の前記複数の接続パッド上に半導体チップを接続する工程と、前記半導体チップを覆うように前記第１基板に金属ケースを配置する工程と、前記第１基板に積層される状態では前記金属ケースの露出面と同じ高さを有し、かつ前記金属ケースが位置する箇所に切り欠き部が形成される第２基板を前記第１基板に積層する工程と、により製造することを特徴する。   According to another aspect of the invention, there is provided a method of manufacturing a printed wiring board including a semiconductor chip, the step of connecting the semiconductor chip on the plurality of connection pads of the first substrate on which the plurality of connection pads are formed, and covering the semiconductor chip. In this way, the metal case is disposed on the first substrate, and in the state of being stacked on the first substrate, the metal case has the same height as the exposed surface, and the metal case is notched at the position. And a step of laminating a second substrate on which the portion is formed on the first substrate.

本発明によれば、半導体チップを内蔵するプリント配線板の低背化を実現し、ベアチップ実装基板の信頼性向上することができる。また、ベアチップ実装基板のリワーク性と検査の作業性向上、並びに半導体チップを内蔵するプリント配線板の放熱性の向上を図ることができる。   According to the present invention, it is possible to reduce the height of a printed wiring board incorporating a semiconductor chip and improve the reliability of a bare chip mounting substrate. Further, the reworkability of the bare chip mounting substrate and the workability of the inspection can be improved, and the heat dissipation of the printed wiring board incorporating the semiconductor chip can be improved.

本実施形態に係る半導体チップを内蔵するプリント配線板を示す図。The figure which shows the printed wiring board which incorporates the semiconductor chip which concerns on this embodiment. 本実施形態に係る半導体チップを内蔵するプリント配線板の第１の製造工程を示す図。The figure which shows the 1st manufacturing process of the printed wiring board which incorporates the semiconductor chip which concerns on this embodiment. 本実施形態に係る半導体チップを内蔵するプリント配線板の第２の製造工程を示す図。The figure which shows the 2nd manufacturing process of the printed wiring board which incorporates the semiconductor chip which concerns on this embodiment. 本実施形態に係る半導体チップを内蔵するプリント配線板の第３の製造工程を示す図。The figure which shows the 3rd manufacturing process of the printed wiring board which incorporates the semiconductor chip which concerns on this embodiment.

以下、図面を参照しながら本発明の実施形態を説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（実施例）
図１は、本実施形態に係る半導体チップを内蔵するプリント配線板を示している。図１において、プリント配線板１００は、１層目及び２層目の配線を形成する第１基板である。プリント配線板２００は、３層目および４層目の配線を形成する第２基板である。プリント配線板３００は、５層目および６層目の配線を形成する第３基板である。なお、本実施形態では６層配線としたが、これに限定されるものではなく、少なくとも３層配線以上の多層プリント配線板であれば良い。 (Example)
FIG. 1 shows a printed wiring board incorporating a semiconductor chip according to the present embodiment. In FIG. 1, a printed wiring board 100 is a first substrate on which first and second layer wirings are formed. The printed wiring board 200 is a second substrate on which third and fourth layer wirings are formed. The printed wiring board 300 is a third substrate on which fifth and sixth layer wirings are formed. In this embodiment, the six-layer wiring is used. However, the present invention is not limited to this, and any multilayer printed wiring board having at least three-layer wiring may be used.

ベアチップ４００は、上記多層プリント配線板１０に内蔵される半導体チップである。ベアチップ４００とプリント配線板１００の２層面との接続は、半田ボール４５０（例えば、フリップチップボールＦＣＢ）によって接続される。   The bare chip 400 is a semiconductor chip built in the multilayer printed wiring board 10. The bare chip 400 and the two-layer surface of the printed wiring board 100 are connected by solder balls 450 (for example, flip chip balls FCB).

金属ケース５００は、ベアチップ４００を覆うケースである。金属ケース５００は、上面から見た場合、例えば正方形の形状をなし、プリント配線板１００に向かって４方向に側壁部が形成されている。これにより、プリント配線板１００と金属ケース５００とによって形成された取り付け部に、ベアチップ４００が内蔵（密閉）される。金属ケース５００によってベアチップ４００を覆う際、金属ケース５００とベアチップ４００との間は、放熱用の金属ペースト６００が塗布されている。これにより、ベアチップ４００で発生した熱は、金属ペースト６００を介して金属ケース５００の露出面から放熱される構造となっている。   The metal case 500 is a case that covers the bare chip 400. When viewed from above, the metal case 500 has, for example, a square shape, and side walls are formed in four directions toward the printed wiring board 100. As a result, the bare chip 400 is built (sealed) in the attachment portion formed by the printed wiring board 100 and the metal case 500. When the bare chip 400 is covered with the metal case 500, a metal paste 600 for heat dissipation is applied between the metal case 500 and the bare chip 400. As a result, the heat generated in the bare chip 400 is dissipated from the exposed surface of the metal case 500 through the metal paste 600.

プリント配線板１００の１層面には、基板パッド１１０や，配線部１２０，１３０，１４０が形成されている。プリント配線板１００の２層面には、基板パッド１１０とスルーホール接続されている基板パッド１５０、およびベアチップ４００と接続する半田ボール４５０が載置される複数の接続パッド１６０が形成されている。   A substrate pad 110 and wiring portions 120, 130, and 140 are formed on the first layer surface of the printed wiring board 100. On the two-layer surface of the printed wiring board 100, a plurality of connection pads 160 on which board pads 150 that are through-hole connected to the board pads 110 and solder balls 450 that are connected to the bare chips 400 are placed are formed.

プリント配線板２００の３層面と４層面には、基板パッド２１０，２２０，２３０，２４０が形成されている。基板パッド２１０と２２０はスルーホール接続されており、また基板パッド２３０と２４０はスルーホール接続されている。   Substrate pads 210, 220, 230, and 240 are formed on the third layer surface and the fourth layer surface of the printed wiring board 200. The substrate pads 210 and 220 are through-hole connected, and the substrate pads 230 and 240 are through-hole connected.

プリント配線板３００の５層面と６層面には、基板パッド３２０，３３０，３４０，３５０、配線部３１０，３６０が形成されている。基板パッド３２０と３３０はスルーホール接続されており、また基板パッド３４０と３５０はスルーホール接続されている。例えば、基板パッド３２０と３３０は、スルーホール３７０により内部接続されている。   On the 5th and 6th layer surfaces of the printed wiring board 300, substrate pads 320, 330, 340, 350 and wiring portions 310, 360 are formed. The substrate pads 320 and 330 are through-hole connected, and the substrate pads 340 and 350 are through-hole connected. For example, the substrate pads 320 and 330 are internally connected by a through hole 370.

プリント配線板２００とプリント配線板３００のベアチップ４００が内蔵される箇所には、後述するキャビティ（切り欠き部）が形成されている。ここでは、プリント配線板２００とプリント配線板３００とが一体化した状態で、積層用接着剤７００（例えば、プリプレグ）によってプリント配線板１００に接続した構造としている。   A cavity (notch) to be described later is formed at a place where the bare chip 400 of the printed wiring board 200 and the printed wiring board 300 is built. Here, the printed wiring board 200 and the printed wiring board 300 are connected to the printed wiring board 100 by a laminating adhesive 700 (for example, prepreg) in a state where the printed wiring board 200 and the printed wiring board 300 are integrated.

本実施形態では、金属ケース５００の上蓋５００ａが、例えば図示しないヒンジ機構により開閉可能に多層プリント配線板１０に取り付けられている。また、金属ケース５００の上蓋５００ａに配線ライン５１０，５２０，５３０を形成してもよい。   In the present embodiment, the upper lid 500a of the metal case 500 is attached to the multilayer printed wiring board 10 so as to be opened and closed by, for example, a hinge mechanism (not shown). In addition, wiring lines 510, 520, and 530 may be formed on the upper lid 500a of the metal case 500.

次に、上述した半導体チップを内蔵する多層プリント配線板１０の製造方法を説明する。   Next, a method for manufacturing the multilayer printed wiring board 10 incorporating the semiconductor chip described above will be described.

図２は、本実施形態に係る半導体チップを内蔵する多層プリント配線板の第１の製造工程を示している。両面基板の１層目と２層目に基板パッドおよび配線部１１０乃至１５０を形成し、２層目に半田ボール４５０が載置される複数の接続パッド１６０を形成したプリント配線板１００の２層目の上に、半田ボール４５０が接続されるベアチップ４００を実装する。これにより、ベアチップ４００の半田ボール４５０とプリント配線板１００の複数の接続パッド１６０が接続される。   FIG. 2 shows a first manufacturing process of the multilayer printed wiring board incorporating the semiconductor chip according to the present embodiment. Two layers of the printed wiring board 100 in which substrate pads and wiring portions 110 to 150 are formed in the first layer and the second layer of the double-sided substrate, and a plurality of connection pads 160 on which the solder balls 450 are placed are formed in the second layer. A bare chip 400 to which the solder balls 450 are connected is mounted on the eyes. Thereby, the solder balls 450 of the bare chip 400 and the plurality of connection pads 160 of the printed wiring board 100 are connected.

図３は、本実施形態に係る半導体チップを内蔵するプリント配線板の第２の製造工程を示している。次に、ベアチップ４００を覆うように金属ケース５００をプリント配線板１００上に実装する。この際、金属ケース５００とベアチップ４００との間には、放熱用の金属ペースト６００が塗布される。これにより、ベアチップ４００で発生した熱は、金属ペースト６００を介して金属ケース５００の露出面から放熱される。また、ベアチップ４００をグランド接続することもできる。   FIG. 3 shows a second manufacturing process of the printed wiring board incorporating the semiconductor chip according to the present embodiment. Next, the metal case 500 is mounted on the printed wiring board 100 so as to cover the bare chip 400. At this time, a heat dissipating metal paste 600 is applied between the metal case 500 and the bare chip 400. Thereby, the heat generated in the bare chip 400 is radiated from the exposed surface of the metal case 500 through the metal paste 600. Further, the bare chip 400 can be grounded.

また、金属ケース５００内に不活性ガス（例えば、ヘリウム等）を充填し、ベアチップ４００を機密封止してもよい。これにより、ベアチップ４００に対する不正アクセスを確認することができ、ベアチップ実装基板の信頼性を向上することができる。   Alternatively, the metal case 500 may be filled with an inert gas (for example, helium), and the bare chip 400 may be sealed. Thereby, unauthorized access to the bare chip 400 can be confirmed, and the reliability of the bare chip mounting substrate can be improved.

図４は、本実施形態に係る半導体チップを内蔵するプリント配線板の第３の製造工程を示している。この工程では、図４の下側に示すように、プリント配線板１００に一体化したプリント配線板２００，３００が積層される。一体化したプリント配線板２００，３００は、金属ケース５００が実装されたプリント配線板１００（ベアチップ実装基板）に積層された状態では、金属ケース５００の上面（露出面）と同じ高さになる高さを有している。そして、積層する一体化したプリント配線板２００，３００のベアチップ４００を内蔵する箇所には、キャビティ６５０（切り欠き部）が形成されている。また、プリント配線板２００，３００を積層する際、プリント配線板２００とプリント配線板１００との間には層間接着材料７００（例えば、プリプレグ）が塗布される。   FIG. 4 shows a third manufacturing process of the printed wiring board incorporating the semiconductor chip according to this embodiment. In this step, as shown in the lower side of FIG. 4, the printed wiring boards 200 and 300 integrated with the printed wiring board 100 are laminated. The integrated printed wiring boards 200 and 300 are the same height as the upper surface (exposed surface) of the metal case 500 when stacked on the printed wiring board 100 (bare chip mounting substrate) on which the metal case 500 is mounted. Have A cavity 650 (notch portion) is formed at a place where the bare chip 400 of the integrated printed wiring boards 200 and 300 to be stacked is built. Further, when the printed wiring boards 200 and 300 are laminated, an interlayer adhesive material 700 (for example, prepreg) is applied between the printed wiring board 200 and the printed wiring board 100.

本実施形態では、層間接着材料７００は、金属ケース５００によって堰き止められる構造となっているので、ベアチップ４００が取り付けられている金属ケース５００内に流入することはない。したがって、ベアチップ４００に層間接着材料７００が付着することはなく、ベアチップ４００とプリント配線板１００の接続部に掛かる応力を心配する必要がない。   In the present embodiment, the interlayer adhesive material 700 is structured to be dammed by the metal case 500, and therefore does not flow into the metal case 500 to which the bare chip 400 is attached. Therefore, the interlayer adhesive material 700 does not adhere to the bare chip 400, and there is no need to worry about the stress applied to the connection portion between the bare chip 400 and the printed wiring board 100.

また、本実施形態では、図１に示すように金属ケース５００の上面の上蓋５００ａが開閉できる構造（上蓋構造）とすることもできる。このような開閉構造とすることにより、多層プリント配線板１０に内蔵するベアチップ４００のリワーク性を向上することができる。例えば、故障したベアチップを容易に交換することができる。また、ベアチップ４００の検査作業を容易に行うことができる。   Moreover, in this embodiment, as shown in FIG. 1, it can also be set as the structure (upper cover structure) which can open and close the upper cover 500a of the upper surface of the metal case 500. FIG. With such an open / close structure, the reworkability of the bare chip 400 built in the multilayer printed wiring board 10 can be improved. For example, a failed bare chip can be easily replaced. Further, the inspection work of the bare chip 400 can be easily performed.

更に、金属ケース５００の上蓋５００ａに配線を施すことにより、配線密度を向上させることができる。   Furthermore, wiring density can be improved by wiring the upper cover 500a of the metal case 500.

以上の説明の通り、本実施形態によれば、半導体チップを内蔵するプリント配線板の低背化を実現し、ベアチップ実装基板の信頼性向上することができる。また、ベアチップ実装基板のリワーク性と検査の作業性向上、並びに半導体チップを内蔵するプリント配線板の放熱性の向上を図ることができる。   As described above, according to the present embodiment, it is possible to reduce the height of the printed wiring board incorporating the semiconductor chip and improve the reliability of the bare chip mounting substrate. Further, the reworkability of the bare chip mounting substrate and the workability of the inspection can be improved, and the heat dissipation of the printed wiring board incorporating the semiconductor chip can be improved.

なお、本発明は上記実施形態に限定されることなく、本発明の要旨を逸脱しない範囲において適宜設計変更可能である。   The present invention is not limited to the above-described embodiment, and can be appropriately changed in design without departing from the gist of the present invention.

１００‥プリント配線板（第１基板）
２００‥プリント配線板（第２基板）
３００‥プリント配線板（第３基板）
１１０，１５０，２１０，２２０，２３０，２４０，３２０，３３０，３４０，３５‥基板パッド
１２０，１３０，１４０，３１０，３６０‥配線部
１６０‥接続パッド
４００‥半導体チップ（ベアチップ）
４５０‥半田ボール
５００‥金属ケース
６００‥放熱用の金属ペースト
６５０‥キャビティ（切り欠き部）
７００‥層間接着材料 100 ... Printed wiring board (first board)
200 ... Printed wiring board (second board)
300 ... Printed wiring board (third board)
110, 150, 210, 220, 230, 240, 320, 330, 340, 35 ... substrate pads 120, 130, 140, 310, 360 ... wiring part 160 ... connection pad 400 ... semiconductor chip (bare chip)
450 ... Solder ball 500 ... Metal case 600 ... Metal paste for heat dissipation 650 ... Cavity (notch)
700 ... Interlayer adhesive material

Claims (5)

複数の接続パッドが形成される第１基板と、
前記第１基板の前記複数の接続パッド上に接続される半導体チップと、
前記第１基板と共同して前記半導体チップを覆う金属ケースと、
前記第１基板に積層された状態では前記金属ケースの露出面と同じ高さを有し、かつ前記金属ケースが位置する箇所に切り欠き部が形成され、前記第１基板に積層される第２基板と、
を有することを特徴とする半導体チップを内蔵するプリント配線板。 A first substrate on which a plurality of connection pads are formed;
A semiconductor chip connected on the plurality of connection pads of the first substrate;
A metal case that covers the semiconductor chip in cooperation with the first substrate;
In a state of being stacked on the first substrate, a notch is formed at a location where the metal case is located and has the same height as the exposed surface of the metal case, and is stacked on the first substrate. A substrate,
A printed wiring board having a built-in semiconductor chip. 前記金属ケースの露出面は開閉可能に接続されていることを特徴とする請求項１に記載の半導体チップを内蔵するプリント配線板。   2. The printed wiring board with a built-in semiconductor chip according to claim 1, wherein the exposed surface of the metal case is connected to be openable and closable. 前記半導体チップと前記金属ケースの間には放熱用の金属ペーストが塗布されていることを特徴とする請求項１に記載の半導体チップを内蔵するプリント配線板。   2. The printed wiring board with a built-in semiconductor chip according to claim 1, wherein a metal paste for heat dissipation is applied between the semiconductor chip and the metal case. 前記半導体チップを覆った前記金属ケース内には不活性ガスが充填されていることを特徴とする請求項１に記載の半導体チップを内蔵するプリント配線板。   The printed wiring board with a built-in semiconductor chip according to claim 1, wherein the metal case covering the semiconductor chip is filled with an inert gas. 複数の接続パッドが形成される第１基板の前記複数の接続パッド上に半導体チップを接続する工程と、
前記半導体チップを覆うように前記第１基板に金属ケースを配置する工程と、
前記第１基板に積層される状態では前記金属ケースの露出面と同じ高さを有し、かつ前記金属ケースが位置する箇所に切り欠き部が形成される第２基板を前記第１基板に積層する工程と、
により製造することを特徴する半導体チップを内蔵するプリント配線板の製造方法。 Connecting a semiconductor chip on the plurality of connection pads of the first substrate on which the plurality of connection pads are formed;
Disposing a metal case on the first substrate so as to cover the semiconductor chip;
In the state of being stacked on the first substrate, a second substrate having the same height as the exposed surface of the metal case and having a notch formed at a location where the metal case is positioned is stacked on the first substrate. And a process of
A method of manufacturing a printed wiring board containing a semiconductor chip, characterized by being manufactured by the method described above.
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