JP2007324330A - Circuit board - Google Patents

Circuit board Download PDF

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JP2007324330A
JP2007324330A JP2006152078A JP2006152078A JP2007324330A JP 2007324330 A JP2007324330 A JP 2007324330A JP 2006152078 A JP2006152078 A JP 2006152078A JP 2006152078 A JP2006152078 A JP 2006152078A JP 2007324330 A JP2007324330 A JP 2007324330A
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Prior art keywords
layer
metal
lsi chip
circuit board
insulating layer
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JP2006152078A
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Inventor
Shinya Nakano
慎也 中野
Yasuhiro Obara
泰浩 小原
Shunichi Imaoka
俊一 今岡
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2006152078A priority Critical patent/JP2007324330A/en
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    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To restrain lowering of reliability caused by heat generation from a circuit element by raising heat dissipation of a circuit board. <P>SOLUTION: The circuit board has a wiring layer 20 consisting of a plurality of insulation layers 2, 4 and conductive layers 3, 5 on a metal plate 1, a solder resist layer 7 provided to partially cover the wiring layer 20, an LSI chip 9 provided on the solder resist layer 7 via an adhesion layer 8, and a plurality of metal protrusions 6a provided through the solder resist layer 7 and the adhesion layer 8 in a region below the LSI chip 9. The wiring layer 20 in a region below the LSI chip 9 is provided with a thermal via hole 3a of the conductive layer 3 and the thermal via hole 5a of the conductive layer 5. A plurality of metal protrusions 6a are provided to corresponding positions each on the thermal via hole 5a. The LSI chip 9 is thermally coupled to the metal plate 1 via the plurality of metal protrusions 6a and the thermal via holes 3a, 5a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、回路基板に関し、特に、金属板を備えた回路基板に関する。   The present invention relates to a circuit board, and particularly to a circuit board provided with a metal plate.

近年、ＬＳＩ（Large Scale Integrated Circuit：大規模集積回路）のさらなる高性能化、高機能化にともない、その消費電力は増加の傾向にある。また、電子機器の小型化にともなって、実装基板にも小型化、高密度化、多層化が求められている。このため、基板の体積当たりの消費電力（熱密度）は上昇し、その放熱対策の必要性が高まっている。このため、回路基板として高い放熱性を有する金属板を用いるとともに、その金属板上にＬＳＩなどの回路素子を装着している（たとえば、特許文献１参照）。   In recent years, with further increase in performance and functionality of LSI (Large Scale Integrated Circuit), power consumption has been increasing. Further, as electronic devices are downsized, mounting substrates are also required to be downsized, high density, and multi-layered. For this reason, the power consumption (heat density) per volume of the substrate is increased, and the necessity for heat radiation countermeasures is increasing. For this reason, a metal plate having high heat dissipation is used as a circuit board, and a circuit element such as an LSI is mounted on the metal plate (see, for example, Patent Document 1).

図１１は上記特許文献１に開示された従来の回路基板の構造を概略的に示した断面図である。図１１に示されるように、従来の回路基板は、金属板１０１と、金属板１０１上に設けられた複数の樹脂層（絶縁層）１０２，１０４並び導電層１０３，１０５からなる配線層１２０と、配線層１２０上に設けられたソルダーレジスト層１０６ａと、ソルダーレジスト層１０６ａ上に樹脂層（接着層）１０６を介して搭載されたＬＳＩチップ（回路素子）１０９とを備える。ここで、ＬＳＩチップ１０９の下方の領域には、ＬＳＩチップ１０９から発生した熱を導電層１０３に伝導するためのサーマルビア部１０５ａと、導電層１０５の熱を金属板１０１に伝導するためのサーマルビア部１０３ａとを有している。   FIG. 11 is a cross-sectional view schematically showing the structure of a conventional circuit board disclosed in Patent Document 1. As shown in FIG. 11, the conventional circuit board includes a metal plate 101, a plurality of resin layers (insulating layers) 102 and 104 provided on the metal plate 101, and a wiring layer 120 including conductive layers 103 and 105. A solder resist layer 106a provided on the wiring layer 120 and an LSI chip (circuit element) 109 mounted on the solder resist layer 106a via a resin layer (adhesive layer) 106 are provided. Here, in a region below the LSI chip 109, a thermal via portion 105a for conducting heat generated from the LSI chip 109 to the conductive layer 103, and a thermal for conducting heat of the conductive layer 105 to the metal plate 101 are provided. And a via portion 103a.

図１１に示した従来の回路基板では、ＬＳＩチップ１０９で発生した熱はこれらサーマルビア部１０３ａ，１０５ａを有する配線層１２０を介して金属板１０１に伝導されるので、ＬＳＩチップ１０９から多量の熱が発生したとしても、その熱を金属板１０１により放熱することが可能となる。   In the conventional circuit board shown in FIG. 11, heat generated in the LSI chip 109 is conducted to the metal plate 101 through the wiring layer 120 having the thermal via portions 103a and 105a. Even if this occurs, the heat can be dissipated by the metal plate 101.

さらに近年では、ＬＳＩチップからの熱をより効果的に金属板に放熱することが求められている。このため、回路素子からの熱を金属板に効率的に逃がすのに、回路素子と金属板との間の伝熱経路の熱伝導率を高めることが必要となる。この解決策の１つとして、配線層１２０上に設けられたソルダーレジスト層１０６ａや樹脂層（接着層）１０６に対して熱伝導率を高くするためのフィラーを添加する手法がある。
特開２００５−３４０５８１号公報 Furthermore, in recent years, it has been required to dissipate heat from the LSI chip more effectively to the metal plate. For this reason, in order to efficiently release heat from the circuit element to the metal plate, it is necessary to increase the thermal conductivity of the heat transfer path between the circuit element and the metal plate. One solution is to add a filler for increasing the thermal conductivity to the solder resist layer 106a or the resin layer (adhesive layer) 106 provided on the wiring layer 120.
JP 2005-340581 A

しかしながら、上記手法では、添加するフィラーの種類、粒径（寸法）や添加量などを調整しても熱伝導率の向上には一定の限界があった。   However, in the above method, there is a certain limit in improving the thermal conductivity even if the kind of filler to be added, the particle size (dimension), the added amount, and the like are adjusted.

本発明は上記事情を踏まえてなされたものであり、その目的は、回路基板の放熱性を高め、回路素子からの発熱に起因した信頼性の低下を抑制することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to enhance heat dissipation of a circuit board and to suppress a decrease in reliability due to heat generation from circuit elements.

上記目的を達成するために、本発明に係る回路基板は、基板と、基板上に設けられた絶縁層と、絶縁層内からその一端が突出して設けられた複数の金属突起と、絶縁層の表面から露出して設けられたワイヤ接続用電極と、を備え、金属突起の他端は基板と結合していることを特徴とする。   In order to achieve the above object, a circuit board according to the present invention includes a substrate, an insulating layer provided on the substrate, a plurality of metal protrusions having one end protruding from the insulating layer, and an insulating layer. And an electrode for wire connection provided exposed from the surface, and the other end of the metal protrusion is coupled to the substrate.

この発明によれば、金属突起の一端上に回路素子を設けた場合、回路素子から発生する熱が複数の金属突起を介して基板に伝導するようになるので、従来の金属突起を設けない場合に比べ、回路素子からの熱を基板へ放熱する際の熱抵抗が減少する。このため、回路基板としての放熱性が向上する。   According to the present invention, when the circuit element is provided on one end of the metal protrusion, the heat generated from the circuit element is conducted to the substrate through the plurality of metal protrusions, so that the conventional metal protrusion is not provided. In contrast, the thermal resistance when heat from the circuit element is radiated to the substrate is reduced. For this reason, the heat dissipation as a circuit board improves.

上記構成において、金属突起の少なくとも一部は第１の金属突起と第２の金属突起とを結合して構成され、絶縁層は第１の絶縁層とこの第１の絶縁層上に設けられた第２の絶縁層とを含み、第１の絶縁層には第１の金属突起が設けられ、第２の絶縁層には第２の金属突起が設けられていてもよい。この場合にも、回路素子から発生する熱が第１の金属突起および第２の金属突起を含む金属突起を介して基板に伝導するようになる。このため、従来の金属突起を設けない場合に比べ、回路基板としての放熱性が向上する。   In the above configuration, at least a part of the metal protrusion is configured by combining the first metal protrusion and the second metal protrusion, and the insulating layer is provided on the first insulating layer and the first insulating layer. A first metal protrusion may be provided on the first insulating layer, and a second metal protrusion may be provided on the second insulating layer. Also in this case, the heat generated from the circuit element is conducted to the substrate through the metal protrusion including the first metal protrusion and the second metal protrusion. For this reason, the heat dissipation as a circuit board improves compared with the case where the conventional metal protrusion is not provided.

上記構成において、金属突起の一端上に設けられた回路素子をさらに備え、回路素子はワイヤ線によってワイヤ接続用電極と電気的に接続されていてもよい。この場合、回路素子から発生する熱が複数の金属突起を介して基板に伝導するようになるので、回路素子からの発熱に起因する信頼性低下を抑制した回路基板が容易に提供される。   The said structure WHEREIN: The circuit element provided on the end of a metal protrusion is further provided, and the circuit element may be electrically connected with the electrode for wire connection by the wire wire. In this case, the heat generated from the circuit element is conducted to the substrate through the plurality of metal protrusions, so that it is possible to easily provide a circuit board in which a decrease in reliability due to heat generated from the circuit element is suppressed.

本発明によれば、回路素子からの発熱に起因した信頼性低下を抑制した回路基板が提供される。   ADVANTAGE OF THE INVENTION According to this invention, the circuit board which suppressed the reliability fall resulting from the heat_generation | fever from a circuit element is provided.

以下、本発明を具現化した実施形態について図面に基づいて説明する。なお、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。
（第１実施形態）
図１は本発明の第１実施形態に係る金属板を備えた回路基板の概略断面図である。図１に基づいて第１実施形態の回路基板について説明する。 DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.
(First embodiment)
FIG. 1 is a schematic cross-sectional view of a circuit board provided with a metal plate according to the first embodiment of the present invention. The circuit board according to the first embodiment will be described with reference to FIG.

第１実施形態の回路基板は、金属板１と、複数の絶縁層２，４並び導電層３，５からなる配線層２０と、金属突起６ａと、ソルダーレジスト層７と、接着層８と、ＬＳＩチップ９と、ワイヤ線１０と、及び封止樹脂層１１とを備えている。   The circuit board of the first embodiment includes a metal plate 1, a wiring layer 20 composed of a plurality of insulating layers 2, 4 and conductive layers 3, 5, a metal protrusion 6 a, a solder resist layer 7, an adhesive layer 8, An LSI chip 9, a wire 10, and a sealing resin layer 11 are provided.

金属板１は、たとえば、約１．５ｍｍの厚みを有する銅（Ｃｕ）基板を用いる。なお、この金属板１は本発明の「基板」の一例である。   For the metal plate 1, for example, a copper (Cu) substrate having a thickness of about 1.5 mm is used. The metal plate 1 is an example of the “substrate” in the present invention.

配線層２０は、金属板１の上に形成されており、絶縁層２，４と導電層３，５とが交互に２回積層された構造を有する。具体的な配線層２０の構造は以下の通りである。   The wiring layer 20 is formed on the metal plate 1 and has a structure in which the insulating layers 2 and 4 and the conductive layers 3 and 5 are alternately laminated twice. The specific structure of the wiring layer 20 is as follows.

金属板１の上面上に１層目の絶縁層２および導電層３が順次形成されている。この絶縁層２にはエポキシ樹脂を主成分とする膜が採用され、その厚さは、たとえば、約５５μｍである。絶縁層２は回路基板の放熱性向上の観点から高熱伝導性を有することが望ましい。このため、絶縁層２は、銀、ビスマス、銅、アルミニウム、マグネシウム、錫、亜鉛およびこれらの合金などやシリカ、アルミナ、窒化ケイ素、窒化アルミニウムなどの高熱伝導性フィラーを含有することが好ましい。たとえば、アルミナやシリカなどのフィラーが添加されたエポキシ樹脂の熱伝導率は、約２Ｗ／（ｍ・Ｋ）であり、フィラーが添加されていないエポキシ樹脂の熱伝導率（約０．６Ｗ／（ｍ・Ｋ））よりも高い。   A first insulating layer 2 and a conductive layer 3 are sequentially formed on the upper surface of the metal plate 1. The insulating layer 2 is a film mainly composed of an epoxy resin and has a thickness of about 55 μm, for example. The insulating layer 2 desirably has high thermal conductivity from the viewpoint of improving the heat dissipation of the circuit board. For this reason, the insulating layer 2 preferably contains silver, bismuth, copper, aluminum, magnesium, tin, zinc, and alloys thereof, and high thermal conductive fillers such as silica, alumina, silicon nitride, and aluminum nitride. For example, the thermal conductivity of an epoxy resin to which a filler such as alumina or silica is added is about 2 W / (m · K), and the thermal conductivity of an epoxy resin to which no filler is added (about 0.6 W / ( higher than m · K)).

絶縁層２にはＬＳＩチップ９の下方に位置する所定領域に、約７０μｍの直径（ビア径）を有するとともに、厚み方向に貫通する４つのビアホール２ａが形成されている。そして、絶縁層２上の所定領域には、サーマルビア部３ａと配線部３ｂ，３ｃとを含む１層目の銅からなる導電層３が形成されている。導電層３の膜厚は、たとえば、約２５μｍである。導電層３のサーマルビア部３ａは、ＬＳＩチップ９の下方の領域に配置されているとともに、金属板１の表面に接触するようにビアホール２ａ内に埋め込まれた部分を有する。この導電層３のサーマルビア部３ａは金属板１に熱を放熱する機能を有する。なお、ビアホール２ａ内に導電層３が埋め込まれた状態での絶縁層２の熱伝導率は約６Ｗ／（ｍ・Ｋ）〜約８Ｗ／（ｍ・Ｋ）である。また、導電層３の配線部３ｂ，３ｃはＬＳＩチップ９およびサーマルビア部３ａの周辺領域に配置されている。   In the insulating layer 2, four via holes 2 a having a diameter (via diameter) of about 70 μm and penetrating in the thickness direction are formed in a predetermined region located below the LSI chip 9. In a predetermined region on the insulating layer 2, a first conductive layer 3 made of copper including the thermal via portion 3a and the wiring portions 3b and 3c is formed. The film thickness of the conductive layer 3 is, for example, about 25 μm. The thermal via portion 3 a of the conductive layer 3 is disposed in a region below the LSI chip 9 and has a portion embedded in the via hole 2 a so as to contact the surface of the metal plate 1. The thermal via portion 3 a of the conductive layer 3 has a function of radiating heat to the metal plate 1. The thermal conductivity of the insulating layer 2 in a state where the conductive layer 3 is embedded in the via hole 2a is about 6 W / (m · K) to about 8 W / (m · K). Further, the wiring portions 3b and 3c of the conductive layer 3 are disposed in the peripheral region of the LSI chip 9 and the thermal via portion 3a.

次に、２層目の絶縁層４および導電層５が順次形成されている。２層目の絶縁層４は、絶縁層２と同じ組成を有する材料が採用され、導電層３を覆うように形成されている。絶縁層４の膜厚は、たとえば、約５５μｍである。絶縁層４にはＬＳＩチップ９の下方に位置する領域に、約７０μｍの直径を有するとともに、厚み方向に貫通する４つのビアホール４ａが形成されている。この４つのビアホール４ａはそれぞれ絶縁層２に形成された４つのビアホール２ａに対応する位置に形成されている。また、絶縁層４には、導電層３の配線部３ｂおよび３ｃに対応する領域に、約７０μｍの直径（ビア径）を有するとともに、絶縁層４を厚み方向に貫通するビアホール４ｂ，４ｃが形成されている。このビアホール４ｂ，４ｃは上下配線層を電気的に接続するコンタクトホールとしての機能を有する。そして、絶縁層４上の所定領域には、サーマルビア部５ａと配線部５ｂ〜５ｄとを含む２層目の導電層５が形成されている。導電層５の膜厚は、たとえば、約２０μｍである。導電層５には１層目の導電層３と同じ材料が採用されている。また、サーマルビア部５ａの４つのビアホール４ａに充填された部分は導電層３のサーマルビア部３ａの上面に接触している。この導電層５のサーマルビア部５ａはＬＳＩチップ９で発生した熱を導電層３のサーマルビア部３ａに伝導して放熱する機能を有する。また、導電層５の配線部５ｂ，５ｃのビアホール４ｂ，４ｃに充填された部分は導電層３の配線部３ｂ，３ｃの表面にそれぞれ接触している。なお、導電層５の配線部５ｂ，５ｃは本発明の「ワイヤ接続用電極」の一例である。   Next, a second insulating layer 4 and a conductive layer 5 are sequentially formed. The second insulating layer 4 is made of a material having the same composition as the insulating layer 2 and is formed so as to cover the conductive layer 3. The film thickness of the insulating layer 4 is, for example, about 55 μm. In the insulating layer 4, four via holes 4 a having a diameter of about 70 μm and penetrating in the thickness direction are formed in a region located below the LSI chip 9. The four via holes 4a are formed at positions corresponding to the four via holes 2a formed in the insulating layer 2, respectively. The insulating layer 4 has via holes 4b and 4c having a diameter (via diameter) of about 70 μm and penetrating the insulating layer 4 in the thickness direction in regions corresponding to the wiring portions 3b and 3c of the conductive layer 3. Has been. The via holes 4b and 4c function as contact holes that electrically connect the upper and lower wiring layers. A second conductive layer 5 including a thermal via portion 5a and wiring portions 5b to 5d is formed in a predetermined region on the insulating layer 4. The film thickness of the conductive layer 5 is about 20 μm, for example. The same material as that of the first conductive layer 3 is used for the conductive layer 5. Further, the portion filled in the four via holes 4 a of the thermal via portion 5 a is in contact with the upper surface of the thermal via portion 3 a of the conductive layer 3. The thermal via portion 5a of the conductive layer 5 has a function of conducting heat generated in the LSI chip 9 to the thermal via portion 3a of the conductive layer 3 to radiate heat. Further, the portions filled in the via holes 4b and 4c of the wiring portions 5b and 5c of the conductive layer 5 are in contact with the surfaces of the wiring portions 3b and 3c of the conductive layer 3, respectively. The wiring portions 5b and 5c of the conductive layer 5 are examples of the “wire connection electrode” in the present invention.

以上により、金属板１の上に２層構造の配線層２０が設けられた配線基板３０部分が構成される。なお、導電層３のサーマルビア部３ａおよび導電層５のサーマルビア部５ａからなる部分が配線層２０を貫通する伝熱部６ｂに相当する。   As described above, the wiring board 30 portion in which the wiring layer 20 having the two-layer structure is provided on the metal plate 1 is configured. Note that a portion formed of the thermal via portion 3 a of the conductive layer 3 and the thermal via portion 5 a of the conductive layer 5 corresponds to the heat transfer portion 6 b that penetrates the wiring layer 20.

金属突起６ａはソルダーレジスト層７および接着層８を貫通するように設けられている。この金属突起６ａの一端上にはＬＳＩチップ９が直に接するように搭載されている。このようにすることで、金属突起６ａの一端とＬＳＩチップ９とは熱的に結合した状態となる。図２は図１に示した回路基板の金属突起のレイアウトを表す平面図である。金属突起６ａは約７０μｍの直径（ビア径）を有する丸型に設けられ、複数の金属突起６ａのそれぞれは正方格子状に並べられている。金属突起間のピッチは約１４０μｍとしている。複数の金属突起６ａは上記配線層２０における導電層５のサーマルビア部５ａの上にそれぞれ対応する位置に設けられている。このようにすることで、金属突起６ａの他端とサーマルビア部５ａとは熱的に結合した状態、すなわち、金属突起６ａの他端と配線層２０を貫通する伝熱部６ｂとが熱的に結合された状態となる。なお、金属突起として丸型のものを採用したが、四角形などの多角形であってもよく、またそれらを組み合わせてもよい。また、金属突起の寸法もすべて同一の寸法である必要はなく、必要に応じて複数の寸法の金属突起を組み合わせてもよい。   The metal protrusion 6 a is provided so as to penetrate the solder resist layer 7 and the adhesive layer 8. An LSI chip 9 is mounted on one end of the metal protrusion 6a so as to be in direct contact therewith. By doing so, one end of the metal protrusion 6a and the LSI chip 9 are thermally coupled. FIG. 2 is a plan view showing a layout of metal protrusions of the circuit board shown in FIG. The metal protrusions 6a are provided in a round shape having a diameter (via diameter) of about 70 μm, and each of the plurality of metal protrusions 6a is arranged in a square lattice shape. The pitch between metal protrusions is about 140 μm. The plurality of metal protrusions 6 a are provided at positions corresponding to the thermal via portions 5 a of the conductive layer 5 in the wiring layer 20. By doing so, the other end of the metal protrusion 6a and the thermal via part 5a are thermally coupled, that is, the other end of the metal protrusion 6a and the heat transfer part 6b penetrating the wiring layer 20 are thermally connected. It becomes the state where it was combined with. In addition, although the round thing was employ | adopted as metal protrusion, polygons, such as a rectangle, may be sufficient, and they may be combined. Further, the metal protrusions need not all have the same dimension, and a plurality of metal protrusions having a plurality of dimensions may be combined as necessary.

ソルダーレジスト層７は、配線層２０の表面（絶縁層４と導電層５）を覆うように、導電層５の所定の部分（ＬＳＩチップ９とのワイヤボンディング接続に対応する部分）に開口部を有するように形成されている。このソルダーレジスト層７は、配線層２０（特に導電層５）の保護膜として機能する。ソルダーレジスト層７は、エポキシ樹脂などの熱硬化性樹脂が採用され、その膜厚は、たとえば、約２５μｍである。また、ソルダーレジスト層７にＳｉＯ２などのフィラーを添加してもよい。なお、配線層２０およびこのソルダーレジスト層７は本発明の「絶縁層」の一例である。   The solder resist layer 7 has an opening in a predetermined portion (corresponding to wire bonding connection with the LSI chip 9) of the conductive layer 5 so as to cover the surface of the wiring layer 20 (insulating layer 4 and conductive layer 5). It is formed to have. The solder resist layer 7 functions as a protective film for the wiring layer 20 (particularly the conductive layer 5). The solder resist layer 7 is made of a thermosetting resin such as an epoxy resin, and its film thickness is, for example, about 25 μm. Further, a filler such as SiO 2 may be added to the solder resist layer 7. The wiring layer 20 and the solder resist layer 7 are examples of the “insulating layer” in the present invention.

ＬＳＩチップ９は、複数の金属突起６ａの一端上に直に接して設けられ、このＬＳＩチップ９とソルダーレジスト層７との間に設けられた約５０μｍの厚みを有するエポキシ樹脂からなる接着層８によって固定されている。なお、ＬＳＩチップ９は本発明の「回路素子」の一例である。   The LSI chip 9 is provided in direct contact with one end of the plurality of metal protrusions 6a, and an adhesive layer 8 made of an epoxy resin having a thickness of about 50 μm provided between the LSI chip 9 and the solder resist layer 7. It is fixed by. The LSI chip 9 is an example of the “circuit element” in the present invention.

ワイヤ線１０は、金線やアルミ線などが採用され、配線層２０（金属突起６ａ）の上に搭載されたＬＳＩチップ９と導電層５（配線部５ｂ，５ｃ）とを電気的にワイヤボンディング接続している。   The wire line 10 employs a gold wire, an aluminum wire or the like, and electrically bonds the LSI chip 9 mounted on the wiring layer 20 (metal protrusion 6a) and the conductive layer 5 (wiring portions 5b and 5c). Connected.

封止樹脂層１１は、配線層２０（金属突起６ａ）の上に搭載されたＬＳＩチップ９を封止し、ＬＳＩチップ９を外界からの影響から保護している。封止樹脂層１１の材料は、たとえば、エポキシ樹脂などの熱硬化性の絶縁樹脂である。なお、封止樹脂層１１中には熱伝導性を高めるためのフィラーが添加されていてもよい。
（製造方法）
図３〜図６は、図１に示した本実施形態による回路基板の製造プロセスを説明するための断面図である。次に、図１、図３〜図６を参照して、本実施形態による回路基板の製造プロセスについて説明する。 The sealing resin layer 11 seals the LSI chip 9 mounted on the wiring layer 20 (metal protrusion 6a) and protects the LSI chip 9 from the influence from the outside. The material of the sealing resin layer 11 is, for example, a thermosetting insulating resin such as an epoxy resin. In addition, a filler for increasing thermal conductivity may be added to the sealing resin layer 11.
(Production method)
3 to 6 are cross-sectional views for explaining a manufacturing process of the circuit board according to the present embodiment shown in FIG. Next, the circuit board manufacturing process according to the present embodiment will be described with reference to FIGS. 1 and 3 to 6.

まず、図３（Ａ）に示すように、約１．５ｍｍの厚みを有する金属板１を用意する。この金属板１上に絶縁層２と銅箔３ｚからなる積層膜を圧着することによって、約５５μｍの厚みを有する絶縁層２と約１０μｍの厚みを有する銅箔３ｚを形成する。絶縁層２には先に示したエポキシ樹脂を主成分とする膜が採用される。   First, as shown in FIG. 3A, a metal plate 1 having a thickness of about 1.5 mm is prepared. A laminated film composed of the insulating layer 2 and the copper foil 3z is pressure-bonded on the metal plate 1, thereby forming the insulating layer 2 having a thickness of about 55 μm and the copper foil 3z having a thickness of about 10 μm. The insulating layer 2 employs a film mainly composed of the epoxy resin described above.

図３（Ｂ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いてビアホール２ａ（図１参照）の形成領域に位置する銅箔３ｚを除去する。これにより、絶縁層２のビアホール２ａの形成領域が露出される。   As shown in FIG. 3B, the copper foil 3z located in the formation region of the via hole 2a (see FIG. 1) is removed using a photolithography technique and an etching technique. Thereby, the formation region of the via hole 2a of the insulating layer 2 is exposed.

図３（Ｃ）に示すように、銅箔３ｚの上方から炭酸ガスレーザまたはＵＶレーザを照射することによって、絶縁層２の露出した表面から金属板１の表面に達するまでの領域を除去する。これにより、絶縁層２に、約７０μｍの直径を有し、絶縁層２を貫通する４つのビアホール２ａを形成する。   As shown in FIG. 3C, the region from the exposed surface of the insulating layer 2 to the surface of the metal plate 1 is removed by irradiating a carbon dioxide laser or UV laser from above the copper foil 3z. Thus, four via holes 2 a having a diameter of about 70 μm and penetrating the insulating layer 2 are formed in the insulating layer 2.

図３（Ｄ）に示すように、無電解めっき法を用いて、銅箔３ｚの表面およびビアホール２ａの内面上に銅を約０．５μｍの厚みでめっきする。続いて、電解めっき法を用いて、銅箔３ｚの表面およびビアホール２ａの内部に銅をめっきする。なお、本実施形態では、めっき液中に抑制剤および促進剤を添加することによって、抑制剤を銅箔３ｚの表面上に吸着させるとともに、促進剤をビアホール２ａの内面上に吸着させる。これにより、ビアホール２ａの内面上の銅めっきの厚みを大きくすることができるので、ビアホール２ａ内に銅を埋め込むことができる。その結果、図３（Ｄ）に示すように、絶縁層２上に約２５μｍの厚みを有する導電層３が形成されるとともに、ビアホール２ａ内に導電層３が埋め込まれる。   As shown in FIG. 3D, copper is plated to a thickness of about 0.5 μm on the surface of the copper foil 3z and the inner surface of the via hole 2a by using an electroless plating method. Subsequently, copper is plated on the surface of the copper foil 3z and the inside of the via hole 2a by using an electrolytic plating method. In this embodiment, by adding an inhibitor and an accelerator to the plating solution, the inhibitor is adsorbed on the surface of the copper foil 3z and the accelerator is adsorbed on the inner surface of the via hole 2a. Thereby, since the thickness of the copper plating on the inner surface of the via hole 2a can be increased, copper can be embedded in the via hole 2a. As a result, as shown in FIG. 3D, the conductive layer 3 having a thickness of about 25 μm is formed on the insulating layer 2, and the conductive layer 3 is embedded in the via hole 2a.

図３（Ｅ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いて、導電層３をパターニングする。これにより、サーマルビア部３ａと配線部３ｂ，３ｃとを含む所定の配線パターンを有する導電層３が形成される。   As shown in FIG. 3E, the conductive layer 3 is patterned using a photolithography technique and an etching technique. Thus, the conductive layer 3 having a predetermined wiring pattern including the thermal via portion 3a and the wiring portions 3b and 3c is formed.

次に、図４（Ａ）に示すように、１層目の導電層３が形成された金属板１上に、絶縁層４と銅箔５ｚからなる積層膜を圧着することによって、約５５μｍの厚みを有する絶縁層４と約１０μｍの厚みを有する銅箔５ｚを形成する。絶縁層４には、絶縁層２と同じ組成を有する材料が採用される。   Next, as shown in FIG. 4A, a laminated film composed of the insulating layer 4 and the copper foil 5z is pressure-bonded onto the metal plate 1 on which the first conductive layer 3 is formed, so as to have a thickness of about 55 μm. An insulating layer 4 having a thickness and a copper foil 5z having a thickness of about 10 μm are formed. A material having the same composition as that of the insulating layer 2 is used for the insulating layer 4.

図４（Ｂ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いてビアホール４ａ〜４ｃ（図１参照）の形成領域に位置する銅箔５ｚを除去する。これにより、絶縁層４のビアホール４ａ〜４ｃの形成領域が露出される。   As shown in FIG. 4B, the copper foil 5z located in the formation region of the via holes 4a to 4c (see FIG. 1) is removed using a photolithography technique and an etching technique. Thereby, the formation regions of the via holes 4a to 4c of the insulating layer 4 are exposed.

図４（Ｃ）に示すように、銅箔５ｚの上方から炭酸ガスレーザまたはＵＶレーザを照射することによって、絶縁層４の露出した表面から導電層３の表面に達するまでの領域を除去する。これにより、絶縁層４に、約７０μｍの直径（ビア径）を有し、絶縁層４を貫通するビアホール４ａ〜４ｃを形成する。   As shown in FIG. 4C, a region from the exposed surface of the insulating layer 4 to the surface of the conductive layer 3 is removed by irradiating a carbon dioxide laser or UV laser from above the copper foil 5z. As a result, via holes 4 a to 4 c having a diameter (via diameter) of about 70 μm and penetrating the insulating layer 4 are formed in the insulating layer 4.

図４（Ｄ）に示すように、無電解めっき法を用いて、銅箔５ｚの表面およびビアホール４ａ〜４ｃの内面上に銅を約０．５μｍの厚みでめっきする。続いて、電解めっき法を用いて、銅箔５ｚの上面およびビアホール４ａ〜４ｃの内部にめっきする。この際、めっき液中に抑制剤および促進剤を添加することによって、抑制剤を銅箔５ｚの表面上に吸着させるとともに、促進剤をビアホール４ａ〜４ｃの内面上に吸着させる。これにより、ビアホール４ａ〜４ｃの内面上の銅めっきの厚みを大きくすることができるので、ビアホール４ａ〜４ｃ内に銅を埋め込むことができる。その結果、絶縁層４上に約２０μｍの厚みを有する導電層５が形成されるとともに、ビアホール４ａ〜４ｃ内に導電層５が埋め込まれる。   As shown in FIG. 4D, copper is plated to a thickness of about 0.5 μm on the surface of the copper foil 5z and the inner surfaces of the via holes 4a to 4c by using an electroless plating method. Subsequently, the upper surface of the copper foil 5z and the inside of the via holes 4a to 4c are plated using an electrolytic plating method. At this time, by adding an inhibitor and an accelerator to the plating solution, the inhibitor is adsorbed on the surface of the copper foil 5z, and the accelerator is adsorbed on the inner surfaces of the via holes 4a to 4c. Thereby, since the thickness of the copper plating on the inner surfaces of the via holes 4a to 4c can be increased, copper can be embedded in the via holes 4a to 4c. As a result, a conductive layer 5 having a thickness of about 20 μm is formed on the insulating layer 4, and the conductive layer 5 is embedded in the via holes 4a to 4c.

次に、図５（Ａ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いて導電層５をパターニングする。これにより、複数のサーマルビア部５ａと配線部５ｂ〜５ｄとを含む所定の配線パターンを有する導電層５が形成される。この結果、金属板１上に絶縁層２，４と導電層３，５とが交互に２回積層された配線層２０が形成される。なお、この配線層２０には、導電層３のサーマルビア部３ａと導電層５のサーマルビア部５ａからなる伝熱部６ｂが形成されている。   Next, as shown in FIG. 5A, the conductive layer 5 is patterned using a photolithography technique and an etching technique. Thereby, the conductive layer 5 having a predetermined wiring pattern including the plurality of thermal via portions 5a and the wiring portions 5b to 5d is formed. As a result, the wiring layer 20 in which the insulating layers 2 and 4 and the conductive layers 3 and 5 are alternately laminated twice is formed on the metal plate 1. The wiring layer 20 is formed with a heat transfer portion 6 b including a thermal via portion 3 a of the conductive layer 3 and a thermal via portion 5 a of the conductive layer 5.

図５（Ｂ）に示すように、金属突起６ａ（図１参照）の形成領域に位置する部分に開口部を有するレジストマスク（図示せず）を形成した後、電解めっき法によりこの開口部に銅からなる金属突起６ａを選択的に形成する。その後、レジストマスクを除去することにより、図５（Ｂ）に示したように、導電層５のサーマルビア部５ａの上に複数の金属突起６ａが形成される。金属突起６ａの高さは、たとえば、約７５μｍとした。これにより、
金属突起６ａの他端が導電層５のサーマルビア部５ａと直に結合した状態となる。なお、金属突起６ａの配置に関しては先に図２を参照して述べた通りである。 As shown in FIG. 5B, after forming a resist mask (not shown) having an opening in a portion located in the formation region of the metal protrusion 6a (see FIG. 1), the opening is formed in the opening by electrolytic plating. A metal protrusion 6a made of copper is selectively formed. Thereafter, by removing the resist mask, a plurality of metal protrusions 6a are formed on the thermal via portion 5a of the conductive layer 5, as shown in FIG. The height of the metal protrusion 6a was, for example, about 75 μm. This
The other end of the metal protrusion 6 a is directly coupled to the thermal via portion 5 a of the conductive layer 5. The arrangement of the metal protrusions 6a is as described above with reference to FIG.

図５（Ｃ）に示すように、配線層２０の表面（絶縁層４と導電層５）を覆うように、導電層５の所定の部分（ＬＳＩチップ９とのワイヤボンディング接続に対応する部分）に開口部を有するようにソルダーレジスト層７を形成する。ソルダーレジスト層７には先に示した材料を採用している。ソルダーレジスト層７の膜厚は、たとえば、約２５μｍである。以上の工程により、ソルダーレジスト層７内から複数の金属突起６ａの一端が突出した状態となる。   As shown in FIG. 5C, a predetermined portion of the conductive layer 5 (corresponding to wire bonding connection with the LSI chip 9) so as to cover the surface of the wiring layer 20 (insulating layer 4 and conductive layer 5). The solder resist layer 7 is formed so as to have an opening. The solder resist layer 7 is made of the materials described above. The film thickness of the solder resist layer 7 is, for example, about 25 μm. Through the above steps, one end of the plurality of metal protrusions 6a protrudes from the solder resist layer 7.

次に、図６（Ａ）に示すように、複数の金属突起６ａ上にＬＳＩチップ９を直に接するように装着する。この際、ＬＳＩチップ９は、このＬＳＩチップ９とソルダーレジスト層７との間に約５０μｍの厚みを有するエポキシ樹脂からなる接着層８を塗布形成することによって固定される。なお、ＬＳＩチップ９としてはその上面にパッド電極（図示せず）を備えている。   Next, as shown in FIG. 6A, the LSI chip 9 is mounted so as to be in direct contact with the plurality of metal protrusions 6a. At this time, the LSI chip 9 is fixed by applying and forming an adhesive layer 8 made of an epoxy resin having a thickness of about 50 μm between the LSI chip 9 and the solder resist layer 7. The LSI chip 9 has a pad electrode (not shown) on the upper surface.

図６（Ｂ）に示すように、ワイヤ線１０を用いてＬＳＩチップ９のパッド電極と導電層５とをワイヤボンディング接続する。これにより、ＬＳＩチップ９と配線層２０（導電層５）とが電気的に接続される。   As shown in FIG. 6B, the wire electrode 10 is used to connect the pad electrode of the LSI chip 9 and the conductive layer 5 by wire bonding. As a result, the LSI chip 9 and the wiring layer 20 (conductive layer 5) are electrically connected.

最後に、図１に示すように、配線層２０（金属突起６ａ）上に設けられたＬＳＩチップ９を保護するために、ＬＳＩチップ９を覆うようにエポキシ樹脂からなる封止樹脂層１１を形成する。   Finally, as shown in FIG. 1, in order to protect the LSI chip 9 provided on the wiring layer 20 (metal protrusion 6a), a sealing resin layer 11 made of an epoxy resin is formed so as to cover the LSI chip 9. To do.

これらの工程により、第１実施形態の回路基板を得ることができる。   Through these steps, the circuit board of the first embodiment can be obtained.

以上説明した第１実施形態の回路基板によれば、以下のような効果を得ることができるようになる。
（１）ＬＳＩチップ９から発生する熱が複数の金属突起６ａを介して配線層２０（金属板１）に伝導するようになるので、従来の金属突起を設けない場合に比べ、ＬＳＩチップ９からの熱を配線層２０（金属板１）へ放熱する際の熱抵抗が減少する。このため、回路基板としての放熱性が向上する。
（２）金属突起６ａの他端が配線層２０を貫通して金属板１の表面に接触するように設けられた伝熱部６ｂと熱的に結合したことで、ＬＳＩチップ９からの熱が金属突起６ａおよび伝熱部６ｂを介して金属板１に伝導することになるので、回路基板としての放熱性が向上する。
（３）ＬＳＩチップ９から発生する熱が複数の金属突起６ａおよび伝熱部６ｂを介して金属板１に伝導するようになるので、ＬＳＩチップ９からの発熱に起因する信頼性低下を抑制した回路基板が容易に提供される。
（４）金属突起６ａとＬＳＩチップ９との接続面を配線層２０の最上層となる導電層５よりも上側に位置するようにしたことで、金属突起６ａを接地した場合には、ＬＳＩチップ９からのノイズを金属突起６ａにより吸収し、低減することができる。このため、ＬＳＩチップ９近傍に設けられた導電層５への影響（たとえば、ＬＳＩチップ９近傍の導電層５と電磁的に干渉して回路基板の動作性能に変動を生じさせる）を抑制することができる。特に、ＬＳＩチップ９の下方領域に導電層５を設ける場合には、その周囲を複数の金属突起６ａが取り囲むので、ノイズ抑制効果を顕著に享受することができる。また、これとは反対に導電層５からＬＳＩチップ９への影響も同様に抑制することができる。
（５）複数の金属突起６ａ（および伝熱部６ｂ）を正方格子状に並べて均一に配置したことにより、ＬＳＩチップ９に局所的な発熱箇所が存在する場合でも熱を効率的に配線層２０（金属板１）に放熱することが可能となる。
（６）複数の金属突起６ａを正方格子状に並べて均一に配置したことにより、ＬＳＩチップ９と金属突起６ａとの界面に接着層８の残膜が介在することが抑制されるため、ＬＳＩチップ９と金属突起６ａとをより確実に結合した状態とすることができる。
（７）ＬＳＩチップ９との熱的な結合を複数の金属突起６ａにより行い、個々の金属突起６ａの周囲に接着層８を設けたことにより、金属突起６ａとＬＳＩチップ９との密着性が向上するので、回路基板の信頼性が向上する。
（８）金属突起６ａおよび導電層５を同一の材料により構成したことで、金属突起６ａおよび導電層５を同一のプロセス（電解めっき法）を用いて形成することができるので、放熱性の向上した回路基板を容易に形成することができる。
（第２実施形態）
図７は本発明の第２実施形態に係る金属板を備えた回路基板の概略断面図である。第１実施形態と異なる箇所は、金属突起６ａ１部分が導電層５（サーマルビア部５ａ１）と一体的に形成されていることである。それ以外については、先の第１実施形態と同様である。 According to the circuit board of the first embodiment described above, the following effects can be obtained.
(1) Since the heat generated from the LSI chip 9 is conducted to the wiring layer 20 (metal plate 1) through the plurality of metal protrusions 6a, the LSI chip 9 is compared with the case where no conventional metal protrusion is provided. The heat resistance when heat of heat is radiated to the wiring layer 20 (metal plate 1) is reduced. For this reason, the heat dissipation as a circuit board improves.
(2) Since the other end of the metal protrusion 6a is thermally coupled to the heat transfer portion 6b provided so as to pass through the wiring layer 20 and contact the surface of the metal plate 1, the heat from the LSI chip 9 is increased. Since it conducts to the metal plate 1 through the metal protrusion 6a and the heat transfer part 6b, the heat dissipation as a circuit board is improved.
(3) Since heat generated from the LSI chip 9 is conducted to the metal plate 1 through the plurality of metal protrusions 6a and the heat transfer portions 6b, a decrease in reliability due to heat generation from the LSI chip 9 is suppressed. A circuit board is easily provided.
(4) Since the connection surface between the metal protrusion 6a and the LSI chip 9 is positioned above the conductive layer 5 which is the uppermost layer of the wiring layer 20, when the metal protrusion 6a is grounded, the LSI chip 9 can be absorbed and reduced by the metal protrusion 6a. For this reason, the influence on the conductive layer 5 provided in the vicinity of the LSI chip 9 (for example, electromagnetic interference with the conductive layer 5 in the vicinity of the LSI chip 9 causes fluctuation in the operation performance of the circuit board) is suppressed. Can do. In particular, when the conductive layer 5 is provided in the lower region of the LSI chip 9, since the plurality of metal protrusions 6a surround the periphery of the conductive layer 5, a noise suppression effect can be remarkably enjoyed. On the contrary, the influence on the LSI chip 9 from the conductive layer 5 can be similarly suppressed.
(5) By arranging the plurality of metal protrusions 6a (and the heat transfer portions 6b) in a square lattice pattern and arranging them uniformly, even when a local heat generation location exists in the LSI chip 9, the heat is efficiently transmitted. It becomes possible to radiate heat to (metal plate 1).
(6) Since the plurality of metal protrusions 6a are arranged in a square lattice pattern and uniformly arranged, the residual film of the adhesive layer 8 is suppressed from being interposed at the interface between the LSI chip 9 and the metal protrusion 6a. 9 and the metal protrusion 6a can be more reliably combined.
(7) The thermal bonding with the LSI chip 9 is performed by the plurality of metal protrusions 6a, and the adhesive layer 8 is provided around each metal protrusion 6a, so that the adhesion between the metal protrusions 6a and the LSI chip 9 is improved. As a result, the reliability of the circuit board is improved.
(8) Since the metal protrusion 6a and the conductive layer 5 are made of the same material, the metal protrusion 6a and the conductive layer 5 can be formed by using the same process (electrolytic plating method), so that heat dissipation is improved. The circuit board thus formed can be easily formed.
(Second Embodiment)
FIG. 7 is a schematic cross-sectional view of a circuit board provided with a metal plate according to a second embodiment of the present invention. The difference from the first embodiment is that the metal protrusion 6a1 portion is formed integrally with the conductive layer 5 (thermal via portion 5a1). The rest is the same as in the first embodiment.

まず、先の図４（Ｃ）において絶縁層４にビアホール４ａ〜４ｃが形成された構造体を用意する。   First, a structure in which via holes 4a to 4c are formed in the insulating layer 4 in FIG. 4C is prepared.

次に、図８（Ａ）に示すように、先の図４（Ｄ）における導電層５の形成工程と同様の手法で絶縁層４上に約７５μｍの厚みを有する導電層５を形成する。   Next, as shown in FIG. 8A, the conductive layer 5 having a thickness of about 75 μm is formed on the insulating layer 4 by the same method as the step of forming the conductive layer 5 in FIG.

図８（Ｂ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いて第１回目の導電層５のエッチングを行い、金属突起６ａ１を形成する。金属突起６ａ１の高さはエッチング量により制御され、この場合には、突起電極６ａ１の高さが約５５μｍとなるようにエッチングしている。   As shown in FIG. 8B, the first conductive layer 5 is etched using a photolithography technique and an etching technique to form a metal protrusion 6a1. The height of the metal protrusion 6a1 is controlled by the etching amount, and in this case, the etching is performed so that the height of the protrusion electrode 6a1 is about 55 μm.

図８（Ｃ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いて第２回目の導電層５のエッチングを行い、サーマルビア部５ａ１と配線部５ｂ１〜５ｄ１とを含む所定の配線パターンを有する導電層５をパターニング形成する。この結果、サーマルビア部５ａ１と金属突起６ａ１とが一体的に形成された導電層５が形成される。   As shown in FIG. 8C, the second conductive layer 5 is etched by using the photolithography technique and the etching technique to have a predetermined wiring pattern including the thermal via part 5a1 and the wiring parts 5b1 to 5d1. The conductive layer 5 is formed by patterning. As a result, the conductive layer 5 in which the thermal via portion 5a1 and the metal protrusion 6a1 are integrally formed is formed.

これ以降の形成工程は、先に示した図５（Ｃ）以降の工程と同様である。これらの工程を経た結果、第２実施形態の回路基板を得ることができる。   The subsequent formation process is the same as the process after FIG. 5C described above. As a result of these steps, the circuit board of the second embodiment can be obtained.

この第２実施形態の回路基板によれば、先に示した第１実施形態での効果に加え、以下のような効果を得ることができるようになる。
（９）金属突起６ａ１が導電層５のサーマルビア部５ａ１と一体的に形成されているので、ＬＳＩチップ９からの熱が金属突起６ａ１を介して伝導する際、これに伴う応力に起因した金属突起６ａ１とサーマルビア部５ａ１との界面での剥離が生じない。このため、回路基板としての信頼性が向上する。 According to the circuit board of the second embodiment, the following effects can be obtained in addition to the effects of the first embodiment described above.
(9) Since the metal protrusion 6a1 is integrally formed with the thermal via portion 5a1 of the conductive layer 5, when heat from the LSI chip 9 is conducted through the metal protrusion 6a1, the metal caused by the stress accompanying this No peeling occurs at the interface between the protrusion 6a1 and the thermal via portion 5a1. For this reason, the reliability as a circuit board improves.

なお、上記実施形態では、金属板１に対して複数の金属突起６ａをそれぞれ独立した状態での例を示したが、本発明はこれに限らず、金属突起６ａ同士が部分的に接続されていてもよい。たとえば、図９に示すように、絶縁層２および絶縁層４の上面上に設けたサーマルビア部３ａ１およびサーマルビア部５ａ２をそれぞれ一体的に設けてもよい。この場合、伝熱部６ｂ１としてもより一体化されるため、ＬＳＩチップ９と金属板１との熱的な結合がより増強されるので、回路基板としての放熱性がさらに向上する。   In the above embodiment, the example in which the plurality of metal protrusions 6a are independent from each other with respect to the metal plate 1 has been described. However, the present invention is not limited to this, and the metal protrusions 6a are partially connected to each other. May be. For example, as shown in FIG. 9, the thermal via portion 3a1 and the thermal via portion 5a2 provided on the upper surfaces of the insulating layer 2 and the insulating layer 4 may be integrally provided. In this case, since the heat transfer portion 6b1 is further integrated, the thermal coupling between the LSI chip 9 and the metal plate 1 is further enhanced, so that heat dissipation as a circuit board is further improved.

上記実施形態では、金属突起６ａはソルダーレジスト層７と接着層８とを貫通して設けた例を示したが、本発明はこれに限らず、たとえば、図１０に示すように、ＬＳＩチップ９の搭載領域にソルダーレジスト層７ａを設けず、金属突起６ａ２が接着層８ａのみを貫通するように設けてもよい。この場合、ＬＳＩチップ９と配線層２０（金属板１）との間隔をより短くすることができるので、両者間の熱的な結合がより増強され、回路基板としての放熱性がさらに向上する。   In the above embodiment, the metal protrusion 6a is provided so as to penetrate the solder resist layer 7 and the adhesive layer 8. However, the present invention is not limited to this, for example, as shown in FIG. Alternatively, the solder resist layer 7a may not be provided in the mounting region, and the metal protrusion 6a2 may be provided so as to penetrate only the adhesive layer 8a. In this case, since the distance between the LSI chip 9 and the wiring layer 20 (metal plate 1) can be shortened, the thermal coupling between the two is further enhanced, and the heat dissipation as a circuit board is further improved.

上記実施形態では、金属突起６ａとＬＳＩチップ９とがすべて接続した例を示したが、本発明はこれに限らず、たとえば、金属突起の少なくとも一部がＬＳＩチップ９と接続されていればよい。この場合、その部分において金属突起を介して熱が放熱されるので、少なくとも上記（１）〜（３）の効果を享受することができる。   In the above-described embodiment, an example in which the metal protrusions 6a and the LSI chip 9 are all connected is shown. However, the present invention is not limited to this, and for example, at least a part of the metal protrusions may be connected to the LSI chip 9. . In this case, since heat is radiated through the metal protrusions at that portion, at least the effects (1) to (3) can be enjoyed.

上記実施形態では、金属突起６ａの直下に、導電層３のサーマルビア部３ａおよび導電層５のサーマルビア部５ａを設けた例を示したが、本発明はこれに限らず、たとえば、導電層３もしくは導電層５を引き回すことによって金属突起６ａの直下以外（たとえば、ＬＳＩチップ９の周辺近傍）に設けられていてもよい。この場合、放熱経路に関する設計レイアウトの自由度が向上するので、回路基板の低コスト化を実現できる。   In the above embodiment, the example in which the thermal via portion 3a of the conductive layer 3 and the thermal via portion 5a of the conductive layer 5 are provided immediately below the metal protrusion 6a has been described. However, the present invention is not limited thereto, and for example, a conductive layer 3 or the conductive layer 5 may be provided other than directly below the metal protrusion 6a (for example, near the periphery of the LSI chip 9). In this case, the degree of freedom in the design layout regarding the heat dissipation path is improved, and thus the cost of the circuit board can be reduced.

上記実施形態では、金属板１として銅単層板を適用したが、たとえば、銅からなる下層金属層と、下層金属層上に形成されたＦｅ−Ｎｉ系合金（いわゆるインバー合金）からなる中間金属層と、中間金属層上に形成された銅からなる上層金属層とが積層されたクラッド材によって構成されていてもよい。この場合、下層金属層、中間金属層、上層金属層の厚みを調整することにより、これら積層金属板の熱膨張係数を制御することができる。これにより、金属板の熱膨張係数が絶縁層の熱膨張係数に近づくように、各金属層の厚みを調節すれば、金属板と絶縁層との間の熱膨張係数差に起因して、配線層（絶縁層）が金属板から剥離するのを抑制することができる。   In the said embodiment, although the copper single layer board was applied as the metal plate 1, For example, the intermediate metal which consists of a lower layer metal layer which consists of copper, and the Fe-Ni type alloy (what is called an Invar alloy) formed on the lower layer metal layer You may be comprised by the clad material by which the layer and the upper metal layer which consists of copper formed on the intermediate metal layer were laminated | stacked. In this case, the thermal expansion coefficient of these laminated metal plates can be controlled by adjusting the thicknesses of the lower metal layer, the intermediate metal layer, and the upper metal layer. As a result, if the thickness of each metal layer is adjusted so that the thermal expansion coefficient of the metal plate approaches the thermal expansion coefficient of the insulating layer, the wiring is caused by the difference in the thermal expansion coefficient between the metal plate and the insulating layer. It can suppress that a layer (insulating layer) peels from a metal plate.

上記実施形態では、２層構造の配線層２０における例を示したが、本発明はこれに限らず、たとえば、単層構造あるいは３層以上の構造を有する配線層にも適用可能である。   In the above embodiment, the example in the wiring layer 20 having the two-layer structure has been described. However, the present invention is not limited to this, and can be applied to, for example, a wiring layer having a single-layer structure or a structure having three or more layers.

上記実施形態では、ＬＳＩチップが装着された回路基板に本発明を適用したが、本発明はこれに限らず、ＬＳＩチップ以外の回路素子が装着された回路基板にも適用可能である。たとえば、キャパシタや抵抗などの受動素子であってもよい。   In the above embodiment, the present invention is applied to the circuit board on which the LSI chip is mounted. However, the present invention is not limited to this, and can be applied to a circuit board on which circuit elements other than the LSI chip are mounted. For example, a passive element such as a capacitor or a resistor may be used.

上記実施形態では、金属突起６ａが配線層２０内に設けられた伝熱部６ｂと結合した例を示したが、本発明はこれに限らず、金属突起６ａと金属板１とを直に結合するようにしてもよい。また、金属突起６ａが金属板１と直に結合するものと、伝熱部６ｂを介して結合するものとを組み合わせてもよい。   In the above embodiment, an example in which the metal protrusion 6a is coupled to the heat transfer portion 6b provided in the wiring layer 20 has been described. However, the present invention is not limited to this, and the metal protrusion 6a and the metal plate 1 are directly coupled. You may make it do. Moreover, you may combine what the metal protrusion 6a couple | bonds directly with the metal plate 1, and what couple | bonds via the heat-transfer part 6b.

上記実施形態では、金属板１の一方の面側に金属突起６ａ（配線層２０およびＬＳＩチップ９を含む）を設けた例を示したが、本発明はこれに限らず、金属板１の他方の面側を含む両側に金属突起をそれぞれ設け、各金属突起の上にＬＳＩチップを搭載していてもよい。   In the above embodiment, an example in which the metal protrusion 6a (including the wiring layer 20 and the LSI chip 9) is provided on one surface side of the metal plate 1 has been described. Metal protrusions may be provided on both sides including the surface side, and an LSI chip may be mounted on each metal protrusion.

本発明の第１実施形態に係る金属板を備えた回路基板の概略断面図である。It is a schematic sectional drawing of the circuit board provided with the metal plate which concerns on 1st Embodiment of this invention. 図１に示した回路基板の金属突起のレイアウトを表す平面図である。It is a top view showing the layout of the metal protrusion of the circuit board shown in FIG. （Ａ）〜（Ｅ）図１に示した第１実施形態による回路基板の製造プロセスを説明するための断面図である。(A)-(E) It is sectional drawing for demonstrating the manufacturing process of the circuit board by 1st Embodiment shown in FIG. （Ａ）〜（Ｄ）図１に示した第１実施形態による回路基板の製造プロセスを説明するための断面図である。(A)-(D) It is sectional drawing for demonstrating the manufacturing process of the circuit board by 1st Embodiment shown in FIG. （Ａ）〜（Ｃ）図１に示した第１実施形態による回路基板の製造プロセスを説明するための断面図である。(A)-(C) It is sectional drawing for demonstrating the manufacturing process of the circuit board by 1st Embodiment shown in FIG. （Ａ），（Ｂ）図１に示した第１実施形態による回路基板の製造プロセスを説明するための断面図である。(A), (B) It is sectional drawing for demonstrating the manufacturing process of the circuit board by 1st Embodiment shown in FIG. 本発明の第２実施形態に係る金属板を備えた回路基板の概略断面図である。It is a schematic sectional drawing of the circuit board provided with the metal plate which concerns on 2nd Embodiment of this invention. （Ａ）〜（Ｃ）図７に示した第２実施形態による回路基板の製造プロセスを説明するための断面図である。(A)-(C) It is sectional drawing for demonstrating the manufacturing process of the circuit board by 2nd Embodiment shown in FIG. 第１実施形態の第１変形例に係る回路基板の概略断面図である。It is a schematic sectional drawing of the circuit board which concerns on the 1st modification of 1st Embodiment. 第１実施形態の第２変形例に係る回路基板の概略断面図である。It is a schematic sectional drawing of the circuit board which concerns on the 2nd modification of 1st Embodiment. 従来の回路基板の構造を概略的に示した断面図である。It is sectional drawing which showed the structure of the conventional circuit board roughly.

符号の説明Explanation of symbols

１・・・金属板、２・・・絶縁層、３・・・導電層、３ａ・・・サーマルビア部、３ｂ，３ｃ・・・配線部、４・・・絶縁層、５・・・導電層、５ａ・・・サーマルビア部、５ｂ〜５ｄ・・・配線部、６ａ・・・金属突起、６ｂ・・・伝熱部、７・・・ソルダーレジスト層、８・・・接着層、９・・・ＬＳＩチップ、１０・・・ワイヤ線、１１・・・封止樹脂層、２０・・・配線層、３０・・・配線基板   DESCRIPTION OF SYMBOLS 1 ... Metal plate, 2 ... Insulating layer, 3 ... Conductive layer, 3a ... Thermal via part, 3b, 3c ... Wiring part, 4 ... Insulating layer, 5 ... Conductive 5a ... thermal via part, 5b-5d ... wiring part, 6a ... metal protrusion, 6b ... heat transfer part, 7 ... solder resist layer, 8 ... adhesive layer, 9 ... LSI chip, 10 ... wire wire, 11 ... sealing resin layer, 20 ... wiring layer, 30 ... wiring substrate

Claims (3)

基板と、
前記基板上に設けられた絶縁層と、
前記絶縁層内からその一端が突出して設けられた複数の金属突起と、
前記絶縁層の表面から露出して設けられたワイヤ接続用電極と、
を備え、
前記金属突起の他端は前記基板と結合している、回路基板。 A substrate,
An insulating layer provided on the substrate;
A plurality of metal protrusions, one end of which protrudes from within the insulating layer;
A wire connecting electrode provided exposed from the surface of the insulating layer;
With
A circuit board, wherein the other end of the metal protrusion is coupled to the board. 前記金属突起の少なくとも一部は第１の金属突起と第２の金属突起とを結合して構成され、
前記絶縁層は第１の絶縁層とこの第１の絶縁層上に設けられた第２の絶縁層とを含み、
前記第１の絶縁層には前記第１の金属突起が設けられ、前記第２の絶縁層には前記第２の金属突起が設けられている請求項１に記載の回路基板。 At least a part of the metal protrusion is configured by combining a first metal protrusion and a second metal protrusion,
The insulating layer includes a first insulating layer and a second insulating layer provided on the first insulating layer,
The circuit board according to claim 1, wherein the first insulating layer is provided with the first metal protrusion, and the second insulating layer is provided with the second metal protrusion. 前記金属突起の一端上に設けられた回路素子をさらに備え、
前記回路素子はワイヤ線によって前記ワイヤ接続用電極と電気的に接続されている請求項１または２に記載の回路基板。 A circuit element provided on one end of the metal protrusion;
The circuit board according to claim 1, wherein the circuit element is electrically connected to the wire connection electrode by a wire line.
JP2006152078A 2006-05-31 2006-05-31 Circuit board Pending JP2007324330A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011507238A (en) * 2007-12-14 2011-03-03 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Apparatus comprising at least one optoelectronic semiconductor element
JP2011096995A (en) * 2009-10-29 2011-05-12 Samsung Electro-Mechanics Co Ltd Heat dissipation structure and method for manufacturing the same
JP2013157441A (en) * 2012-01-30 2013-08-15 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
JP2013542611A (en) * 2010-10-26 2013-11-21 ザイリンクス インコーポレイテッド Lead-free structure in semiconductor devices
US9054279B2 (en) 2007-01-11 2015-06-09 Osram Opto Semiconductors Gmbh Optoelectronic component disposed in a recess of a housing and electrical componenet disposed in the housing
CN104955265A (en) * 2015-05-26 2015-09-30 苏州旭创科技有限公司 PCB (printed circuit board) substrate and optical module with same
CN111092023A (en) * 2018-10-23 2020-05-01 碁鼎科技秦皇岛有限公司 Package substrate and manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9054279B2 (en) 2007-01-11 2015-06-09 Osram Opto Semiconductors Gmbh Optoelectronic component disposed in a recess of a housing and electrical componenet disposed in the housing
JP2011507238A (en) * 2007-12-14 2011-03-03 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Apparatus comprising at least one optoelectronic semiconductor element
US8994047B2 (en) 2007-12-14 2015-03-31 Osram Opto Semiconductors Gmbh Arrangement comprising at least one optoelectronics semiconductor component
JP2011096995A (en) * 2009-10-29 2011-05-12 Samsung Electro-Mechanics Co Ltd Heat dissipation structure and method for manufacturing the same
JP2013542611A (en) * 2010-10-26 2013-11-21 ザイリンクス インコーポレイテッド Lead-free structure in semiconductor devices
JP2013157441A (en) * 2012-01-30 2013-08-15 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
CN104955265A (en) * 2015-05-26 2015-09-30 苏州旭创科技有限公司 PCB (printed circuit board) substrate and optical module with same
CN111092023A (en) * 2018-10-23 2020-05-01 碁鼎科技秦皇岛有限公司 Package substrate and manufacturing method thereof
CN111092023B (en) * 2018-10-23 2021-10-19 碁鼎科技秦皇岛有限公司 Package substrate and manufacturing method thereof

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