JP2007318183A - Multilayer semiconductor device - Google Patents

Multilayer semiconductor device Download PDF

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Publication number
JP2007318183A
JP2007318183A JP2007228247A JP2007228247A JP2007318183A JP 2007318183 A JP2007318183 A JP 2007318183A JP 2007228247 A JP2007228247 A JP 2007228247A JP 2007228247 A JP2007228247 A JP 2007228247A JP 2007318183 A JP2007318183 A JP 2007318183A
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wiring board
semiconductor device
wiring
stacked semiconductor
stacked
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Takao Nishimura
隆雄 西村
Tadashi Uno
正 宇野
Akira Takashima
晃 高島
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To reduce occurrence of cracks in a wiring substrate in relation to a multilayer semiconductor device. <P>SOLUTION: The multilayer semiconductor device comprises a primary wiring substrate 12 with a semiconductor element 18, a secondary wiring substrate 14 which is laminated under the primary wiring substrate 12 and has a semiconductor element 26, and two or more electrode terminals 24 which electrically connect the primary wiring substrate 12 and the secondary wiring substrate 14. The dimension of the primary wiring substrate 12 is larger than that of the secondary wiring substrate 14 so that the outline of the secondary wiring substrate 14 is included within the area enclosed by the outline of the primary wiring substrate 12. The electrode terminals are not placed in the area of the primary wiring substrate 12 outside the secondary wiring substrate 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は積層型半導体装置に関する。   The present invention relates to a stacked semiconductor device.

近年の電子機器の発達にともない、電子機器に使用される半導体装置には小型化、薄型化、多機能化、高機能化、高密度化が要求されている。このような要求に対処すべく、複数の回路基板を積層した積層型半導体装置が提案されている（例えば、特許文献１、２参照) 。半導体素子が載置された第１の配線基板を、半導体素子が載置された第２の配線基板の上に配置して積層してなる積層型半導体装置が提案されている。   With the recent development of electronic devices, semiconductor devices used in electronic devices are required to be smaller, thinner, multifunctional, highly functional, and dense. In order to cope with such a demand, a stacked semiconductor device in which a plurality of circuit boards are stacked has been proposed (for example, see Patent Documents 1 and 2). There has been proposed a stacked semiconductor device in which a first wiring board on which a semiconductor element is placed is placed and stacked on a second wiring board on which a semiconductor element is placed.

第１の配線基板と第２の配線基板とを積層してなる積層型半導体装置においては、複数の電極端子が第１の配線基板と第２の配線基板とを電気的に接続する。典型的には、電極端子ははんだボールからなる。はんだボールの大きさを半導体素子の厚さより大きくし、はんだボールが第１の配線基板と第２の配線基板との間の間隔を維持するスペーサの作用をするようにした提案がある（特許文献１参照）。   In a stacked semiconductor device in which a first wiring board and a second wiring board are stacked, a plurality of electrode terminals electrically connect the first wiring board and the second wiring board. Typically, the electrode terminal is made of a solder ball. There is a proposal in which the size of the solder ball is made larger than the thickness of the semiconductor element, and the solder ball acts as a spacer for maintaining a distance between the first wiring board and the second wiring board (Patent Literature). 1).

積層型半導体装置はさらにマザーボード等の外部配線基板に搭載される。積層型半導体装置の配線基板の材料が外部配線基板の材料と異なっていると、両者の熱膨張の差によって積層型半導体装置の第１の配線基板と第２の配線基板とを電気的に接続する電極端子が疲労する。そこで、これらの電気的に接続する電極端子とは別に、電気的に接続しない補助電極端子を設け、電気的に接続する電極端子の疲労を緩和する提案がある（特許文献２参照) 。   The stacked semiconductor device is further mounted on an external wiring substrate such as a mother board. When the material of the wiring substrate of the stacked semiconductor device is different from the material of the external wiring substrate, the first wiring substrate and the second wiring substrate of the stacked semiconductor device are electrically connected due to the difference in thermal expansion between them. The electrode terminals to be fatigued. Therefore, there is a proposal to provide an auxiliary electrode terminal that is not electrically connected separately from these electrically connected electrode terminals to alleviate fatigue of the electrically connected electrode terminals (see Patent Document 2).

特開２００１−２２３２９７号公報JP 2001-223297 A 特開２００２−１７０９２４号公報（第２〜３頁）JP 2002-170924 A (pages 2 to 3)

配線基板とを積層した積層型半導体装置はその搬送（運搬）、試験等に於ける取扱い（ハンドリング）ならびに電子機器のプリント基板、マザーボード等への高密度実装のために、直方体とするのが好ましく、そこで、積層型半導体装置においては、第１の配線基板の外形と第２の配線基板の外形とを等しく形成し、両者が積層されてなる積層型半導体装置を上方から見たときに第１の配線基板の外形と第２の配線基板の外形とが全く重なって見えるような構造にする。   A stacked semiconductor device laminated with a wiring board is preferably a rectangular parallelepiped for its transportation (transportation), handling in testing (handling), and high-density mounting on printed circuit boards, motherboards, etc. of electronic equipment. Therefore, in the stacked semiconductor device, the first and second wiring boards are formed to have the same outer shape and the stacked semiconductor device in which both are stacked is viewed from above. The outer shape of the wiring board and the outer shape of the second wiring board are completely overlapped.

しかし、積層時に第１の配線基板と第２の配線基板との間に位置ずれが生じると、第１の配線基板の外形の一部が第２の配線基板の外形から突出し（あるいは逆に第２の配線基板の外形の一部が第１の配線基板の外形から突出し）、積層型半導体装置の外形寸法公差が大きくなる。積層する配線基板の数が増加すると、積層型半導体装置の外形寸法公差がさらに大きくなる可能性がある。   However, if a positional shift occurs between the first wiring board and the second wiring board during lamination, a part of the outer shape of the first wiring board protrudes from the outer shape of the second wiring board (or conversely, A part of the outer shape of the wiring board 2 protrudes from the outer shape of the first wiring board), and the outer dimensional tolerance of the stacked semiconductor device increases. As the number of wiring boards to be stacked increases, the outer dimensional tolerance of the stacked semiconductor device may further increase.

図５は従来の積層型半導体装置を上から見た略断面図である。上方の配線基板１２ａと中間の配線基板１４ａとは同じ外形形状及び外形サイズを有する。この場合、図５に示されるように、上方の配線基板１２ａと中間の配線基板１４ａとを積層する際に両者間に位置ずれがあると、中間の配線基板１４ａの一部が見える、すなわち、中間の配線基板１４ａの一部が上方の配線基板１２ａから突出する。このために、積層型半導体装置の側面に人の指や工具を当ててハンドリングする場合、指や工具が突出した配線基板の外形の一部に当たり、１枚の基板に応力が集中して、配線基板にクラックが生じやすい。   FIG. 5 is a schematic cross-sectional view of a conventional stacked semiconductor device viewed from above. The upper wiring board 12a and the intermediate wiring board 14a have the same outer shape and outer size. In this case, as shown in FIG. 5, when the upper wiring board 12a and the intermediate wiring board 14a are stacked, if there is a positional shift between the two, a part of the intermediate wiring board 14a can be seen. A part of the intermediate wiring board 14a protrudes from the upper wiring board 12a. For this reason, when handling with a finger or tool applied to the side of the stacked semiconductor device, the finger or tool hits a part of the outer shape of the wiring board, and stress concentrates on one board, causing wiring to occur. Cracks are likely to occur on the substrate.

このため、積層型半導体装置をハンドリングする場合に問題が生じる。   For this reason, a problem arises when handling the stacked semiconductor device.

例えば、積層型半導体装置を収容するトレー又は半導体装置を輸送する際に用いるトレーについて、半導体装置の外形寸法公差が大きくなると、それに合わせてトレーの寸法も大きくする必要がある。すると、トレー内での積層型半導体装置のガタツキが大きくなり、輸送時に積層型半導体装置に加わる振動が増大し、配線基板にクラックが生じやすくなる。   For example, regarding the tray that houses the stacked semiconductor device or the tray that is used when transporting the semiconductor device, if the tolerance of the outer dimensions of the semiconductor device increases, the size of the tray needs to be increased accordingly. As a result, the backlash of the stacked semiconductor device in the tray increases, vibrations applied to the stacked semiconductor device during transportation increase, and cracks are likely to occur in the wiring board.

積層型半導体装置を試験用のソケットに載せる場合には、積層型半導体装置の基準位置がソケットの基準位置に合っていないと、端子間の位置ずれが生じる。   When the stacked semiconductor device is placed on a test socket, if the reference position of the stacked semiconductor device does not match the reference position of the socket, a positional deviation between the terminals occurs.

積層型半導体装置の側面に人の指や工具を当ててハンドリングする場合、突出した配線基板に応力が集中するため、配線基板にクラックが生じやすい。   When handling with a finger or a tool applied to the side surface of the stacked semiconductor device, stress concentrates on the protruding wiring board, so that the wiring board is likely to crack.

配線基板が樹脂ガラス−エポキシ樹脂複合材料やガラス−ＢＴ（ビスマレイミド・トリアジン）樹脂複合材料等の有機基板で作られている場合、そして特に配線基板の厚さが薄い（例えば０．１ｍｍ〜０．３ｍｍ）場合は特に外力に対して弱いため、配線基板にクラックが生じやすい。   When the wiring board is made of an organic substrate such as a resin glass-epoxy resin composite material or a glass-BT (bismaleimide / triazine) resin composite material, the thickness of the wiring board is particularly small (for example, 0.1 mm to 0 mm). .3 mm) is particularly vulnerable to external forces, and thus the wiring board is likely to crack.

又、配線基板の位置ずれがあると、積層型半導体装置の外形を画像認識して取り扱う場合、画像認識のずれが大きくなり、自動化処理できない問題も発生する。   In addition, if there is a positional deviation of the wiring board, when the outer shape of the stacked semiconductor device is recognized and handled, the image recognition shift becomes large, and there is a problem that the automatic processing cannot be performed.

本発明は、このような積層型半導体装置において配線基板へのクラックの発生を防止することができる積層型半導体装置を提供するものである。   The present invention provides a stacked semiconductor device capable of preventing the occurrence of cracks in a wiring substrate in such a stacked semiconductor device.

本発明による積層型半導体装置は、少なくとも１つの半導体素子を有する第１の配線基板と、該第１の配線基板の上又は下に積層され且つ少なくとも１つの半導体素子を有する第２の配線基板と、前記第１の配線基板と前記第２の配線基板とを電気的に接続する複数の電極端子とを備え、前記第１の配線基板の外形が前記第２の配線基板の外形よりも大きく、前記第２の配線基板の外形が前記第１の配線基板の外形の範囲内に収まるように形成され、前記第１の配線基板の前記第２の配線基板よりも外側の領域には電極端子が配置されていないことを特徴とするものである。   A stacked semiconductor device according to the present invention includes a first wiring board having at least one semiconductor element, and a second wiring board stacked on or under the first wiring board and having at least one semiconductor element. A plurality of electrode terminals that electrically connect the first wiring board and the second wiring board, and an outer shape of the first wiring board is larger than an outer shape of the second wiring board, The outer shape of the second wiring board is formed so as to be within the range of the outer shape of the first wiring board, and an electrode terminal is provided in a region outside the second wiring board of the first wiring board. It is characterized by not being arranged.

この構成によれば、第１の配線基板の外形は基本的に第２の配線基板の外形とほぼ同じに形成されているが、第１の配線基板の外形が第２の配線基板の外形よりも両者間の位置ずれ量を吸収できる程度に少しだけ大きく形成されている。第１の配線基板の第２の配線基板よりも外側の領域は位置ずれを吸収する領域であるので、そこには電極端子が設けられない。従って、第１の配線基板と第２の配線基板とを積層したときに、両者間に位置ずれがあっても、積層型半導体装置を上から見たときに、小さい第２の配線基板は大きい第１の配線基板の外形の範囲内に収まる。従って、第１の配線基板の外形を基準にしてハンドリングを行うことができる。   According to this configuration, the outer shape of the first wiring board is basically formed substantially the same as the outer shape of the second wiring board, but the outer shape of the first wiring board is more than the outer shape of the second wiring board. Is formed to be slightly large enough to absorb the amount of misalignment between the two. Since the region outside the second wiring substrate of the first wiring substrate is a region that absorbs misalignment, no electrode terminal is provided there. Therefore, when the first wiring board and the second wiring board are stacked, even if there is a positional shift between them, the small second wiring board is large when the stacked semiconductor device is viewed from above. It falls within the range of the outer shape of the first wiring board. Therefore, handling can be performed based on the outer shape of the first wiring board.

好ましくは、前記第１の配線基板の少なくとも１つの半導体素子が設けられた表面が樹脂で封止されており、前記封止樹脂の外形が前記第１の配線基板の外形と等しい。こうすれば、大きい第１の配線基板が封止樹脂により強化されており、且つハンドリングに際して人の指や工具が第１の配線基板の側面及び封止樹脂の側面に接触し、第２の配線基板の側面には接触しないため、配線基板のクラックの発生をより低減できる。   Preferably, a surface of the first wiring board on which at least one semiconductor element is provided is sealed with a resin, and an outer shape of the sealing resin is equal to an outer shape of the first wiring board. In this way, the large first wiring board is reinforced with the sealing resin, and a human finger or tool comes into contact with the side surface of the first wiring board and the side surface of the sealing resin during handling, so that the second wiring Since it does not contact the side surface of the substrate, the generation of cracks in the wiring substrate can be further reduced.

さらに、本発明による積層型半導体装置は、少なくとも１つの半導体素子を有する第１の配線基板と、該第１の配線基板の上又は下に積層され且つ少なくとも１つの半導体素子を有する第２の配線基板と、前記第１の配線基板と前記第２の配線基板とを電気的に接続する複数の電極端子とを備え、前記第１及び第２の配線基板が有機基板からなり、前記第１の配線基板と前記第２の配線基板とを機械的に固定する支持部材が前記第１及び第２の配線基板の四隅を含む周辺領域に設けられることを特徴とする。   Furthermore, the stacked semiconductor device according to the present invention includes a first wiring board having at least one semiconductor element, and a second wiring stacked on or under the first wiring board and having at least one semiconductor element. A plurality of electrode terminals that electrically connect the first wiring board and the second wiring board, the first and second wiring boards being made of organic substrates, A support member for mechanically fixing the wiring board and the second wiring board is provided in a peripheral region including four corners of the first and second wiring boards.

この構成によれば、支持部材が配線基板の四隅を含む周辺領域に設けられ、配線基板の突出した部分がある場合にもクラックしにくいようになっている。従って、配線基板が外力に対して弱い有機基板からなるものであっても、配線基板のクラックの発生を防止することができる。   According to this configuration, the support member is provided in the peripheral region including the four corners of the wiring board, and is difficult to crack even when there is a protruding part of the wiring board. Therefore, even if the wiring substrate is made of an organic substrate that is weak against external force, the occurrence of cracks in the wiring substrate can be prevented.

以下本発明の実施例について図面を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

図１は本発明の第一実施例の積層型半導体装置を示す断面図である。図１において、積層型半導体装置１０は、上方（第１）の配線基板１２と、中間（第２）の配線基板１４と、下方（第３）の配線基板１６とを積層して構成されている。これらの配線基板１２、１４、１６は、コアが樹脂ガラス−エポキシ樹脂複合材料あるいはガラス−ＢＴ（ビスマレイミド・トリアジン）樹脂複合材料等の有機基板から形成され、その内部及び／又は表面に銅（Ｃｕ）などからなる電極／配線層が配設されている。   FIG. 1 is a sectional view showing a stacked semiconductor device according to a first embodiment of the present invention. In FIG. 1, the stacked semiconductor device 10 is configured by stacking an upper (first) wiring board 12, an intermediate (second) wiring board 14, and a lower (third) wiring board 16. Yes. These wiring boards 12, 14, and 16 are formed of an organic substrate such as a resin glass-epoxy resin composite material or a glass-BT (bismaleimide-triazine) resin composite material, and copper ( An electrode / wiring layer made of Cu) or the like is provided.

上方の配線基板１２には半導体素子（半導体チップ）１８が搭載されている。半導体素子１８はバンプ２０を有し、バンプ２０で上方の配線基板１２にフリップチップボンディングされている。半導体素子１８と配線基板１２は接着剤２２によって固着されている。   A semiconductor element (semiconductor chip) 18 is mounted on the upper wiring board 12. The semiconductor element 18 has a bump 20, and the bump 20 is flip-chip bonded to the upper wiring substrate 12. The semiconductor element 18 and the wiring board 12 are fixed by an adhesive 22.

配線基板１２の下面（半導体素子１８が搭載されている側とは反対側の表面）には、はんだボールからなる電極端子２４が配設されている。はんだボール２４は前記配線層を介して半導体素子１８に電気的に接続されている。   On the lower surface of the wiring board 12 (surface opposite to the side where the semiconductor element 18 is mounted), electrode terminals 24 made of solder balls are disposed. The solder ball 24 is electrically connected to the semiconductor element 18 through the wiring layer.

同様に、中間の配線基板１４には半導体素子２６が搭載されている。当該半導体素子２６はバンプ２８を有し、バンプ２８で中間の配線基板１４にフリップチップボンディングされている。半導体素子２６と中間の配線基板１４は接着剤３０によって固着されている。配線基板１４の下面には、外部接続電極３２が配設されている。外部接続電極３２は前記配線層を介して半導体素子２６に電気的に接続されている。   Similarly, a semiconductor element 26 is mounted on the intermediate wiring board 14. The semiconductor element 26 has bumps 28, and is flip-chip bonded to the intermediate wiring substrate 14 with the bumps 28. The semiconductor element 26 and the intermediate wiring board 14 are fixed by an adhesive 30. External connection electrodes 32 are disposed on the lower surface of the wiring board 14. The external connection electrode 32 is electrically connected to the semiconductor element 26 through the wiring layer.

配線基板１２のはんだボール２４は配線基板１２と配線基板１４とを電気的に接続している。はんだボール２４の大きさは半導体素子２６の厚さより大きく、配線基板１２と配線基板１４との間の間隔を維持するスペーサの作用もする。   The solder balls 24 of the wiring board 12 electrically connect the wiring board 12 and the wiring board 14. The size of the solder ball 24 is larger than the thickness of the semiconductor element 26, and also acts as a spacer that maintains the distance between the wiring board 12 and the wiring board 14.

同様に、配線基板１６には半導体素子３４が搭載されている。当該半導体素子３４はバンプ３６を有し、バンプ３６によって配線基板１６にフリップチップボンディングされている。半導体素子３４と下方の配線基板１６は接着剤（アンダーフィル）３８によって固着されている。配線基板１６の下面には外部接続電極４０が取りつけられている。外部接続電極４０は前記配線層を介して半導体素子３４に電気的に接続されている。   Similarly, a semiconductor element 34 is mounted on the wiring board 16. The semiconductor element 34 has bumps 36 and is flip-chip bonded to the wiring substrate 16 by the bumps 36. The semiconductor element 34 and the lower wiring board 16 are fixed by an adhesive (underfill) 38. External connection electrodes 40 are attached to the lower surface of the wiring board 16. The external connection electrode 40 is electrically connected to the semiconductor element 34 through the wiring layer.

前記配線基板１４の外部接続電極３２は当該配線基板１４と配線基板１６とを電気的に接続するとともに、両配線基板間の間隔を維持している。   The external connection electrodes 32 of the wiring board 14 electrically connect the wiring board 14 and the wiring board 16 and maintain a distance between the wiring boards.

下方の配線基板１６の外部接続電極４０はマザーボード等の外部配線基板（図示せず）に電気的に接続される。   The external connection electrodes 40 of the lower wiring board 16 are electrically connected to an external wiring board (not shown) such as a mother board.

第１の実施例にあっては、中間の配線基板１４と下方の配線基板１６とは同じ外形形状及び外形サイズ（寸法）を有する。   In the first embodiment, the intermediate wiring board 14 and the lower wiring board 16 have the same outer shape and outer size (dimension).

一方、配線基板１２は配線基板１４及び配線基板１６とは基本的に同じ外形形状を有するものの、配線基板１２の外形サイズは配線基板１４、１６の外形サイズよりも若干大きなものとされる。従って、配線基板１４、１６の外形は、配線基板１２の外形の範囲内に収まる。   On the other hand, although the wiring board 12 has basically the same outer shape as the wiring board 14 and the wiring board 16, the outer size of the wiring board 12 is slightly larger than the outer size of the wiring boards 14 and 16. Accordingly, the outer shapes of the wiring boards 14 and 16 are within the range of the outer shape of the wiring board 12.

図４は第１実施例の積層型半導体装置１０を上から見た平面図である。   FIG. 4 is a plan view of the stacked semiconductor device 10 of the first embodiment as viewed from above.

同図において、配線基板１２のサイズは１１．１ｍｍ×１５．１ｍｍであり、配線基板１４、１６のサイズは１１ｍｍ×１５ｍｍである。配線基板１２と、配線基板１４、１６との寸法差０．１ｍｍは、配線基板相互の位置ずれを吸収するものであって配線基板１２のサイズを１１．２ｍｍ×１５．２ｍｍとして、位置ずれの吸収量を拡大することもできる。このような構成により配線基板１４、１６は配線基板１２の外形の範囲内に収容され、積層型半導体装置１０を上から見た時、配線基板１４、１６は配線基板１２から突出している部分がない。   In the figure, the size of the wiring board 12 is 11.1 mm × 15.1 mm, and the size of the wiring boards 14 and 16 is 11 mm × 15 mm. The dimensional difference of 0.1 mm between the wiring board 12 and the wiring boards 14 and 16 absorbs the positional deviation between the wiring boards, and the size of the wiring board 12 is 11.2 mm × 15.2 mm. The amount of absorption can also be increased. With such a configuration, the wiring boards 14 and 16 are accommodated within the range of the outer shape of the wiring board 12, and when the stacked semiconductor device 10 is viewed from above, the wiring boards 14 and 16 have portions protruding from the wiring board 12. Absent.

本実施例によれば、配線基板１２は配線基板１４及び配線基板１６とは基本的に同じ外形形状を有し、且つ配線基板１２のサイズを配線基板１４、１６のサイズより大きくしている。こうすれば、配線基板１２を基準として、積層型半導体装置１０の形状を認識し、ハンドリングすることができるので、指や工具が予期せぬところに接触することを防止することができる。よって配線基板にクラックが生じることがない。   According to this embodiment, the wiring board 12 has basically the same outer shape as the wiring board 14 and the wiring board 16, and the size of the wiring board 12 is larger than the size of the wiring boards 14 and 16. In this way, the shape of the stacked semiconductor device 10 can be recognized and handled with the wiring board 12 as a reference, so that it is possible to prevent fingers and tools from coming into contact with unexpected places. Therefore, no crack is generated in the wiring board.

図２は本発明の第２実施例の積層型半導体装置を示す断面図である。本実施例における積層型半導体装置１０は、第１実施例の積層型半導体装置１０と基本的に同様に構成されるが、最下段の配線基板１６の外形寸法が大きくされている点が異なる。即ち、配線基板１２と中間の配線基板１４とは同じ外形形状及び外形サイズを有し、下方の配線基板１６は上方の配線基板１２と中間の配線基板１４とは基本的に同じ外形形状を有するものの、その外形サイズは上方の配線基板１２と中間の配線基板１４の外形サイズよりも若干大きなものとされる。従って配線基板１２と配線基板１４の外形が配線基板１６の外形の範囲内に収まる。本実施例では、下段の配線基板１６の外形サイズを大きくしているため、試験時において、試験ソケットの位置あわせが容易となるメリットもある。   FIG. 2 is a sectional view showing a stacked semiconductor device according to a second embodiment of the present invention. The stacked semiconductor device 10 according to the present embodiment is basically configured in the same manner as the stacked semiconductor device 10 according to the first embodiment, except that the outer dimensions of the lowermost wiring substrate 16 are increased. That is, the wiring board 12 and the intermediate wiring board 14 have the same outer shape and size, and the lower wiring board 16 has basically the same outer shape as the upper wiring board 12 and the intermediate wiring board 14. However, the outer size is slightly larger than the outer size of the upper wiring board 12 and the intermediate wiring board 14. Therefore, the outer shapes of the wiring board 12 and the wiring board 14 are within the range of the outer shape of the wiring board 16. In this embodiment, since the outer size of the lower wiring board 16 is increased, there is also an advantage that the test socket can be easily aligned during the test.

第１、第２実施例においては、積層型半導体装置は３つの配線基板１２、１４、１６を積層してなるものであったが、本発明は３つの配線基板１２、１４、１６を積層してなる積層型半導体装置に限定されるものではなく、２つの配線基板を積層したもの、あるいは４つ以上の配線基板を積層したものとすることができる。   In the first and second embodiments, the stacked semiconductor device is formed by stacking three wiring boards 12, 14, and 16. However, in the present invention, three wiring boards 12, 14, and 16 are stacked. However, the present invention is not limited to the stacked semiconductor device, and may be a stack of two wiring boards or a stack of four or more wiring boards.

また、各配線基板１２、１４、１６はそれぞれ１つの半導体素子１８、２６、３４を実装するものに限定されず、少なくとも１つの配線基板は複数の半導体素子を実装するものとすることができる。また、各配線基板１２、１４、１６はそれぞれ上面側に半導体素子１８、２６、３４を有するものに限定されず、下面側に半導体素子を有するものとすることができる。   Moreover, each wiring board 12, 14, 16 is not limited to the one on which one semiconductor element 18, 26, 34 is mounted, and at least one wiring board can be mounted with a plurality of semiconductor elements. Moreover, each wiring board 12, 14, and 16 is not limited to what has the semiconductor elements 18, 26, and 34 on the upper surface side, respectively, It can have a semiconductor element on the lower surface side.

また、各半導体素子１８、２６、３４は配線基板にフリップチップボンディングされるか、ワイヤボンディングされる。   Each semiconductor element 18, 26, 34 is flip-chip bonded or wire bonded to the wiring board.

積層型半導体装置が３つ以上の配線基板を積層してなるものである場合に、最上方又は最下方の配線基板の外形サイズを最大にするのが好ましい。尚、各配線基板１２、１４、１６は単層型配線基板又は多層型配線基板とすることができる。   When the stacked semiconductor device is formed by stacking three or more wiring substrates, it is preferable to maximize the outer size of the uppermost or lowermost wiring substrate. Each wiring board 12, 14, 16 can be a single-layer wiring board or a multilayer wiring board.

よって、トレー寸法を最大外形サイズの配線基板に合わせることで、トレー内でのガタツキをなくすことができる。さらに、第２の実施例において試験ソケットに半導体装置を装着する際、外部端子を備えた下方の配線基板を大きくして、その外形サイズで積層型半導体装置の位置決めをすると、試験時のソケットと積層型半導体装置の位置ずれが低減できる。   Therefore, the backlash in the tray can be eliminated by adjusting the tray dimensions to the wiring board having the maximum external size. Further, when the semiconductor device is mounted on the test socket in the second embodiment, the lower wiring board having the external terminals is enlarged and the stacked semiconductor device is positioned with the outer size. The misalignment of the stacked semiconductor device can be reduced.

図３は本発明の第３実施例の積層型半導体装置を示す断面図である。本実施例の積層型半導体装置１０は、第１実施例の積層型半導体装置１０と基本的に同様な構成を有し、大きい上方の配線基板１２の表面は樹脂４２により封止されており、封止樹脂４２の外形は上方の配線基板１２の外形と等しくされている。本実施例においては、上方の配線基板１２には、３つの半導体素子１８ａ、１８ｂ、１８ｃが積層実装された構造となっており、半導体素子１８ａは上方の配線基板１２にフリップチップボンディングされている。半導体素子１８ｂは半導体素子１８ａに積層されて、半導体素子１８ｂの接続端子は上方の配線基板１２にワイヤボンディングされ、半導体素子１８ｃは半導体素子１８ｂに積層されて、半導体素子１８ｃの接続端子は上方の配線基板１２にワイヤボンディングされている。また、下方の配線基板１６は２つの半導体素子３４ａ、３４ｂを実装する。   FIG. 3 is a sectional view showing a stacked semiconductor device according to a third embodiment of the present invention. The stacked semiconductor device 10 of the present embodiment has basically the same configuration as the stacked semiconductor device 10 of the first embodiment, and the surface of the large upper wiring substrate 12 is sealed with a resin 42. The outer shape of the sealing resin 42 is equal to the outer shape of the upper wiring board 12. In this embodiment, the upper wiring substrate 12 has a structure in which three semiconductor elements 18a, 18b, and 18c are stacked and mounted. The semiconductor element 18a is flip-chip bonded to the upper wiring substrate 12. . The semiconductor element 18b is laminated on the semiconductor element 18a, the connection terminal of the semiconductor element 18b is wire-bonded to the upper wiring board 12, the semiconductor element 18c is laminated on the semiconductor element 18b, and the connection terminal of the semiconductor element 18c is upper Wire bonding is performed on the wiring substrate 12. The lower wiring board 16 mounts two semiconductor elements 34a and 34b.

本実施例においては、上方の配線基板１２の外形サイズが最大であり、他の配線基板１４、１６の外形はその最大外形内に収まるように積層されている。上方の配線基板１２の半導体素子１８ａ、１８ｂ、１８ｃが搭載された面はトランスファーモールドにより樹脂４２で封止されている。封止樹脂４２の外形は、配線基板１２の外形と等しくされている。従って、上方の配線基板１２の側面と封止樹脂４２の側面は面一である。かかる接着剤の配設は、前記第１実施例、第２実施例、並びに後述する第４乃至第６実施例においても適用することができる。半導体素子２６、３４、３４ａ、３４ｂとその上にある配線基板１４、１６との間に接着剤を挿入することもできる。   In this embodiment, the outer size of the upper wiring board 12 is the largest, and the outer shapes of the other wiring boards 14 and 16 are stacked so as to be within the maximum outer shape. The surface of the upper wiring board 12 on which the semiconductor elements 18a, 18b, 18c are mounted is sealed with a resin 42 by transfer molding. The outer shape of the sealing resin 42 is equal to the outer shape of the wiring board 12. Therefore, the side surface of the upper wiring board 12 and the side surface of the sealing resin 42 are flush with each other. The arrangement of the adhesive can also be applied to the first embodiment, the second embodiment, and the fourth to sixth embodiments described later. An adhesive may be inserted between the semiconductor elements 26, 34, 34a, and 34b and the wiring boards 14 and 16 on the semiconductor elements 26, 34, 34a, and 34b.

本実施例の積層型半導体装置１０においては、第１の実施例の積層型半導体装置と同様、完成体である積層型半導体装置１０の外形公差を最大外形サイズを有する上方の配線基板１２の外形寸法で管理することができる。さらに、積層型半導体装置１０を収容し、輸送する際、積層型半導体装置１０がトレー内で振動しても上方の配線基板１２及び封止樹脂４２の側面がトレー内壁に接触し、他の配線基板の側面は接触しないため、クラックの発生を防止することができる。   In the stacked semiconductor device 10 according to the present embodiment, as with the stacked semiconductor device according to the first embodiment, the outer shape tolerance of the upper stacked wiring board 12 having the maximum outer size is set as the outer tolerance of the completed stacked semiconductor device 10. It can be managed by dimensions. Further, when the stacked semiconductor device 10 is accommodated and transported, even if the stacked semiconductor device 10 vibrates in the tray, the side surfaces of the upper wiring board 12 and the sealing resin 42 contact the inner wall of the tray, and other wiring Since the side surface of the substrate is not in contact, the occurrence of cracks can be prevented.

第１、第２、第３の実施例においては、複数の配線基板を互いに積層する際に配線基板間に位置ずれが生じても、他の配線基板が最大の配線基板の外形サイズの範囲内に収まるように積層されているので、完成体である積層型半導体装置の外形公差を最大外形サイズの配線基板の外形寸法で管理できる。   In the first, second, and third embodiments, even when positional misalignment occurs between the wiring boards when a plurality of wiring boards are stacked on each other, the other wiring boards are within the range of the maximum size of the wiring board. Therefore, it is possible to manage the outer tolerance of the finished stacked semiconductor device by the outer dimensions of the wiring board having the maximum outer size.

図６は本発明の第４実施例の積層型半導体装置を示す断面図、図７は図６の積層型半導体装置の上方の配線基板のはんだボール及び支持部材を通る断面である。   FIG. 6 is a cross-sectional view showing a stacked semiconductor device according to a fourth embodiment of the present invention, and FIG. 7 is a cross-section passing through solder balls and a support member of a wiring board above the stacked semiconductor device of FIG.

図６において、積層型半導体装置１０は、それぞれ半導体素子が搭載された２枚の配線基板、即ち配線基板１２と、配線基板１４とを積層して構成される。これらの配線基板１２、１４は、コアが樹脂ガラス−エポキシ樹脂複合材料あるいは、ガラス−ＢＴ（ビスマレイミド・トリアジン）樹脂複合材料等で作られている有機基板からなる。   In FIG. 6, the stacked semiconductor device 10 is configured by stacking two wiring boards each mounted with a semiconductor element, that is, a wiring board 12 and a wiring board 14. These wiring substrates 12 and 14 are made of an organic substrate whose core is made of a resin glass-epoxy resin composite material or a glass-BT (bismaleimide / triazine) resin composite material.

上方の配線基板１２には半導体素子（半導体チップ）１８ａ、１８ｂ、１８ｃが搭載されている。これらの半導体素子１８ａ、１８ｂ、１８ｃは、配線基板１２にフリップチップボンディングされ、あるいはワイヤボンディングされる。上方の配線基板１２の上面は樹脂４２で封止される。   Semiconductor elements (semiconductor chips) 18a, 18b, and 18c are mounted on the upper wiring board 12. These semiconductor elements 18a, 18b, and 18c are flip-chip bonded or wire bonded to the wiring board 12. The upper surface of the upper wiring board 12 is sealed with a resin 42.

上方の配線基板１２の下面にははんだボール（電極端子）２４が取りつけられている。上方の配線基板１２は回路パターンを有し、はんだボール２４は回路パターンを介して半導体素子１８ａ、１８ｂ、１８ｃに電気的に接続されている。   Solder balls (electrode terminals) 24 are attached to the lower surface of the upper wiring board 12. The upper wiring board 12 has a circuit pattern, and the solder balls 24 are electrically connected to the semiconductor elements 18a, 18b, and 18c through the circuit pattern.

下方の配線基板１４は半導体素子２６を実装し、半導体素子２６は下方の配線基板１４にフリップチップボンディングされている。下方の配線基板１４の下面には外部接続電極３２が取りつけられている。中間の配線基板１４は回路パターンを有し、外部接続電極３２は回路パターンを介して半導体素子２６に電気的に接続されている。上方の配線基板１２のはんだボール２４は、上方の配線基板１２と下方の配線基板１４とを電気的に接続している。   The lower wiring board 14 mounts a semiconductor element 26, and the semiconductor element 26 is flip-chip bonded to the lower wiring board 14. External connection electrodes 32 are attached to the lower surface of the lower wiring board 14. The intermediate wiring board 14 has a circuit pattern, and the external connection electrode 32 is electrically connected to the semiconductor element 26 through the circuit pattern. The solder balls 24 of the upper wiring board 12 electrically connect the upper wiring board 12 and the lower wiring board 14.

本実施例によれば、上方の配線基板１２と下方の配線基板１４とを機械的に固定する補強部４４が上方及び下方の配線基板１２、１４の四隅を含む周辺領域に配設される。   According to this embodiment, the reinforcing portions 44 for mechanically fixing the upper wiring board 12 and the lower wiring board 14 are disposed in the peripheral region including the four corners of the upper and lower wiring boards 12 and 14.

補強部４４は、はんだボール２４の最外側の列上またはそれより外側で上方及び下方の配線基板１２、１４の四隅を含む周辺領域に配設される。図７においては、補強部４４ははんだボール２４の外側で上方及び下方の配線基板１２、１４の四隅に設けられる。   The reinforcing portion 44 is disposed in a peripheral region including the four corners of the upper and lower wiring boards 12 and 14 on the outermost row of the solder balls 24 or outside thereof. In FIG. 7, the reinforcing portions 44 are provided at the four corners of the upper and lower wiring boards 12 and 14 outside the solder ball 24.

補強部４４は例えば次の幾つかのグループの中の１つの材料から形成することができる。   The reinforcement portion 44 can be formed of one material in the following several groups, for example.

（ａ）液状のエポキシ、ポリイミド、アクリル等の絶縁性樹脂をディスペンス法やスタンピング法で形成した後に加熱硬化させて固着させたもの。   (A) An insulating resin such as liquid epoxy, polyimide, acrylic, etc., formed by a dispensing method or a stamping method and then heat-cured and fixed.

（ｂ）Ｂステージで半硬化状態とされた樹脂フィルム。   (B) A resin film that has been semi-cured in the B stage.

（ｃ）両面に粘着剤が形成されたＰＥＴ等のフィルムを貼りつけた後に加熱硬化させて固着させたもの。   (C) A film made of PET or the like having a pressure-sensitive adhesive formed on both sides and then heat-cured and fixed.

（ｄ）配線基板のコア材と同じ材料（ガラス−エポキシ樹脂、ガラス−ＢＴ樹脂）で両面に熱硬化性の接着剤が形成されたもの。   (D) The same material (glass-epoxy resin, glass-BT resin) as the core material of the wiring board, on which thermosetting adhesive is formed on both sides.

（ｅ）Ｃｕ、Ａｌ、Ｗ、Ｆｅ、Ｎｉ、４２アロイ剤等の金属およびそれらの合金で、両面に熱硬化性の接着剤が形成されたもの。   (E) Metals such as Cu, Al, W, Fe, Ni, 42 alloy, and alloys thereof, with thermosetting adhesive formed on both sides.

このように、上下の配線基板１２、１４の四隅が支持固定されていることにより、外的な機械的ストレスが一方の配線基板１２、１４の端部に加わった場合に、配線基板１２、１４のクラックの発生を防止することができる。   As described above, when the four corners of the upper and lower wiring boards 12 and 14 are supported and fixed, when an external mechanical stress is applied to the end portion of one of the wiring boards 12 and 14, the wiring boards 12 and 14. Generation of cracks can be prevented.

図８から図１４は第４実施例の変形例を示す図である。   8 to 14 are diagrams showing modifications of the fourth embodiment.

図８に示される例においては、配線基板１２、１４の一辺の長さに相当する長い補強部４４が、配線基板１２、１４の対向する２辺に沿って配置される。これにより、補強部４４は、配線基板１２、１４間を支持固定して、外的な機械的ストレスが配線基板１２、１４の端部に加わった場合に、配線基板１２、１４のクラックの発生を防止する。また、配線基板１２、１４の辺の中央部に局所的な力が加わった場合にも、クラックの発生を防止することができる。   In the example shown in FIG. 8, a long reinforcing portion 44 corresponding to the length of one side of the wiring boards 12 and 14 is arranged along two opposing sides of the wiring boards 12 and 14. As a result, the reinforcing portion 44 supports and fixes the wiring boards 12 and 14, and when external mechanical stress is applied to the ends of the wiring boards 12 and 14, cracks in the wiring boards 12 and 14 occur. To prevent. In addition, even when a local force is applied to the central part of the sides of the wiring boards 12 and 14, the occurrence of cracks can be prevented.

図９においては、長い補強部４４が配線基板１２、１４の４辺に沿って配置される。各辺の補強部４４は独立しており、隣接する２つの補強部４４の端部の間に隙間４６が設けられている。これにより、補強部４４は、配線基板１２、１４の四隅を支持固定して、外的な機械的ストレスが配線基板１２、１４の端部に加わった場合に、配線基板１２、１４のクラックの発生を防止する。また、配線基板１２、１４の辺の中央部に局所的な力が加わった場合にもクラックの発生を防止することができる。補強部４４が配線基板１２、１４の４辺に沿って配置されているので、よりクラックの発生を低減できる。又、熱処理時における基板の反りもおさえる効果がある。配線基板１２、１４の４隅に近い位置に隙間４６が設けられているので、組立て工程における積層配線基板の洗浄工程において、配線基板の間の接続端子部に洗浄液を容易に流入および流出させることができる。   In FIG. 9, long reinforcing portions 44 are arranged along the four sides of the wiring boards 12 and 14. The reinforcing portions 44 on each side are independent, and a gap 46 is provided between the ends of two adjacent reinforcing portions 44. As a result, the reinforcing portion 44 supports and fixes the four corners of the wiring boards 12 and 14, and when external mechanical stress is applied to the ends of the wiring boards 12 and 14, cracks in the wiring boards 12 and 14 are generated. Prevent occurrence. In addition, the occurrence of cracks can also be prevented when a local force is applied to the central part of the sides of the wiring boards 12 and 14. Since the reinforcing portions 44 are arranged along the four sides of the wiring boards 12 and 14, the generation of cracks can be further reduced. In addition, there is an effect of suppressing the warpage of the substrate during the heat treatment. Since the gaps 46 are provided at positions close to the four corners of the wiring boards 12 and 14, the cleaning liquid can easily flow into and out of the connection terminal portions between the wiring boards in the cleaning process of the laminated wiring board in the assembly process. Can do.

図１０から図１２においては、閉じていない（不連続な）環状（枠状）の補強部４４が配線基板１２、１４の４辺に沿って配設される。補強部４４の配線基板１２、１４と接する面には接着剤４８が塗布されている。接着剤４８は配線基板１４に予め取り付けておくこともできる。図１１は、接着剤４８が配線基板１４に塗布された図を示す。隙間４６とスリット５０にあたる部分には塗布されていない。接着剤４８は補強部４４を配線基板１２、１４に固定するものである。   10 to 12, non-closed (discontinuous) annular (frame-shaped) reinforcing portions 44 are arranged along the four sides of the wiring boards 12 and 14. An adhesive 48 is applied to the surface of the reinforcing portion 44 that contacts the wiring boards 12 and 14. The adhesive 48 can be attached to the wiring board 14 in advance. FIG. 11 shows a diagram in which the adhesive 48 is applied to the wiring board 14. The portion corresponding to the gap 46 and the slit 50 is not applied. The adhesive 48 fixes the reinforcing portion 44 to the wiring boards 12 and 14.

補強部４４の配線基板１２、１４の一隅に近い位置に隙間４６を設ける。接着剤４８は補強部４４の隙間４６に相当する位置及び隙間４６と対角線上の位置にスリット５０を有する。従って、この場合にも、配線基板１２、１４の四隅及び辺の中央部に外的な機械的ストレスが加わった場合に、配線基板１２、１４のクラックの発生を低減できる。また、補強部４４が略環状になっているので、積層型半導体装置１０の剛性が高まり、熱時の反りや変形をも軽減することができる。補強部４４に隙間４６があり且つ接着剤４８にスリット５０が入っているため、配線基板積層時の洗浄工程において、配線基板の間の接続端子部に洗浄液を容易に流入および流出させることができる。   A gap 46 is provided at a position near the corners of the wiring boards 12 and 14 of the reinforcing portion 44. The adhesive 48 has slits 50 at positions corresponding to the gap 46 of the reinforcing portion 44 and at positions diagonal to the gap 46. Accordingly, in this case as well, the occurrence of cracks in the wiring boards 12 and 14 can be reduced when an external mechanical stress is applied to the four corners and the central part of the sides of the wiring boards 12 and 14. In addition, since the reinforcing portion 44 has a substantially annular shape, the rigidity of the stacked semiconductor device 10 is increased, and warpage and deformation during heat can be reduced. Since the reinforcing portion 44 has the gap 46 and the adhesive 48 has the slit 50, the cleaning liquid can easily flow into and out of the connection terminal portions between the wiring boards in the cleaning process when the wiring boards are stacked. .

図１３及び図１４においては、閉じた（連続な）環状（枠状）の補強部４４が配線基板１２、１４の４辺に沿って配置される。補強部４４の配線基板１２、１４と接する面には接着剤４８が塗布又は取り付けられている。この例では、補強部４４には図１０の隙間４６がない。このため、補強部４４の剛性はより高くなる。従って、この場合にも、配線基板１２、１４の四隅あるいは辺の中央部に外的な機械的ストレスが加わった場合に、配線基板１２、１４のクラックの発生を防止することができる。配線基板１２、１４の四隅に近い位置に接着剤４８の塗布されていないスリット５０を有する。よって、配線基板積層時の洗浄工程において、配線基板の間の接続端子部に洗浄液を容易に流入および流出させることができる。   In FIGS. 13 and 14, closed (continuous) annular (frame-shaped) reinforcing portions 44 are arranged along the four sides of the wiring boards 12 and 14. An adhesive 48 is applied or attached to the surface of the reinforcing portion 44 that contacts the wiring boards 12 and 14. In this example, the reinforcing portion 44 does not have the gap 46 of FIG. For this reason, the rigidity of the reinforcement part 44 becomes higher. Therefore, also in this case, when external mechanical stress is applied to the four corners or the central part of the side of the wiring boards 12 and 14, the occurrence of cracks in the wiring boards 12 and 14 can be prevented. There are slits 50 to which the adhesive 48 is not applied at positions close to the four corners of the wiring boards 12 and 14. Accordingly, the cleaning liquid can easily flow into and out of the connection terminal portions between the wiring boards in the cleaning process when wiring boards are stacked.

図８から図１４の補強部４４は上記したグループ（ａ）から（ｅ）のいずれかの材料により形成することができる。   The reinforcing portion 44 in FIGS. 8 to 14 can be formed of any of the materials in the groups (a) to (e) described above.

図１５及び図１６は第５の実施例を示す図である。   15 and 16 are views showing a fifth embodiment.

この例においては、上下の配線基板１２、１４を接続するはんだボール（電極端子）２４と同じ材料で構成され、補強部４４は上下の配線基板１２、１４の四隅に配置される。かかる構成によれば、補強部４４が電極端子と同じ材料により構成されるので、材料コストを低減でき、組立て工程も従来と同様にできる。配線基板１２、１４の四隅が補強部４４によって支持固定されているので、外的な機械的ストレスが配線基板１２、１４の端部に加わった場合に、配線基板のクラック１２、１４の発生を低減できる。尚、上方の配線基板１２を樹脂４２で封止してある。   In this example, it is made of the same material as the solder balls (electrode terminals) 24 that connect the upper and lower wiring boards 12 and 14, and the reinforcing portions 44 are arranged at the four corners of the upper and lower wiring boards 12 and 14. According to such a configuration, since the reinforcing portion 44 is made of the same material as the electrode terminal, the material cost can be reduced, and the assembly process can be performed in the same manner as the conventional one. Since the four corners of the wiring boards 12 and 14 are supported and fixed by the reinforcing portions 44, when external mechanical stress is applied to the ends of the wiring boards 12 and 14, the generation of cracks 12 and 14 on the wiring boards is prevented. Can be reduced. The upper wiring board 12 is sealed with a resin 42.

図１７（Ａ）〜（Ｄ）は第５の実施例の変形例を示す図である。図１７（Ａ）においては、上下の配線基板１２、１４の四隅に複数の補強部４４が配設される。補強部４４ははんだボール２４と同じ材料で作られる。これによって、上下の配線基板１２、１４の四隅をより強化することができる。   FIGS. 17A to 17D are views showing a modification of the fifth embodiment. In FIG. 17A, a plurality of reinforcing portions 44 are disposed at the four corners of the upper and lower wiring boards 12 and 14. The reinforcing portion 44 is made of the same material as the solder ball 24. As a result, the four corners of the upper and lower wiring boards 12 and 14 can be further strengthened.

図１７（Ｂ）においては、複数の補強部４４が上下の配線基板１２、１４の四隅及び辺の中央部に配置される。補強部４４ははんだボール２４と同じ材料で作られる。これによって、上下の配線基板１２、１４の四隅及び辺をより強化することができる。   In FIG. 17B, a plurality of reinforcing portions 44 are arranged at the four corners and the central portion of the sides of the upper and lower wiring boards 12 and 14. The reinforcing portion 44 is made of the same material as the solder ball 24. Thereby, the four corners and sides of the upper and lower wiring boards 12 and 14 can be further strengthened.

図１７（Ｃ）においては、補強部４４が上下の配線基板１２、１４の四隅ではんだボール２４の最外側の列の延長線上に配置される。補強部４４をはんだボール２４と等ピッチをなす位置に配置することで、試験ソケットの作成が容易になる。補強部４４ははんだボール２４と同じ材料で作られる。これによって、上下の配線基板１２、１４の四隅を強化することができる。   In FIG. 17C, the reinforcing portions 44 are arranged on the extended lines of the outermost rows of the solder balls 24 at the four corners of the upper and lower wiring boards 12 and 14. By arranging the reinforcing portion 44 at a position that makes an equal pitch with the solder balls 24, it is easy to create a test socket. The reinforcing portion 44 is made of the same material as the solder ball 24. Thereby, the four corners of the upper and lower wiring boards 12 and 14 can be strengthened.

図１７（Ｄ）においては、補強部４４が上下の配線基板１２、１４の四隅ではんだボール２４の最外側の直交する２つの列の交差部に配置される。はんだボール２４（電極端子）の列が配線基板１２、１４の側縁部近傍に配置されている場合には、最外側のはんだボール２４の列の列上に配置され、はんだボール２４と等ピッチで配置することで、試験ソケットの作成が容易になる。補強部４４ははんだボール２４と同じ材料で作られる。これによって、上下の配線基板１２、１４の四隅を強化することができる。   In FIG. 17D, the reinforcing portions 44 are arranged at the intersections of the two outermost orthogonal rows of the solder balls 24 at the four corners of the upper and lower wiring boards 12 and 14. When the rows of solder balls 24 (electrode terminals) are arranged in the vicinity of the side edges of the wiring boards 12 and 14, they are arranged on the row of the outermost solder balls 24 and have the same pitch as the solder balls 24. This makes it easy to create a test socket. The reinforcing portion 44 is made of the same material as the solder ball 24. Thereby, the four corners of the upper and lower wiring boards 12 and 14 can be strengthened.

図１８及び図１９は第６の実施例を示す図である。本実施例は、第１実施例と第５の実施例とを組み合わせたものに相当する。上方の配線基板１２の外形は大きく、樹脂４２で封止されている。上方の配線基板１２の外形と封止樹脂４２の外形は等しい。補強部４４は上下の配線基板１２、１４の四隅に配置され、上下の配線基板１２、１４を電気的に接続するはんだボール（電極端子）２４と同じ材料で形成されている。従って、複数の配線基板の積層の位置ずれが生じても、クラックの発生を低減できる。   18 and 19 are views showing a sixth embodiment. This embodiment corresponds to a combination of the first embodiment and the fifth embodiment. The upper wiring board 12 has a large outer shape and is sealed with a resin 42. The outer shape of the upper wiring board 12 and the outer shape of the sealing resin 42 are the same. The reinforcing portions 44 are disposed at the four corners of the upper and lower wiring boards 12 and 14 and are formed of the same material as the solder balls (electrode terminals) 24 that electrically connect the upper and lower wiring boards 12 and 14. Therefore, even if the positional deviation of the lamination of the plurality of wiring boards occurs, the generation of cracks can be reduced.

尚、補強部４４は、はんだボールと同じ材料の他に、一般の電極に用いられる材料を用いてもよい。   The reinforcing portion 44 may be made of a material used for a general electrode in addition to the same material as the solder ball.

本発明の第７実施例を、図１５、図１６に示す。   A seventh embodiment of the present invention is shown in FIGS.

本実施例にあっては、前記第１の実施例にて採られた構成と、前記第５実施例にて採られた構成を含んでいる。   The present embodiment includes the configuration adopted in the first embodiment and the configuration adopted in the fifth embodiment.

即ち、一方の主面に半導体素子が搭載された配線基板１２は、同じく半導体素子が搭載された配線基板１４よりも、その外形サイズ（寸法）が大とされている。   That is, the wiring board 12 on which the semiconductor element is mounted on one main surface has a larger outer size (dimension) than the wiring board 14 on which the semiconductor element is mounted.

前記配線基板の一方の主面に搭載された半導体素子は、樹脂４２によって封止されている。樹脂４２の外形寸法は、配線基板１２と同じとされ、当該配線基板１２の側面は表出している。   The semiconductor element mounted on one main surface of the wiring board is sealed with a resin 42. The external dimensions of the resin 42 are the same as those of the wiring board 12, and the side surface of the wiring board 12 is exposed.

又、配線基板１２と下方の配線基板１４とは、その隅部に配設されたはんだボールからなる補強部４４によって、機械的に一体化されている。   Further, the wiring board 12 and the lower wiring board 14 are mechanically integrated by a reinforcing portion 44 made of a solder ball disposed at the corner.

このような構成によれば、上方の配線基板１２及び封止樹脂４２を基準として、当該積層型半導体装置１０を認識し、ハンドリングすることができる。   According to such a configuration, the stacked semiconductor device 10 can be recognized and handled with reference to the upper wiring substrate 12 and the sealing resin 42.

従って、ハンドリング用治具などが予期せぬ箇所に接触することを防止することができ、もって配線基板にクラックなどを生じることが無い。   Therefore, it is possible to prevent the handling jig or the like from coming into contact with an unexpected part, and thus the wiring board is not cracked.

また、配線基板１２と配線基板１４とが機械的に一体化されることにより、配線基板としての剛性が向上し、機械的なストレスが加わった場合にも、当該配線基板へのクラックの発生を防止することができる。   Further, since the wiring board 12 and the wiring board 14 are mechanically integrated, the rigidity as the wiring board is improved, and even when mechanical stress is applied, the generation of cracks in the wiring board is prevented. Can be prevented.

〔付記１〕 少なくとも１つの半導体素子が実装された基板を、複数積載してなる積層型半導体装置において、
該複数の基板のうち、少なくとも１つの基板の外形寸法は、他の基板の外形寸法より大きく、
該少なくとも１つの基板の外形寸法が該搭載型半導体装置の最大外形寸法と等しく、
該複数の基板のうち最下段の基板にのみ外部電極端子が設けられている
ことを特徴とする積層型半導体装置。
〔付記２〕 該複数の基板のうち、最上段の基板の外形寸法が、該最上段の基板よりも下に位置する基板の外形寸法より大きい
ことを特徴とする付記１に記載の積層型半導体装置。
〔付記３〕 該複数の基板のうち、最上段に位置する基板の半導体素子が実装された表面が樹脂封止されており、
該樹脂の外形寸法が該最上に位置する基板の外形寸法と等しい
ことを特徴とする付記２に記載の積層型半導体装置。 [Appendix 1] In a stacked semiconductor device in which a plurality of substrates on which at least one semiconductor element is mounted are stacked.
Outer dimensions of at least one of the plurality of substrates are larger than outer dimensions of other substrates,
The external dimension of the at least one substrate is equal to the maximum external dimension of the mounted semiconductor device;
An external electrode terminal is provided only on the lowermost substrate among the plurality of substrates.
[Appendix 2] The stacked semiconductor according to appendix 1, wherein an outer dimension of the uppermost substrate of the plurality of substrates is larger than an outer dimension of a substrate located below the uppermost substrate. apparatus.
[Appendix 3] Of the plurality of substrates, the surface of the substrate located on the uppermost stage on which the semiconductor element is mounted is resin-sealed.
3. The stacked semiconductor device according to appendix 2, wherein the outer dimension of the resin is equal to the outer dimension of the uppermost substrate.

〔付記４〕 該複数の基板のうち、最下段の基板の外形寸法が、該最下段の基板よりも上に位置する基板の外形寸法より大きい
ことを特徴とする付記１に記載の積層型半導体装置。
〔付記５〕 少なくとも１つの半導体素子が実装された基板を、複数積載してなる積層型半導体装置において、
該複数の基板の少なくとも隅部において、該複数の基板間を機械的に接合する補強部が配置されている
ことを特徴とする積層型半導体装置。
〔付記６〕 該支持部材は、対向する該複数の基板の４隅に複数個配置されている
ことを特徴とする付記５に記載の積層型半導体装置。
〔付記７〕 該補強部は、対向する該複数の基板の外周の少なくとも対向する２辺において、辺にわたって配置されている
ことを特徴とする付記５に記載の積層型半導体装置。
〔付記８〕 該補強部は、対向する該複数の基板の外周に沿って配置されている
ことを特徴とする付記５に記載の積層型半導体装置。
〔付記９〕 該補強部は、該複数の基板のコア材と同じ材料あるいは、エポキシ、ポリイミド、アクリル等の樹脂あるいは、Ｃｕ、Ａｌ、Ｗ、Ｆｅ、Ｎｉ、４２アロイ材等の金属およびそれらの合金からなる
ことを特徴とする付記５乃至付記８に記載の積層型半導体装置。 [Appendix 4] The stacked type semiconductor according to appendix 1, wherein an outer dimension of a lowermost substrate of the plurality of substrates is larger than an outer dimension of a substrate located above the lowermost substrate. apparatus.
[Appendix 5] In a stacked semiconductor device in which a plurality of substrates on which at least one semiconductor element is mounted are stacked,
A laminated semiconductor device, wherein a reinforcing portion for mechanically joining the plurality of substrates is disposed at least at a corner portion of the plurality of substrates.
[Appendix 6] The stacked semiconductor device according to Appendix 5, wherein a plurality of the support members are arranged at four corners of the plurality of substrates facing each other.
[Supplementary Note 7] The stacked semiconductor device according to Supplementary Note 5, wherein the reinforcing portion is disposed over at least two opposing sides of the outer circumferences of the opposing substrates.
[Appendix 8] The stacked semiconductor device according to Appendix 5, wherein the reinforcing portion is disposed along the outer periphery of the plurality of substrates facing each other.
[Supplementary Note 9] The reinforcing portion is made of the same material as the core material of the plurality of substrates, a resin such as epoxy, polyimide, or acrylic, or a metal such as Cu, Al, W, Fe, Ni, or 42 alloy material, and their 9. The stacked semiconductor device according to appendix 5 to appendix 8, which is made of an alloy.

〔付記１０〕 該補強部は、該複数の基板に接着剤によって固定されている
ことを特徴とする付記５乃至付記９に記載の積層型半導体装置。
〔付記１１〕 該補強部は、該複数の基板を電気的に接続する電極端子と同じ材料からなる
ことを特徴とする付記５に記載の積層型半導体装置。
〔付記１２〕 該複数の基板の材質が有機樹脂を含む材料からなる
ことを特徴とする付記５乃至付記１１に記載の積層型半導体装置。 [Supplementary Note 10] The stacked semiconductor device according to any one of Supplementary Notes 5 to 9, wherein the reinforcing portion is fixed to the plurality of substrates with an adhesive.
[Appendix 11] The stacked semiconductor device according to Appendix 5, wherein the reinforcing portion is made of the same material as the electrode terminal that electrically connects the plurality of substrates.
[Supplementary Note 12] The stacked semiconductor device according to any one of Supplementary Notes 5 to 11, wherein the plurality of substrates are made of a material containing an organic resin.

〔付記１３〕 該複数の基板のうち、少なくとも１つの基板の外形寸法は、他の基板の外形寸法より大きく、
該少なくとも１つの基板の外形寸法が該搭載型半導体装置の最大外形寸法と等しい
ことを特徴とする付記５乃至付記１２に記載の積層型半導体装置。 [Supplementary Note 13] Of the plurality of substrates, the outer dimension of at least one substrate is larger than the outer dimensions of the other substrates.
13. The stacked semiconductor device according to appendix 5 to appendix 12, wherein an external dimension of the at least one substrate is equal to a maximum external dimension of the mounted semiconductor device.

以上説明したように、本発明によれば、配線基板のクラックの発生を防止することができるようにした積層型半導体装置を得ることができる。   As described above, according to the present invention, it is possible to obtain a stacked semiconductor device capable of preventing the occurrence of cracks in the wiring board.

本発明の第１実施例の積層型半導体装置を示す断面図である。1 is a cross-sectional view showing a stacked semiconductor device according to a first embodiment of the present invention. 本発明の第２実施例の積層型半導体装置を示す断面図である。It is sectional drawing which shows the laminated semiconductor device of 2nd Example of this invention. 本発明の第３実施例の積層型半導体装置を示す断面図である。It is sectional drawing which shows the laminated semiconductor device of 3rd Example of this invention. 第１実施例の積層型半導体装置を上から見た略断面図である。1 is a schematic cross-sectional view of a stacked semiconductor device according to a first embodiment as viewed from above. 従来の積層型半導体装置を上から見た略断面図である。It is the general sectional view which looked at the conventional lamination type semiconductor device from the top. 本発明の第４実施例の積層型半導体装置を示す断面図である。It is sectional drawing which shows the laminated semiconductor device of 4th Example of this invention. 図６の積層型半導体装置の上方の配線基板のはんだボール及び支持部材を通る断面図である。FIG. 7 is a cross-sectional view passing through solder balls and support members of a wiring board above the stacked semiconductor device of FIG. 第４実施例の変形例を示す配線基板の断面図である。It is sectional drawing of the wiring board which shows the modification of 4th Example. 第４実施例の変形例を示す配線基板の断面図である。It is sectional drawing of the wiring board which shows the modification of 4th Example. 第４実施例の変形例を示す配線基板の断面図である。It is sectional drawing of the wiring board which shows the modification of 4th Example. 図１０の配線基板の底面図である。It is a bottom view of the wiring board of FIG. 配線基板に塗布された接着剤を示す図である。It is a figure which shows the adhesive agent apply | coated to the wiring board. 第４実施例の変形例を示す配線基板の断面図である。It is sectional drawing of the wiring board which shows the modification of 4th Example. 図１３の配線基板の底面図である。It is a bottom view of the wiring board of FIG. 本発明の第５実施例の積層型半導体装置を示す断面図である。It is sectional drawing which shows the laminated semiconductor device of 5th Example of this invention. 図１５の積層型半導体装置の上方の配線基板のはんだボール及び支持部材を通る断面図である。FIG. 16 is a cross-sectional view passing through solder balls and a support member of a wiring board above the stacked semiconductor device of FIG. 図１６の変形例を示す配線基板の断面図である。It is sectional drawing of the wiring board which shows the modification of FIG. 本発明の第６実施例の積層型半導体装置を示す断面図である。It is sectional drawing which shows the laminated semiconductor device of 6th Example of this invention. 図１６の積層型半導体装置の上方の配線基板のはんだボール及び支持部材を通る断面図である。FIG. 17 is a cross-sectional view passing through solder balls and a support member of a wiring board above the stacked semiconductor device of FIG. 16.

符号の説明Explanation of symbols

１０ 積層型半導体装置
１２、１４、１６ 配線基板
１８ 半導体素子
２４ はんだボール
２６ 半導体素子
３２ 外部接続電極
３４ 半導体素子
４０ 外部接続電極
４２ 封止樹脂
４４ 補強部
４６ 隙間
５０ スリット DESCRIPTION OF SYMBOLS 10 Laminated semiconductor device 12, 14, 16 Wiring board 18 Semiconductor element 24 Solder ball 26 Semiconductor element 32 External connection electrode 34 Semiconductor element 40 External connection electrode 42 Sealing resin 44 Reinforcement part 46 Gap 50 Slit

Claims (7)

少なくとも１つの半導体素子が実装された基板を、複数積載してなる積層型半導体装置において、
該複数の基板の少なくとも隅部において、該複数の基板間を機械的に接合する補強部が配置されている
ことを特徴とする積層型半導体装置。 In a stacked semiconductor device in which a plurality of substrates on which at least one semiconductor element is mounted are stacked,
A laminated semiconductor device, wherein a reinforcing portion for mechanically joining the plurality of substrates is disposed at least at a corner portion of the plurality of substrates. 該支持部材は、対向する該複数の基板の４隅に複数個配置されている
ことを特徴とする請求項１に記載の積層型半導体装置。 2. The stacked semiconductor device according to claim 1, wherein a plurality of the supporting members are arranged at four corners of the plurality of substrates facing each other. 該補強部は、対向する該複数の基板の外周の少なくとも対向する２辺において、辺にわたって配置されている
ことを特徴とする請求項１に記載の積層型半導体装置。 2. The stacked semiconductor device according to claim 1, wherein the reinforcing portion is arranged over at least two opposing sides of the outer periphery of the plurality of opposing substrates. 該補強部は、対向する該複数の基板の外周に沿って配置されている
ことを特徴とする請求項１に記載の積層型半導体装置。 2. The stacked semiconductor device according to claim 1, wherein the reinforcing portion is disposed along the outer periphery of the plurality of substrates facing each other. 該補強部は、該複数の基板に接着剤によって固定されている
ことを特徴とする請求項１乃至請求項４に記載の積層型半導体装置。 The stacked semiconductor device according to claim 1, wherein the reinforcing portion is fixed to the plurality of substrates with an adhesive. 該補強部は、該複数の基板を電気的に接続する電極端子と同じ材料からなる
ことを特徴とする請求項１に記載の積層型半導体装置。 The stacked semiconductor device according to claim 1, wherein the reinforcing portion is made of the same material as the electrode terminal that electrically connects the plurality of substrates. 該複数の基板のうち、少なくとも１つの基板の外形寸法は、他の基板の外形寸法より大きく、
該少なくとも１つの基板の外形寸法が該搭載型半導体装置の最大外形寸法と等しい
ことを特徴とする請求項１に記載の積層型半導体装置。 Outer dimensions of at least one of the plurality of substrates are larger than outer dimensions of other substrates,
2. The stacked semiconductor device according to claim 1, wherein an outer dimension of the at least one substrate is equal to a maximum outer dimension of the mounted semiconductor device.
JP2007228247A 2007-09-03 2007-09-03 Multilayer semiconductor device Pending JP2007318183A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2071411A1 (en) 2007-12-10 2009-06-17 Ricoh Company, Ltd. Corona charger, and process cartridge and image forming apparatus using same
WO2012035972A1 (en) * 2010-09-17 2012-03-22 住友ベークライト株式会社 Semiconductor package and semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831872A (en) * 1994-07-13 1996-02-02 Hitachi Ltd Semiconductor device
JPH09205113A (en) * 1996-01-26 1997-08-05 Toshiba Corp Semiconductor device, mounting substrate and mounting construction body
JP2000022034A (en) * 1998-07-01 2000-01-21 Hitachi Ltd Connection structure of electronic circuit device
JP2000174200A (en) * 1998-12-03 2000-06-23 Rohm Co Ltd Structure of multi-layer hybrid integrated circuit device and manufacture thereof
JP2001068594A (en) * 1999-06-22 2001-03-16 Mitsubishi Electric Corp Electronic circuit package, packaging board, and packaging body
JP2001094002A (en) * 1999-09-21 2001-04-06 Nec Corp Method and structure for mounting bga
JP2002083922A (en) * 2000-09-05 2002-03-22 Seiko Epson Corp Semiconductor device and its manufacturing method, and circuit board and electronic equipment
JP2002170924A (en) * 2000-11-29 2002-06-14 Kyocera Corp Laminated type semiconductor device and mounting board

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831872A (en) * 1994-07-13 1996-02-02 Hitachi Ltd Semiconductor device
JPH09205113A (en) * 1996-01-26 1997-08-05 Toshiba Corp Semiconductor device, mounting substrate and mounting construction body
JP2000022034A (en) * 1998-07-01 2000-01-21 Hitachi Ltd Connection structure of electronic circuit device
JP2000174200A (en) * 1998-12-03 2000-06-23 Rohm Co Ltd Structure of multi-layer hybrid integrated circuit device and manufacture thereof
JP2001068594A (en) * 1999-06-22 2001-03-16 Mitsubishi Electric Corp Electronic circuit package, packaging board, and packaging body
JP2001094002A (en) * 1999-09-21 2001-04-06 Nec Corp Method and structure for mounting bga
JP2002083922A (en) * 2000-09-05 2002-03-22 Seiko Epson Corp Semiconductor device and its manufacturing method, and circuit board and electronic equipment
JP2002170924A (en) * 2000-11-29 2002-06-14 Kyocera Corp Laminated type semiconductor device and mounting board

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2071411A1 (en) 2007-12-10 2009-06-17 Ricoh Company, Ltd. Corona charger, and process cartridge and image forming apparatus using same
WO2012035972A1 (en) * 2010-09-17 2012-03-22 住友ベークライト株式会社 Semiconductor package and semiconductor device

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