JP2002170924A - Laminated type semiconductor device and mounting board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a laminated type semiconductor device and a mounting board which are excellent in electrical connecting property with an external circuit board and have high reliability. SOLUTION: This laminated type semiconductor device is constituted by laminating a plurality of semiconductor devices 7 which are provided with wiring boards 3 having conductor layers 15 inside insulating boards 13, and with semiconductor elements 5 arranged on surfaces of the wiring boards 3. A plurality of connection terminals 23 electrically connected with the conductor layers 15 of the wiring boards 3 are arranged between the upper and the lower semiconductor devices 7, and on the lower surface of the semiconductor device 7 of the lowermost layer. Auxiliary connection terminals 27 which are not electrically connected with the conductor layers 15 of the wiring boards 3 are arranged in the outer peripheral part of a connection terminal group 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element mounted thereon, and more particularly to a stacked semiconductor device and a mounting substrate.

[0002]

2. Description of the Related Art In recent years, with the increase in speed and integration of semiconductor devices and the rapid spread of portable devices, there has been an increasing demand for smaller and lighter electronic devices. Along with this, the development of high-density mounting technology for semiconductor elements and electronic components has been promoted, but the mounting area inside electronic equipment is limited,
Considering the transmission speed, it is required to arrange semiconductor elements close to each other, and a more compact mounting technique is required.

In general, in a semiconductor device, the number of electrodes formed on the semiconductor device increases as the degree of integration of the transistor increases. Therefore, it is necessary to increase the number of terminals of a wiring board that houses the semiconductor device. However, as the number of electrodes increases, the dimensions of the wiring board itself increase, leading to an increase in mounting area.

For this reason, in recent years, a wiring board compatible with high-density mounting is formed by arranging connection terminals containing solder in a lattice pattern on the lower surface of the wiring board, thereby enabling a surface-mounted ball grid array (BGA) type. Wiring boards are the mainstream. Among such BGA type wiring boards, in order to further reduce the mounting area, a chip scale package (C) in which the size of the wiring board is made closer to the size of the semiconductor element.
The shift to small-sized wiring boards referred to as SP) is in progress.

[0005] These approaches are based on the premise that a wiring board is mounted on an external circuit board two-dimensionally (two-dimensionally), and it is in principle impossible to reduce the mounting area from the total area of the semiconductor elements. is there. That is, the two-dimensional mounting method has a limit in increasing the density.

For this reason, a stacked semiconductor device has been proposed in which a semiconductor device itself having a semiconductor element mounted on a wiring board is three-dimensionally stacked. As such a stacked semiconductor device, for example, a device disclosed in Japanese Patent Application Laid-Open No. Hei 6-13541 is known.

In the stacked semiconductor device disclosed in this publication, a high thermal conductive material such as aluminum nitride ceramics is used for the wiring substrates of the upper and lower semiconductor devices, and the upper and lower layers of the semiconductor devices are adjacent to each other. Solder bumps are formed on the interface side and joined.

As described above, the mounting method in which the semiconductor devices are three-dimensionally stacked is intended to further increase the density of semiconductor elements and electronic components as compared with the conventional mounting of the two-dimensionally arranged semiconductor devices. Therefore, the wiring length between the semiconductor element and the semiconductor device on which the semiconductor element is mounted can be reduced, which leads to an increase in the speed of transmission of a signal transmitted from a driving circuit of the semiconductor element.

[0009]

However, in Japanese Patent Application Laid-Open No. Hei 6-13541, a high thermal conductive material such as an aluminum nitride ceramic is used as a material for the upper and lower wiring boards constituting the stacked semiconductor device. These wiring boards are physically and electrically joined by connection terminals provided on the interface side between adjacent upper and lower layers.

When such a laminated semiconductor device is mounted on an external circuit board such as a printed circuit board containing an organic resin such as a glass-epoxy resin composite material or a glass-polyimide resin composite material, the operating environment, the driving of the semiconductor elements, Due to the repeated heat generation and cooling associated with the shutdown, the connectivity between the external circuit board and the stacked semiconductor device is impaired, and there is a problem that stable connection cannot be maintained for a long period of time as compared with the conventional single-layer semiconductor device. Was.

[0011] This reduction in reliability is mainly due to the fact that thermal stress caused by the difference in thermal expansion coefficient between the wiring board and the external circuit board constituting the semiconductor device repeatedly acts on the connection terminals.
It is considered that the connection terminals are fatigued and eventually cracks and the like are generated.

With respect to such cracks generated in the connection terminals, if the semiconductor device mounted on the external circuit board is a single layer, the rigidity is not so high, so that the difference in thermal expansion can be reduced by the warpage of the wiring board. However, in a stacked semiconductor device in which a plurality of semiconductor devices are stacked, rigidity is increased, so that a difference in thermal expansion cannot be reduced due to warpage,
Thermal fatigue fracture due to thermal stress is likely to occur in the connection terminal.

As described above, the thermal fatigue failure is most likely to occur at the connection terminal connecting the stacked semiconductor device and the external circuit board, but also at the connection terminal connecting the semiconductor devices. However, there is a problem that thermal fatigue fracture occurs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a stacked semiconductor device and a mounting substrate which are excellent in electrical connectivity between semiconductor devices and between a semiconductor device and an external circuit board and can maintain stable connection for a long period of time. I do.

[0015]

According to the stacked semiconductor device of the present invention, a wiring board having a conductor layer inside an insulating substrate;
A plurality of semiconductor devices each including a semiconductor element provided on the surface of the wiring substrate are stacked, and between the upper and lower semiconductor devices and on the lower surface of the lowermost semiconductor device,
A plurality of connection terminals that are electrically connected to the conductor layer of the wiring board, and auxiliary connection terminals that are not electrically connected to the conductor layer of the wiring board are provided on an outer peripheral portion of the connection terminal group. It is.

According to such a configuration, even in a configuration in which the semiconductor device is stacked on the external circuit board, the stress generated in the connection terminal formed on the lower surface of the semiconductor device is supported by the auxiliary connection terminal, and the auxiliary connection terminal is supported. Since stress can be absorbed by the deformation of itself, even in the case of stacked semiconductor devices, fatigue disconnection of solder in the connection terminal group can be prevented and connection reliability can be dramatically improved.

In the stacked semiconductor device of the present invention, it is desirable that the lowermost semiconductor device has a higher thermal expansion coefficient than the upper semiconductor device.

For example, when a semiconductor device is stacked on an external circuit board and connected, the stress generated in the lowermost semiconductor device can be relieved due to a difference in thermal expansion between the semiconductor device and the external circuit board. Fatigue disconnection of the group can be prevented, and connection reliability can be dramatically improved.

In the stacked semiconductor device according to the present invention, it is desirable that the thermal expansion coefficient of the stacked semiconductor devices be higher in lower layers.

For example, in a structure in which the semiconductor device is mounted on an external circuit board, even when the temperature changes due to the operating environment or the driving of the semiconductor element, the stacked semiconductor device is concavely formed and the center of curvature is formed together with the external circuit board. Since they are deformed to be the same, distortion due to the difference in thermal expansion between the upper and lower layers of the connection terminal can be reduced, and disconnection of the external circuit board and the semiconductor device, and disconnection of the connection terminal connecting the semiconductor devices can be prevented. , Connection reliability can be improved.

In the stacked semiconductor device of the present invention, the main surface of the wiring board has a rectangular shape, and a group of square connection terminals is provided on the main surface of the wiring substrate so as to correspond to the outer shape of the wiring substrate. It is desirable to provide auxiliary connection terminals at corners of the main surface of the wiring board.

It is known that, in a rectangular wiring board, the highest stress is generated in connection terminals formed near the corners and fatigue disconnection is likely to occur.
The auxiliary connection terminals can more effectively support the stress generated in the connection terminals formed on the lower surface of the wiring board, and can prevent the fatigue breakage of the solder in the connection terminal group and further improve the connection reliability.

In the mounting board of the present invention, the above-mentioned stacked semiconductor device is connected to an external circuit board via connection terminals and auxiliary connection terminals formed on the lower surface of the lowermost semiconductor device.

According to such a configuration, for example, even when the semiconductor device is connected to an external circuit board having a large difference in thermal expansion as compared with each semiconductor device to be stacked, for example, the semiconductor device may be connected to a corner of the semiconductor device. In particular, by forming an auxiliary connection terminal that is not electrically connected, the stress generated in the connection terminal group is supported by the auxiliary connection terminal, and fatigue disconnection of solder in the connection terminal group can be prevented, and connection reliability can be improved.

In the mounting board of the present invention, the lowermost wiring board to be joined to the external circuit board has a thermal expansion coefficient larger than that of the upper wiring board and higher than that of the external circuit board. Is also desirable.

According to such a configuration, for example, when the coefficient of thermal expansion of the external circuit board is larger than that of the semiconductor device bonded thereon, the semiconductor device bonded directly to the external circuit board can be used. Due to the difference in thermal expansion between the mounting substrate and the mounting substrate, the mounting substrate is warped in a concave shape, and the generated stress can be more effectively relieved.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure) One embodiment of a stacked semiconductor device of the present invention and a mounting board on which the semiconductor device is mounted will be described in detail with reference to a schematic sectional view of FIG.

The stacked semiconductor device 1 of the present invention is constituted by stacking a plurality of semiconductor devices 7 each having a semiconductor element 5 provided on the upper surface of a wiring board 3, and this stacked semiconductor device 1 is further mounted on an external circuit board 9. They are joined to form a mounting substrate 11.

The wiring substrate 3 constituting the semiconductor device 7 is formed by forming a conductor layer 15 inside an insulating substrate 13, and has a plurality of connection pads 1 on its upper and lower surfaces.
7 is formed, the conductor layer 15 and the connection pad 17 are connected via a via-hole conductor 19, and the semiconductor element 5 on the upper surface of the wiring board 3 and the connection pad 17 are connected by a wire 21.

A plurality of connection pads 17 are also formed on the upper and lower surfaces of the wiring board 3 of the semiconductor device 7 in the second and subsequent layers from the top, and are respectively connected to the internal conductor layer 15 via the via-hole conductors 19. .

The connection pads 17 of each wiring board 3 are mechanically and electrically connected to each other by connection terminals 23.

The outer peripheral portion of the connection terminal group 25, which is an aggregate of the plurality of connection terminals 23, is connected to the connection pad 17 of each wiring board 3, but is not connected to the conductor layer 15. An auxiliary connection terminal 27 is provided, and the upper and lower semiconductor devices 7 are mechanically connected.

The connection pads 17 on the lower surface of the wiring board 3 constituting the lowermost semiconductor device 7 are connected to the connection pads 17 formed on the surface of the external circuit board 9 on which the stacked semiconductor device 1 is mounted. The connection terminals 23 and the auxiliary connection terminals 27 are connected in the same manner as the wiring boards 3 are connected to each other.

As shown in FIG. 2A, these connection terminals 23 are formed in a lattice pattern on the lower surface of the wiring board 3 except for the portion where the semiconductor element 5 is mounted.
The main surface has a rectangular shape corresponding to the outer shape of the lower surface of the wiring substrate 3 having a rectangular shape, and auxiliary connection terminals 27 are provided at the corners of the main surface of the wiring substrate 3 located at the outer peripheral portion thereof. I have.

The size (area) and interval of these connection terminals 23 and auxiliary connection terminals 27 can be arbitrarily changed according to the total number of connection pads 17 formed on the upper and lower surfaces of the wiring board 3. it can.

The size of the connection pad 17 on which the auxiliary connection terminal 27 is formed may be the same size (area) as the connection pad 17 on which the connection terminal 23 is formed, but FIG. As shown in (2), the size can be increased to sufficiently support the stress generated in the connection terminals 23 formed on the lower surface of the wiring board 3.

Further, as shown in FIG. 2C, the size of the connection pad 17 forming the connection terminal 23 is
An interval is provided to the extent that a short circuit does not occur between the auxiliary connection terminal 3 and the auxiliary connection terminal 27. Further, in order to improve the effect of sufficiently supporting the stress of the auxiliary connection terminal 27, four corners of the wiring board 3 Or, the connection terminal group 2 which is regularly arranged
5 may be formed at a position apart from the extension of the lattice.

As shown in FIG. 1, the semiconductor element 5 provided on the wiring board 3 connects the semiconductor element 5 and the connection pads 17 formed on the wiring board 3 with wires 21 such as Al and Au. They are joined by a wire bonding method for connection, and hermetically sealed with a sealing resin.

As another method for mounting the semiconductor element 5, although not shown, a solder bump is formed between a terminal portion formed on one main surface thereof and a connection pad 17 formed on the wiring board 3. In addition, a flip-chip type joining method in which an underfill filler containing an organic resin is poured between the semiconductor element 5 and the wiring board 3 for sealing is used.

The wiring board 3 constituting the semiconductor device 7
Is preferably larger than the coefficient of thermal expansion of the semiconductor element 5 and smaller than that of the external circuit board 9, and is preferably in the range of ^{6 to} 13 × 10 ⁻⁶ (/ ° C.). . This is because the coefficient of thermal expansion of the semiconductor element 5 is 3-4.
× 10 ⁻⁶ (/ ° C.), and the external circuit board 9
Since a printed circuit board containing an organic resin having a thermal expansion coefficient of 13 to 25 × 10 ⁻⁶ (/ ° C.) is used in many cases, the thermal expansion coefficient of the wiring board 3 may have an intermediate value between them. This is because it is preferable in relieving stress.

It is desirable that the lowermost wiring board 3 of the stacked semiconductor device 1 has a larger thermal expansion coefficient than that of the upper wiring board 3.

For example, in the mounting board in which the stacked semiconductor device 1 is connected to the external circuit board 9, the one whose thermal expansion coefficient of the lowermost wiring board 3 is closer to the thermal expansion coefficient of the external circuit board 9 is the lowermost layer. This is because the stress generated in the connection terminals 23 of the wiring board 3 can be reduced.

That is, the thermal expansion coefficient of the lowermost wiring board 3 bonded to the external circuit board 9 is larger than the thermal expansion coefficient of the upper wiring board 3 and is smaller than the thermal expansion coefficient of the external circuit board 9. Desirably small.

(Material and Manufacturing Method) Semiconductor Device 7 of the Present Invention
The material of the insulating substrate 13 may be any of ceramics such as alumina and mullite and electric insulating materials such as glass ceramics fired at a low temperature. However, in the structure in which the stacked semiconductor device 1 is mounted,
In order to reduce the difference in thermal expansion between the components and reduce the generated stress, it is desirable that the insulating substrate 13 be made of a glass ceramic sintered body.

The connection terminals 23 and the auxiliary connection terminals 27 forming the stacked semiconductor device 1 and the mounting board 11 of the present invention
Is made of a metal material containing solder, and is connected to a connection pad 17 formed on the surface of the wiring board 3 via a metal layer containing at least one of gold, tin, and nickel.

The external circuit board 9 on which the stacked semiconductor device 1 of the present invention is mounted is made of a so-called printed board, and is made of an insulator made of a material containing an organic resin such as a glass-epoxy resin or a glass-polyimide resin composite material. And a wiring conductor made of a metal such as Cu, Au, Al, Ni, or Sn—Pb is formed on the surface and inside of the substrate. Hereinafter, such an external circuit board 9 may be simply referred to as a printed board.

(Operation) The stacked semiconductor device 1 of the present invention
A plurality of connection terminals 23 for electrically connecting to the connection pads 17 of the wiring board 3 are provided between the upper and lower semiconductor devices 7 and on the lower surface of the lowermost semiconductor device 7.
It is important to provide auxiliary connection terminals 27 that are not electrically connected to the conductor layer 15 of the wiring board 3 on the outer periphery of the wiring board 3.

For example, the auxiliary connection terminals 27 not particularly electrically connected to the corners of the wiring board 3 having a square main surface.
Is formed, the auxiliary connection terminal 27 supports the stress generated in the connection terminal 23 formed on the lower surface of the wiring board 3, prevents the solder from breaking due to solder in the connection terminal 23 made of solder, and dramatically improves connection reliability. Can be improved.

That is, in the case of the single-layer semiconductor device 7, the difference in thermal expansion between the semiconductor device 7 and the external circuit board 9 can be reduced by warping deformation. Is the semiconductor device 7 directly above the external circuit board 9
In the semiconductor device 7 at the second or higher stage from the bottom, the warpage deformation is small, and it is difficult to reduce the stress caused by the difference in thermal expansion with the external circuit board 9.

On the other hand, for example, when the auxiliary connection terminal 27 is provided at a corner of the main surface of the wiring substrate 3 formed in a square shape, the auxiliary connection terminal 27 is used instead of the wiring substrate 3.
Since the semiconductor device 7 itself deforms and plays a role of transmitting the stress, even when the semiconductor devices 7 are stacked, the stress generated in each semiconductor device 7 can be greatly reduced.

Further, by providing the auxiliary connection terminals 27, when solder paste is printed and laminated on the semiconductor device 7 and joined through reflow, the molten solder corrects the positions of the upper and lower pads by surface tension. The self-alignment effect can be enhanced.

When the stacked semiconductor device is driven as an active device, that is, when the temperature rises due to the driving of the semiconductor element 5, each wiring board 3 has a thermal expansion difference with the semiconductor element 5. Then, warpage deformation occurs such that the mounting side of the semiconductor element 5 becomes concave. However, the warpage (bending)
The amount is smaller for the lower wiring board 3.

This is because the lower wiring board 3 suppresses warpage (bending) deformation due to the presence of the upper wiring board 3. As a result, when the auxiliary connection terminals 27 are not provided, the thermal expansion difference between the lowermost wiring board 3 and the external circuit board 9 cannot be alleviated by warping (bending) deformation, so that thermal fatigue destruction appears remarkably.

On the other hand, as in the present invention, for example,
When the auxiliary connection terminals 27 are provided at the corners of the rectangular wiring board 3, the warpage (bending) deformations of the semiconductor devices 7 arranged between the upper and lower sides are transmitted to each other, so that the lowermost wiring board 3 is formed.
However, sufficient warping (bending) deformation is possible, and the difference in thermal expansion with the external circuit board 9 can be sufficiently reduced.

This is because when the stacked semiconductor device 1 is mounted on the external circuit board 9 and stress or strain is generated due to a temperature change or the like, between the stacked semiconductor devices 7 or between the semiconductor device 7 and the external circuit board. The auxiliary connection terminals 27 formed at the corners of the wiring board 3 between the semiconductor device 7 and the semiconductor device 7 serve as spacers, and can increase the area of the connection portion in addition to the connection terminals 23. And external circuit board 9
This is for reducing the compressive stress caused by the deformation of.

Further, since the auxiliary connection terminal 27 does not have electrical continuity, even if it is broken by thermal fatigue, it does not affect the reliability of the semiconductor device 7.

The effect of the auxiliary connection terminals 27 is particularly remarkable when the thermal expansion coefficient of at least the lowermost wiring board 3 is larger than the thermal expansion coefficients of the other wiring boards 3.
This is because the amount of warpage (bending) of the lowermost wiring board 3 is doubled not only by the external circuit board 9 but also by the thermal expansion difference with the upper wiring board 3, and as a result, the thermal expansion with the external circuit board 9 This is because the difference can be further reduced.

[0058]

EXAMPLE A wiring board was prepared from the two types of ceramic materials shown in Table 1, cut, and cut into 5 × 4 × 40 mm.
Was prepared. Then, the average thermal expansion coefficient of each sample substrate from room temperature to 400 ° C. was measured, and the results are shown in Table 1.

Further, a four-layer type stacked semiconductor device 1 composed of the combinations shown in Table 2 was prototyped using these wiring boards 3. At this time, the semiconductor element was mounted using a wire bonding method. In Table 2, the order of the layers is from the lower layer, and the first layer is the wiring board 3 connected to the external circuit board 9 at the lowermost layer.

The wiring board 3 was manufactured by conducting conductor processing on an insulating sheet formed by a doctor blade method, laminating a plurality of these sheets, and then firing.

The dimension of the manufactured wiring board 3 is 12
mm × width 12 mm × thickness 0.3 mm, and 5.5 mm in length × 5.5 m in width at the center for housing the semiconductor element 5.
A cavity of mx 0.2 mm in depth was provided. A semiconductor element 5 having a length of 4 mm, a width of 4 mm and a thickness of 0.1 mm was placed in the inside, and sealed with an epoxy resin after wire bonding. The semiconductor element 5 is provided on the front and back surfaces of the wiring board 3.
The connection terminal 23 having a diameter of 0.5 mm except for the portion where
Connection pads 17 are provided at a pitch of 0.8 mm.
The connection pad 17 for the auxiliary connection terminal 27 having a diameter of 1.0 mm was arranged at a corner of the wiring board 3.

Then, after solder paste is applied to the connection pads 17 of the semiconductor device 7, reflow is performed once to form the connection terminals 23 and the auxiliary connection terminals 27.
Each semiconductor device 7 is placed on the connection pad 17 of the external circuit board 9.
Were mounted on the external circuit board 9 in order, and a batch reflow process was performed again to manufacture the mounting board 11. The external circuit board 9 has a coefficient of thermal expansion of 17 × 10 ⁻⁶ (/ ° C.) and a size of 6
The size used was 7 mm x 67 mm x 1.25 mm in thickness.

A temperature cycle test of -40 ° C. to 125 ° C. is performed on the mounting board 11 thus manufactured up to 1500.
It went up to the cycle. External circuit board 9 used in the embodiment
Is provided with external connection pads so that the presence or absence of electrical conduction can be checked, and a tester can be used to detect a change in resistance of the mounting portion due to the connection terminal 23.

Then, the electrical resistance of the mounting portion by each connection terminal 23 of each stacked semiconductor device 1 is measured every 100 cycles, and the connection terminal 23 whose resistance changes by 10% or more at any one position with respect to the initial resistance is measured. Table 2 shows the number of appearances
It was shown to.

[0065]

[Table 1]

[0066]

[Table 2]

As is apparent from Table 2, the sample No. of the present invention manufactured by providing the auxiliary connection terminal 27 on the outer peripheral portion of the connection terminal group 25 of the wiring board. 1, 3, 5, 6, 7, 8, 9, 1,
0, the number of temperature cycle tests is 10
The thermal fatigue life could be prolonged when the number was 00 or more. The sample No. 3 in which the lowermost wiring board 3 has a larger thermal expansion coefficient than the other upper wiring boards 3 has. In 3, 5, and 6, the number of life cycles could be extended up to 1300 cycles. This is because the semiconductor device 7 having a larger thermal expansion coefficient is arranged in the lowermost layer of the stacked semiconductor device 1, so that the stacked semiconductor device 1 and the external circuit board 9 are concave and have the same center of curvature. Due to the deformation, the distortion due to the difference in thermal expansion between the upper and lower layers of the connection terminal 23 can be reduced, and the disconnection of the external circuit board 9 and the semiconductor device 7 and the connection terminal 23 connecting the semiconductor devices 7 can be prevented. Because it was done.

On the other hand, Sample No. in which the auxiliary connection terminal 27 was not formed. For 2, 4, and 11, the number of temperature cycles is 100
Less than 0 cycles.

[0069]

According to the present invention, in a stacked semiconductor device in which a plurality of semiconductor devices each having a semiconductor element provided on the surface of a wiring board are stacked, a semiconductor device between the vertically stacked semiconductor devices and a lowermost semiconductor device are provided. A plurality of connection terminals electrically connected to the conductor layer of the wiring board are provided on the lower surface of the wiring board, and auxiliary connection terminals not electrically connected to the conductor layer of the wiring board are provided on an outer peripheral portion of the connection terminal group, so that The auxiliary connection terminals support the stress generated in the connection terminals formed on the lower surface of the device, so that the fatigue breakage of the solder in the connection terminal group can be prevented and the connection reliability can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a stacked semiconductor device and a mounting substrate according to the present invention.

FIG. 2A is a plan view showing the arrangement of connection terminals arranged in a grid on the lower surface of a wiring board and auxiliary connection terminals provided at the same corners as the connection terminals; FIG. FIG. 3C is a plan view showing auxiliary connection terminals of different sizes provided at the corners of the connection terminal group arranged in a lattice on the lower surface of FIG. It is a top view which shows the auxiliary connection terminal provided outside the outermost row.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Stacked semiconductor device 3 Wiring board 5 Semiconductor element 7 Semiconductor device 9 External circuit board 11 Mounting board 13 Insulating board 15 Conductive layer 23 Connection terminal 25 Connection terminal group 27 Auxiliary connection terminal

Claims (5)

[Claims] A plurality of semiconductor devices each including a wiring substrate having a conductor layer inside an insulating substrate and a semiconductor element provided on a surface of the wiring substrate; A plurality of connection terminals that are electrically connected to the conductor layer of the wiring board are provided on the lower surface of the lower semiconductor device, and auxiliary connection terminals that are not electrically connected to the conductor layer of the wiring board on the outer periphery of the connection terminal group. A stacked semiconductor device, comprising: 2. The stacked semiconductor device according to claim 1, wherein a thermal expansion coefficient of the lowermost wiring board is larger than a thermal expansion coefficient of the upper wiring board. 3. A main surface of the wiring board has a square shape, and a group of connection terminals having a square shape is provided on the main surface of the wiring board so as to correspond to an outer shape of the wiring board. 3. The stacked semiconductor device according to claim 1, wherein auxiliary connection terminals are provided at the corners. 4. The stacked semiconductor device according to claim 1, wherein the stacked semiconductor device is joined to an external circuit board via connection terminals and auxiliary connection terminals provided on the lower surface of the lowermost semiconductor device. A mounting substrate. 5. A thermal expansion coefficient of a lowermost wiring board joined to an external circuit board is larger than a thermal expansion coefficient of an upper wiring board and smaller than a thermal expansion coefficient of the external circuit board. The mounting substrate according to claim 4, wherein