JP2007142124A - Semiconductor device, and method of manufacturing same - Google Patents

Semiconductor device, and method of manufacturing same Download PDF

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JP2007142124A
JP2007142124A JP2005333466A JP2005333466A JP2007142124A JP 2007142124 A JP2007142124 A JP 2007142124A JP 2005333466 A JP2005333466 A JP 2005333466A JP 2005333466 A JP2005333466 A JP 2005333466A JP 2007142124 A JP2007142124 A JP 2007142124A
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semiconductor device
intermediate electrode
substrate
land
carrier substrate
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Hiroyuki Takagi
博之 高木
Takahiro Nakano
高宏 中野
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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Abstract

<P>PROBLEM TO BE SOLVED: To improve a connection failure that occurs between semiconductor devices due to their warpings at high temperatures. <P>SOLUTION: The semiconductor device is composed of a first semiconductor device 10a and a second semiconductor device 10b, and the devices 10a and 10b are joined together by connecting a land 13b formed on the device 10a with a land 13c formed on the device 10b through the intermediary of an intermediate electrode 17. The outline 21 of a formation region with the intermediate electrode 17 is formed into a polygonal shape that has more sides than the external shape of the substrate 11b of the device 10a, so as to enable the intermediate electrode 17 to be formed avoiding the corner C of the device 10b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に、半導体装置の３次元実装構造に適用して好適なものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and is particularly suitable for application to a three-dimensional mounting structure of a semiconductor device.

従来の半導体装置には、２個以上の半導体装置を積層して構成されたものがある。
図７に示される半導体装置１００の場合には、第１の半導体装置１００ａの上に、第２の半導体装置１００ｂを実装して構成されている。 Some conventional semiconductor devices are configured by stacking two or more semiconductor devices.
In the case of the semiconductor device 100 shown in FIG. 7, the second semiconductor device 100b is mounted on the first semiconductor device 100a.

第１の半導体装置１００ａは、第１キャリア基板１０１ａの上に、半導体素子１０２ａがフリップチップ実装されている。また、第１キャリア基板１０１ａの裏面側にはランド１０３ａ、第１キャリア基板１０１ａの表面側にはランド１０３ｂがそれぞれ形成されている。また、ランド１０３ａに、第１キャリア基板１０１ａをマザー基板の上に実装するための外部電極１０４が設けられている。   In the first semiconductor device 100a, a semiconductor element 102a is flip-chip mounted on a first carrier substrate 101a. A land 103a is formed on the back side of the first carrier substrate 101a, and a land 103b is formed on the front side of the first carrier substrate 101a. The land 103a is provided with an external electrode 104 for mounting the first carrier substrate 101a on the mother substrate.

第２の半導体装置１００ｂは、第２キャリア基板１０１ｂの上に、接着層を介し半導体装置１０２ｂがフェイスアップ実装され、半導体素子１０２ｂは、導電性ワイヤ１０５を介してランド１０３ｄにワイヤボンド接続されている。第２キャリア基板１０１ｂの裏面側にはランド１０３ｃが形成されている。そして、第２キャリア基板１０１ｂの上に実装された第２の半導体素子１０２ｂは封止樹脂１０６で封止されている。   In the second semiconductor device 100b, the semiconductor device 102b is mounted face-up on the second carrier substrate 101b via an adhesive layer, and the semiconductor element 102b is wire-bonded to the land 103d via the conductive wire 105. Yes. A land 103c is formed on the back side of the second carrier substrate 101b. The second semiconductor element 102 b mounted on the second carrier substrate 101 b is sealed with a sealing resin 106.

また、ランド１０３ｃには、第２キャリア基板１０１ｂを第１キャリア基板１０１ａの上に実装するための多数の中間電極１０７が設けられている。図７（ｂ）は図７（ａ）の断面図における矢印Ａ−Ａ線に沿った矢視図で、第２キャリア基板１０１ｂの底面に多数設けられた中間電極１０７の配置は、第１の半導体装置１００ａに実装された半導体素子１０２ａの搭載個所に対応して、中央部には中間電極１０７が設けられていない正方形状のエリアＢが形成されている。
特開２００４−２８１９１９号公報 The land 103c is provided with a number of intermediate electrodes 107 for mounting the second carrier substrate 101b on the first carrier substrate 101a. FIG. 7B is an arrow view taken along the line AA in the cross-sectional view of FIG. 7A, and the arrangement of a large number of intermediate electrodes 107 provided on the bottom surface of the second carrier substrate 101b is as follows. A square area B in which the intermediate electrode 107 is not provided is formed at the center portion corresponding to the mounting position of the semiconductor element 102a mounted on the semiconductor device 100a.
JP 2004-281919 A

しかしながら、高温時の熱応力によって第１キャリア基板１０１ａに反りが発生し、第１の半導体装置１００ａと第２の半導体装置１００ｂとの隙間が部分的に大きくなり、例えば、図８に示すように一部の中間電極１０７が、第１キャリア基板１０１ａの表面側のランド１０３ｂに届かなくなることによる接続不良（オープン不良）が起こるという課題がある。   However, the first carrier substrate 101a is warped due to thermal stress at high temperature, and the gap between the first semiconductor device 100a and the second semiconductor device 100b is partially increased. For example, as shown in FIG. There is a problem in that some of the intermediate electrodes 107 fail to reach the land 103b on the surface side of the first carrier substrate 101a, resulting in poor connection (open failure).

本発明では、高温時の反りによる半導体装置間の接続不良を改善することを目的とする。   An object of the present invention is to improve poor connection between semiconductor devices due to warping at a high temperature.

本発明の請求項１記載の半導体装置は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、第２の半導体装置のコーナー部を避けて前記中間電極が形成されるように前記中間電極の形成領域の外郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に形成したことを特徴とする。   According to a first aspect of the present invention, there is provided a semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device. The intermediate electrode is formed on the outer surface of the second semiconductor device so that the intermediate electrode is formed so as to avoid the corner portion of the second semiconductor device. It is characterized in that it is formed in a polygonal shape having more sides than the outer shape of the substrate of the semiconductor device.

本発明の請求項２記載の半導体装置は、請求項１において、前記中間電極の形成領域の内郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に形成したことを特徴とする。   According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the outline of the formation region of the intermediate electrode is formed in a polygon shape having more sides than the outer shape of the substrate of the second semiconductor device. It is characterized by that.

本発明の請求項３記載の半導体装置は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、前記中間電極の形成領域の内郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に形成したことを特徴とする。   According to a third aspect of the present invention, a second semiconductor device is stacked on the first semiconductor device, and a land formed in the first semiconductor device and a land formed in the second semiconductor device. The intermediate electrode is formed in a polygonal shape having a larger number of sides than the outer shape of the substrate of the second semiconductor device. It is characterized by that.

本発明の請求項４記載の半導体装置は、請求項１〜請求項３のいずれかにおいて、第１の半導体装置の前記基板の中心と第２の半導体装置前記基板の中心が、一致していることを特徴とする。   A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the center of the substrate of the first semiconductor device coincides with the center of the second semiconductor device. It is characterized by that.

本発明の請求項５記載の半導体装置の製造方法は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の外郭を、第２の半導体装置のコーナー部を避けて前記中間電極が形成されるように第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に配列し、前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続することを特徴とする。   According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: stacking a second semiconductor device on the first semiconductor device, and forming the land formed on the first semiconductor device and the second semiconductor device. When forming the semiconductor device connected to the land formed through the intermediate electrode, the outline of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is defined by the second semiconductor device. Arranged in a polygonal shape having more sides than the outer shape of the substrate of the second semiconductor device so that the intermediate electrode is formed avoiding the corner portion, and the first semiconductor device is interposed via the intermediate electrode. The land formed is connected to the land formed in the second semiconductor device.

本発明の請求項６記載の半導体装置の製造方法は、請求項５において、前記中間電極の形成領域の内郭を、第１の半導体装置または第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に配列することを特徴とする。   The method for manufacturing a semiconductor device according to claim 6 of the present invention is the method for manufacturing a semiconductor device according to claim 5, wherein the inner region of the formation region of the intermediate electrode is located on the side of the outer shape of the substrate of the first semiconductor device or the second semiconductor device. Are arranged in a polygonal shape having a large number of.

本発明の請求項７記載の半導体装置の製造方法は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の内郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に配列し、前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続することを特徴とする。   According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein the second semiconductor device is stacked on the first semiconductor device, and the land formed on the first semiconductor device and the second semiconductor device are formed. When forming the semiconductor device connected to the land formed through the intermediate electrode, the outline of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is defined as the second semiconductor device. The lands formed in the first semiconductor device and the lands formed in the second semiconductor device are connected via the intermediate electrode, arranged in a polygonal shape having more sides than the outer shape of the substrate. It is characterized by that.

本発明の請求項８記載の半導体装置の製造方法は、請求項５〜請求項７のいずれかにおいて、第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心を一致させた状態で、前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続することを特徴とする。   The method of manufacturing a semiconductor device according to claim 8 of the present invention is the method of manufacturing a semiconductor device according to any one of claims 5 to 7, wherein the center of the substrate of the first semiconductor device is coincident with the center of the substrate of the second semiconductor device. In this state, the land formed in the first semiconductor device and the land formed in the second semiconductor device are connected via the intermediate electrode.

本発明の請求項９記載の半導体装置は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、前記中間電極の形成領域の外郭を、第２の半導体装置の基板の中心に対して同心円状に配列し、かつ第２の半導体装置のコーナー部を避けて前記中間電極を配列したことを特徴とする。   According to a ninth aspect of the present invention, there is provided a semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device. A semiconductor device connected to each other via an intermediate electrode, wherein the outer periphery of the formation region of the intermediate electrode is concentrically arranged with respect to the center of the substrate of the second semiconductor device, and the second semiconductor The intermediate electrodes are arranged so as to avoid corner portions of the apparatus.

本発明の請求項１０記載の半導体装置は、請求項９において、前記中間電極の形成領域の内郭を、第２の半導体装置の基板の中心に対して同心円状となるように形成したことを特徴とする。   According to a tenth aspect of the present invention, in the ninth aspect, the inner region of the formation region of the intermediate electrode is formed so as to be concentric with the center of the substrate of the second semiconductor device. Features.

本発明の請求項１１記載の半導体装置は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、前記中間電極の形成領域の内郭を、第２の半導体装置の基板の中心に対して同心円状に配列したことを特徴とする。   According to an eleventh aspect of the present invention, a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device. The intermediate device is connected to each other via an intermediate electrode, and the outline of the intermediate electrode formation region is arranged concentrically with respect to the center of the substrate of the second semiconductor device. .

本発明の請求項１２記載の半導体装置は、請求項９〜請求項１１のいずれかにおいて、 第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心が、一致していることを特徴とする。   According to a twelfth aspect of the present invention, in any one of the ninth to eleventh aspects, the center of the substrate of the first semiconductor device and the center of the substrate of the second semiconductor device are aligned. It is characterized by being.

本発明の請求項１３記載の半導体装置の製造方法は、第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の外郭を、第２の半導体装置のコーナー部を避けて前記中間電極が形成されるように同心円状に配列し、中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続することを特徴とする。   According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: stacking a second semiconductor device on the first semiconductor device, and forming the land formed on the first semiconductor device and the second semiconductor device. When forming the semiconductor device connected to the land formed through the intermediate electrode, the outline of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is defined by the second semiconductor device. Arranged concentrically so that the intermediate electrode is formed so as to avoid the corner portion, and the land formed in the first semiconductor device and the land formed in the second semiconductor device are connected via the intermediate electrode It is characterized by doing.

本発明の請求項１４記載の半導体装置の製造方法は、請求項１３において、前記中間電極の形成領域の内郭を、第１の半導体装置または第２の半導体装置の基板の中心に対して同心円状となるように形成することを特徴とする。   According to a fourteenth aspect of the present invention, there is provided the method for manufacturing a semiconductor device according to the thirteenth aspect, wherein the inner region of the intermediate electrode forming region is concentric with the center of the substrate of the first semiconductor device or the second semiconductor device. It forms so that it may become a shape.

本発明の請求項１５記載の半導体装置の製造方法は、１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の内郭を、第２の半導体装置の基板の中心に対して同心円状に配列し、前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続することを特徴とする。   According to a fifteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: stacking a second semiconductor device on a single semiconductor device; forming a land formed on the first semiconductor device and a second semiconductor device. In forming the semiconductor device connected to the land via the intermediate electrode, the outline of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is defined by the second semiconductor device. It is arranged concentrically with respect to the center of the substrate, and the land formed in the first semiconductor device and the land formed in the second semiconductor device are connected via the intermediate electrode.

本発明の請求項１６記載の半導体装置の製造方法は請求項１３〜請求項１５のいずれかにおいて、第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心を一致させた状態で、中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続することを特徴とする。   According to a sixteenth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the thirteenth to fifteenth aspects, the center of the substrate of the first semiconductor device and the center of the substrate of the second semiconductor device are matched. In this state, the land formed in the first semiconductor device and the land formed in the second semiconductor device are connected via the intermediate electrode.

これにより、反りの大きい部分の隙間を小さくすることにより、中間電極は、第１の半導体装置の基板と第２の半導体装置の基板とを接続することが可能となり、接続不良を改善できる。   As a result, by reducing the gap between the warped portions, the intermediate electrode can connect the substrate of the first semiconductor device and the substrate of the second semiconductor device, thereby improving the connection failure.

以下、本発明の実施例における半導体装置及び半導体装置の製造方法について図面を参照しながら説明する。
（実施の形態１）
図１と図２は本発明の（実施の形態１）を示す。 Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.
(Embodiment 1)
1 and 2 show (Embodiment 1) of the present invention.

図２（ａ）と図２（ｂ）は本発明の半導体装置１０の製造工程を示している。
図２（ａ）に示すように、第１の半導体装置１０ａと第２の半導体装置１０ｂを用意する。 2A and 2B show the manufacturing process of the semiconductor device 10 of the present invention.
As shown in FIG. 2A, a first semiconductor device 10a and a second semiconductor device 10b are prepared.

第１の半導体装置１０ａは、第１キャリア基板１１ａの上に半導体素子１２ａがフリップチップ実装されている。また、第１キャリア基板１１ａの裏面側にはランド１３ａ、第１キャリア基板１１ａの表面側にはランド１３ｂがそれぞれ形成されている。また、ランド１３ａには、第１キャリア基板１１ａをマザー基板の上に実装するための外部電極１４が設けられている。   In the first semiconductor device 10a, a semiconductor element 12a is flip-chip mounted on a first carrier substrate 11a. A land 13a is formed on the back side of the first carrier substrate 11a, and a land 13b is formed on the front side of the first carrier substrate 11a. The land 13a is provided with an external electrode 14 for mounting the first carrier substrate 11a on the mother substrate.

第２の半導体装置１０ｂは、第２キャリア基板１１ｂの裏面側にはランド１３ｃ、第２キャリア基板１１ｂの表面側にはランド１３ｄがそれぞれ形成されている。そして、第２キャリア基板１１ｂの上には、接着層を介し半導体素子１２ｂがフェイスアップ実装され、半導体素子１２ｂは、導電性ワイヤ１５を介してランド１３ｄにワイヤボンド接続されている。そして、第２キャリア基板１１ｂの上に実装された第２の半導体素子１２ｂは封止樹脂１６で封止されている。   In the second semiconductor device 10b, lands 13c are formed on the back surface side of the second carrier substrate 11b, and lands 13d are formed on the front surface side of the second carrier substrate 11b. The semiconductor element 12b is mounted face-up on the second carrier substrate 11b via an adhesive layer, and the semiconductor element 12b is wire-bonded to the land 13d via a conductive wire 15. The second semiconductor element 12b mounted on the second carrier substrate 11b is sealed with a sealing resin 16.

なお、第１の半導体装置１０ａの第１キャリア基板１１ａの上に、第２の半導体装置１０ｂの第２キャリア基板１１ｂを、第１キャリア基板１１ａの中心と第２キャリア基板１１ｂの中心とを揃えた状態に実装するに際しては、第２キャリア基板１１ｂのランド１３ｃに、中間電極１７が設けられている。この中間電極１７にフラックス１８を転写し、この状態で第１の半導体装置１０ａの上に第２の半導体装置１０ｂを、第１キャリア基板１１ａの中心と第２キャリア基板１１ｂの中心とを一致させて積層し、リフロー処理によって、第１の半導体装置１０ａと第２の半導体装置１０ｂとを中間電極１７を介して接続し、半導体装置１０は製造される。   The second carrier substrate 11b of the second semiconductor device 10b is aligned with the center of the first carrier substrate 11a and the center of the second carrier substrate 11b on the first carrier substrate 11a of the first semiconductor device 10a. When mounted in the above state, the intermediate electrode 17 is provided on the land 13c of the second carrier substrate 11b. The flux 18 is transferred to the intermediate electrode 17, and in this state, the second semiconductor device 10b is placed on the first semiconductor device 10a so that the center of the first carrier substrate 11a coincides with the center of the second carrier substrate 11b. The first semiconductor device 10a and the second semiconductor device 10b are connected via the intermediate electrode 17 by reflow processing, and the semiconductor device 10 is manufactured.

ここで、第２キャリア基板１１ｂのランド１３ｃと中間電極１７は図１（ｂ）に示すように配置に形成されている。つまり、第２キャリア基板１１ｂのコーナー部分Ｃを避けて中間電極１７が形成されるように中間電極１７の形成領域の外郭２１を、第２キャリア基板１１ｂの外形形状よりも辺の数が多い仮想線で示す多角形状に配列して形成されている。具体的には、中間電極１７の直径を０．４ｍｍから０．５ｍｍ、中間電極１７のピッチを０．６５ｍｍとした。   Here, the land 13c and the intermediate electrode 17 of the second carrier substrate 11b are formed in an arrangement as shown in FIG. That is, the outer shape 21 of the formation region of the intermediate electrode 17 has a larger number of sides than the outer shape of the second carrier substrate 11b so that the intermediate electrode 17 is formed so as to avoid the corner portion C of the second carrier substrate 11b. They are arranged in a polygonal shape indicated by a line. Specifically, the diameter of the intermediate electrode 17 was 0.4 mm to 0.5 mm, and the pitch of the intermediate electrode 17 was 0.65 mm.

このように構成したため、第１の半導体装置１０ａと第２の半導体装置１０ｂを接続する際の高温時（半田が溶融する摂氏２００度から摂氏２７０度）において、図１（ａ）に示すように、第１キャリア基板１１ａが下側に凸となるような反りを発生する場合であっても、上記のように、中間電極１７は、第１キャリア基板１１ａの反りの大きいコーナー部分Ｃに設けられていないため、第１の半導体装置１０ａと第２の半導体装置１０ｂとの隙間を小さくすることができ、中間電極１７は、第１キャリア基板１１ａと第２キャリア基板１１ｂとを接続することが可能となり、従来に比べて接続不良を改善できる。   With this configuration, as shown in FIG. 1A, at a high temperature when connecting the first semiconductor device 10a and the second semiconductor device 10b (from 200 degrees Celsius to 270 degrees Celsius when the solder melts). Even if the first carrier substrate 11a is warped so as to protrude downward, the intermediate electrode 17 is provided at the corner portion C where the warp of the first carrier substrate 11a is large as described above. Therefore, the gap between the first semiconductor device 10a and the second semiconductor device 10b can be reduced, and the intermediate electrode 17 can connect the first carrier substrate 11a and the second carrier substrate 11b. Thus, the connection failure can be improved as compared with the conventional case.

（実施の形態２）
図３は本発明の（実施の形態２）を示し、第２キャリア基板１１ｂのランド１３ｃと中間電極１７の配置が図１（ｂ）に示すそれとは変更されているだけで、第１の半導体装置１０ａの中心と第２の半導体装置１０ｂの中心とを一致させて実装するなど、その他については（実施の形態）と同じである。具体的には、第２キャリア基板１１ｂのコーナー部Ｃを避けて中間電極１７が形成されるように中間電極１７の形成領域の外郭２１を、第２の半導体装置１０ａの基板の外形形状よりも辺の数が多い多角形状に形成するとともに、中間電極１７の形成領域の内郭２２を、図３に示すように、第２キャリア基板１１ｂの外形形状よりも辺の数が多い仮想線で示す多角形状に配列して形成されている。 (Embodiment 2)
FIG. 3 shows (Embodiment 2) of the present invention. The arrangement of the land 13c and the intermediate electrode 17 of the second carrier substrate 11b is changed from that shown in FIG. Other than that, the center of the device 10a and the center of the second semiconductor device 10b are mounted in the same manner as in the embodiment. Specifically, the outer shape 21 of the formation region of the intermediate electrode 17 is set to be larger than the outer shape of the substrate of the second semiconductor device 10a so that the intermediate electrode 17 is formed avoiding the corner portion C of the second carrier substrate 11b. As shown in FIG. 3, the inner shape 22 of the formation region of the intermediate electrode 17 is indicated by a virtual line having a larger number of sides than the outer shape of the second carrier substrate 11b. They are arranged in a polygonal shape.

このように第２キャリア基板１１ｂのコーナー部を避けて第２キャリア基板１１ｂの裏面側に中間電極１７を形成したため、第１の半導体装置１０ａと第２の半導体装置１０ｂを接続する際の高温時において、第１キャリア基板１１ａが下側に凸となるような反りを発生する場合であっても、第１の半導体装置１０ａと第２の半導体装置１０ｂとの隙間を小さくすることができ、中間電極１７は、第１キャリア基板１１ａと第２キャリア基板１１ｂとを接続することが可能となり、従来に比べて接続不良を改善できる。   As described above, since the intermediate electrode 17 is formed on the back surface side of the second carrier substrate 11b while avoiding the corner portion of the second carrier substrate 11b, the high temperature when the first semiconductor device 10a and the second semiconductor device 10b are connected is high. In this case, the gap between the first semiconductor device 10a and the second semiconductor device 10b can be reduced even if the first carrier substrate 11a is warped so as to protrude downward. The electrode 17 can connect the first carrier substrate 11a and the second carrier substrate 11b, and can improve connection failure compared to the conventional case.

（実施の形態３）
図４（ａ）と図４（ｂ）は本発明の（実施の形態３）を示す。
この（実施の形態３）の半導体装置１０は、（実施の形態１）のように第１の半導体装置１０ａの第１キャリア基板１１ａの上に半導体素子１２ａがフリップチップ実装されているだけでなく、第１キャリア基板１１ａの裏面にも半導体素子１２ｃがフリップチップ実装されている。第２キャリア基板１１ｂのランド１３に設けられた中間電極１７の形成領域の外郭２３は、第２キャリア基板１１ｂのコーナー部分Ｃにわたって形成され、外形形状が矩形の第２キャリア基板１１ｂの４つの辺に沿った四角形状であり、中間電極１７の形成領域の内郭２４は、第２キャリア基板１１ｂの中心に対して、第２キャリア基板１１ｂの外形形状よりも辺の数が多い仮想線で示す多角形状に配列して形成されている。第１の半導体装置１０ａの中心と第２の半導体装置１０ｂの中心は一致して実装されている。 (Embodiment 3)
FIG. 4A and FIG. 4B show (Embodiment 3) of the present invention.
In the semiconductor device 10 of the (third embodiment), the semiconductor element 12a is not only flip-chip mounted on the first carrier substrate 11a of the first semiconductor device 10a as in the first embodiment. The semiconductor element 12c is also flip-chip mounted on the back surface of the first carrier substrate 11a. The outer region 23 of the formation region of the intermediate electrode 17 provided on the land 13 of the second carrier substrate 11b is formed over the corner portion C of the second carrier substrate 11b, and has four sides of the second carrier substrate 11b having a rectangular outer shape. The outline 24 of the formation region of the intermediate electrode 17 is indicated by an imaginary line having more sides than the outer shape of the second carrier substrate 11b with respect to the center of the second carrier substrate 11b. They are arranged in a polygonal shape. The center of the first semiconductor device 10a and the center of the second semiconductor device 10b are mounted in alignment.

このような場合には、図２（ａ）と図２（ｂ）の工程で第１の半導体装置１０ａの上に第２の半導体装置１０ｂを実装する際の高温時に、第１キャリア基板１１ａが上側が凸となるような反りを発生する場合であっても、第１の半導体装置１０ａと第２の半導体装置１０ｂとの隙間を小さくすることができ、中間電極１７は、第１キャリア基板１１ａと第２キャリア基板１１ｂとを接続することが可能となり、従来に比べて接続不良を改善できる。   In such a case, the first carrier substrate 11a is formed at a high temperature when the second semiconductor device 10b is mounted on the first semiconductor device 10a in the steps of FIGS. 2A and 2B. Even in the case where warpage occurs such that the upper side is convex, the gap between the first semiconductor device 10a and the second semiconductor device 10b can be reduced, and the intermediate electrode 17 serves as the first carrier substrate 11a. And the second carrier substrate 11b can be connected, and the connection failure can be improved as compared with the conventional case.

（実施の形態４）
図１（ｂ）と図３では、第２の半導体装置１０ｂの第２キャリア基板１１ｂに設けた中間電極１７の形成領域の外郭は、第２キャリア基板１１ｂの外形形状よりも辺の数が多い多角形状であったが、図５（ａ）（ｂ）に示すように構成しても同様の効果を期待できる。その他は（実施の形態１）と同じである。 (Embodiment 4)
In FIG. 1B and FIG. 3, the outer shape of the formation region of the intermediate electrode 17 provided on the second carrier substrate 11b of the second semiconductor device 10b has more sides than the outer shape of the second carrier substrate 11b. Although it has a polygonal shape, the same effect can be expected even if it is configured as shown in FIGS. Others are the same as (Embodiment 1).

図５（ａ）に示したものは、第２キャリア基板１１ｂのコーナー部分Ｃを避けて中間電極１７が形成されるように中間電極１７の形成領域の外郭２５を、第２キャリア基板１１ｂの中心２６に対して仮想線で示す同心円形状に配列して形成されている。中間電極１７の形成領域の内郭２７は、外形形状が矩形の第２キャリア基板１１ｂの４つの辺に沿った四角形状である。   In FIG. 5A, the outer region 25 of the formation region of the intermediate electrode 17 is formed in the center of the second carrier substrate 11b so that the intermediate electrode 17 is formed avoiding the corner portion C of the second carrier substrate 11b. 26 are arranged in concentric circles indicated by phantom lines. The inner contour 27 of the formation region of the intermediate electrode 17 has a quadrangular shape along the four sides of the second carrier substrate 11b having a rectangular outer shape.

図５（ｂ）に示したものは、第２キャリア基板１１ｂのコーナー部分Ｃを避けて中間電極１７が形成されるように中間電極１７の形成領域の外郭２８を、第２キャリア基板１１ｂの中心２９に対して仮想線で示す同心円形状に配列して形成されている。中間電極１７の形成領域の内郭３０も、第２キャリア基板１１ｂの中心２９に対して仮想線で示す同心円形状に配列して形成されている。   In FIG. 5B, the outer region 28 of the intermediate electrode 17 is formed in the center of the second carrier substrate 11b so that the intermediate electrode 17 is formed avoiding the corner portion C of the second carrier substrate 11b. 29 are arranged in a concentric circle shape indicated by an imaginary line. The inner contour 30 of the formation region of the intermediate electrode 17 is also formed in a concentric circle shape indicated by a virtual line with respect to the center 29 of the second carrier substrate 11b.

（実施の形態５）
図４（ｂ）では、第２の半導体装置１０ｂの第２キャリア基板１１ｂに設けた中間電極１７の形成領域の内郭２４は、第２キャリア基板１１ｂの外形形状よりも辺の数が多い多角形状であったが、図６に示すように、第２キャリア基板１１ｂに設けた中間電極１７の形成領域の内郭３２を、第２キャリア基板１１ｂの中心３１に対して仮想線で示す同心円形状に配列して形成しても同様の効果を期待できる。その他は（実施の形態１）と同じである。 (Embodiment 5)
In FIG. 4B, the inner 24 of the formation region of the intermediate electrode 17 provided on the second carrier substrate 11b of the second semiconductor device 10b is a polygon having more sides than the outer shape of the second carrier substrate 11b. As shown in FIG. 6, the inner shape 32 of the formation region of the intermediate electrode 17 provided on the second carrier substrate 11b is concentrically shown by a virtual line with respect to the center 31 of the second carrier substrate 11b. The same effect can be expected even if they are arranged in the same manner. Others are the same as (Embodiment 1).

なお、上記の各実施の形態では、中間電極１７を第２キャリア基板１１ｂに設けた場合を例に挙げて説明したが、中間電極１７を第１キャリア基板１１ａに設けて構成することもできる。具体的には、第１の半導体装置１０ａに形成した中間電極１７の形成領域の外郭を、第２の半導体装置１０ｂのコーナー部を避けて前記中間電極１７が形成されるように第２の半導体装置１０ａの基板の外形形状よりも辺の数が多い多角形状または同心円状に配列し、中間電極１７を介して、第１の半導体装置に形成されたランド１３ｂと第２の半導体装置に形成されたランド１３ｃとを接続する。さらに、第１キャリア基板１１ａに設けた中間電極１７の形成領域の内郭を、第１の半導体装置１０ａまたは第２の半導体装置１０ｂの基板の外形形状よりも辺の数が多い多角形状または同心円状に配列することもできる。   In each of the above embodiments, the case where the intermediate electrode 17 is provided on the second carrier substrate 11b has been described as an example. However, the intermediate electrode 17 may be provided on the first carrier substrate 11a. Specifically, the second semiconductor is formed so that the intermediate electrode 17 is formed so as to avoid the corner portion of the second semiconductor device 10b around the outer region of the formation region of the intermediate electrode 17 formed in the first semiconductor device 10a. Arranged in a polygonal shape or concentric shape having more sides than the outer shape of the substrate of the device 10a, and formed on the second semiconductor device and the land 13b formed on the first semiconductor device via the intermediate electrode 17. Connected to the land 13c. Furthermore, the inner shape of the formation region of the intermediate electrode 17 provided on the first carrier substrate 11a is a polygonal shape or concentric circle having more sides than the outer shape of the substrate of the first semiconductor device 10a or the second semiconductor device 10b. It can also be arranged in a shape.

また、第１の半導体装置１０ａに形成した中間電極１７の形成領域の内郭を、第２の半導体装置１０ｂの基板の外形形状よりも辺の数が多い多角形状または同心円状に配列し、中間電極１７を介して、第１の半導体装置に形成されたランド１３ｂと第２の半導体装置に形成されたランド１３ｃとを接続する。   In addition, the inner region of the formation region of the intermediate electrode 17 formed in the first semiconductor device 10a is arranged in a polygonal shape or a concentric shape having more sides than the outer shape of the substrate of the second semiconductor device 10b. Via the electrode 17, the land 13b formed in the first semiconductor device and the land 13c formed in the second semiconductor device are connected.

このように、第１の半導体装置１０ａに形成した中間電極１７を介して、第１の半導体装置に形成されたランド１３ｂと第２の半導体装置に形成されたランド１３ｃとを接続する場合にも、第１キャリア基板１１ａの中心と第２キャリア基板１１ｂの中心を一致させた状態で接続する。   As described above, even when the land 13b formed in the first semiconductor device and the land 13c formed in the second semiconductor device are connected via the intermediate electrode 17 formed in the first semiconductor device 10a. The connection is made with the center of the first carrier substrate 11a and the center of the second carrier substrate 11b aligned.

上記の各実施の形態において、キャリア基板１１ａ，１１ｂとしては、例えば、両面基板、多層配線基板、ビルドアップ基板、テープ基板またはフィルム基板などを用いることができ、キャリア基板１１ａ，１１ｂの材質としては、例えば、ポリイミド樹脂、ガラスエポキシ樹脂、ＢＴレジン、アラミドとエポキシのコンポジットまたはセラミックなどを用いることができる。外部電極１４および中間電極１７としては、例えば、Ａｕバンプ、半田材などで被覆されたＣｕバンプやＮｉバンプ、あるいは半田ボールなどを用いることができる。半田材としてはＳｎＰｂ共晶や鉛フリー半田（Ｓｎ−Ａｇ−Ｃｕ、Ｓｎ−Ａｇ−Ｂｉ−Ｉｎ、Ｓｎ−Ｚｎ−Ｂｉ）を用いても良い。導電性ワイヤ１５としては、例えば、ＡｕワイヤやＡｌワイヤなどを用いることができる。また、第２の半導体素子１２ｂを第２キャリア基板１１ｂの上に実装する場合に、ワイヤボンド接続を用いる方法について説明したが、第２キャリア基板１１ｂの上に第２の半導体素子１２ｂをフリップチップ実装するようにしてもよい。さらに、第１キャリア基板１１ａの上に第１の半導体素子１２ａを一個だけ実装する方法を例に挙げて説明したが、第１キャリア基板１１ａの上に複数の半導体素子を実装するようにしてもよい。   In each of the above-described embodiments, for example, a double-sided board, a multilayer wiring board, a build-up board, a tape board, or a film board can be used as the carrier boards 11a and 11b. For example, polyimide resin, glass epoxy resin, BT resin, aramid and epoxy composite, ceramic, or the like can be used. As the external electrode 14 and the intermediate electrode 17, for example, an Au bump, a Cu bump coated with a solder material, a Ni bump, or a solder ball can be used. As the solder material, SnPb eutectic or lead-free solder (Sn—Ag—Cu, Sn—Ag—Bi—In, Sn—Zn—Bi) may be used. As the conductive wire 15, for example, an Au wire or an Al wire can be used. Further, the method of using the wire bond connection when mounting the second semiconductor element 12b on the second carrier substrate 11b has been described. However, the second semiconductor element 12b is flip-chiped on the second carrier substrate 11b. You may make it mount. Further, the method of mounting only one first semiconductor element 12a on the first carrier substrate 11a has been described as an example. However, a plurality of semiconductor elements may be mounted on the first carrier substrate 11a. Good.

また、第１キャリア基板１１ａと第２キャリア基板１１ｂとの隙間には、必要に応じて樹脂を注入するようにしてもよい。
なお、第１キャリア基板１１ａの上に、半導体素子１２ａをフリップチップ実装する工程において、異方性導電フィルムを介してＡＣＦ接合してもよいし、ＮＣＦ接合などのその他の圧接接合を用いるようにしてもよく、半田接合や合金接合などの金属接合を用いるようにしてもよい。また、半導体素子１２ａを２層以の上に積層しても、横に並列に実装してもかまわない。 Further, a resin may be injected into the gap between the first carrier substrate 11a and the second carrier substrate 11b as necessary.
In the step of flip-chip mounting the semiconductor element 12a on the first carrier substrate 11a, ACF bonding may be performed via an anisotropic conductive film, or other pressure bonding such as NCF bonding may be used. Alternatively, metal bonding such as solder bonding or alloy bonding may be used. Further, the semiconductor elements 12a may be stacked on two or more layers or mounted side by side in parallel.

なお、第２キャリア基板１１ｂの上に半導体素子を実装する工程において、フリップ実装でもよいし、導電性ワイヤを用いて接続してもかまわない。
なお、外部電極１４を形成する工程において、第１の半導体装置１０ａと第２の半導体装置１０ｂを積層した後でもかまわない。 In the step of mounting the semiconductor element on the second carrier substrate 11b, flip mounting may be used, or connection may be made using a conductive wire.
In the step of forming the external electrode 14, the first semiconductor device 10a and the second semiconductor device 10b may be stacked.

なお、外部電極１４及び中間電極１７としては、例えば、Ａｕバンプ、半田材などで被覆されたＣｕバンプやＮｉバンプ、あるいは、半田ボールなどを用いてもかまわない。
なお、中間電極１７にフラックス１８を転写する工程において、半田ペーストを転写してもよいし、フラックス１８をランド１３ｂにピンで転写してもよい。または、マスクを用いてフラックス１８または半田ペーストを印刷してもかまわない。 As the external electrode 14 and the intermediate electrode 17, for example, an Au bump, a Cu bump covered with a solder material, a Ni bump, a solder ball, or the like may be used.
In the step of transferring the flux 18 to the intermediate electrode 17, the solder paste may be transferred, or the flux 18 may be transferred to the land 13b with pins. Alternatively, the flux 18 or solder paste may be printed using a mask.

本発明の半導体装置及びその製造方法は、高温時の基板の反りによる半導体装置間の接続不良を改善することができ、半導体装置の３次元実装構造に適用して好適である。   INDUSTRIAL APPLICABILITY The semiconductor device and the manufacturing method thereof according to the present invention can improve the connection failure between the semiconductor devices due to the warping of the substrate at a high temperature, and is suitable for application to a three-dimensional mounting structure of a semiconductor device.

本発明の（実施の形態１）における半導体装置の構成を示す断面図とＡ−Ａ線に沿う第２の半導体装置の平面図Sectional drawing which shows the structure of the semiconductor device in (Embodiment 1) of this invention, and the top view of the 2nd semiconductor device along an AA line 本同実施の形態の組み立て工程図Assembly process diagram of this embodiment 本発明の（実施の形態２）における第２の半導体装置の平面図The top view of the 2nd semiconductor device in (Embodiment 2) of this invention 本発明の（実施の形態３）における半導体装置の構成を示す断面図とＡ−Ａ線に沿う第２の半導体装置の平面図Sectional drawing which shows the structure of the semiconductor device in (Embodiment 3) of this invention, and the top view of the 2nd semiconductor device along an AA line 本発明の（実施の形態４）における第２の半導体装置の平面図The top view of the 2nd semiconductor device in (Embodiment 4) of this invention 本発明の（実施の形態５）における第２の半導体装置の平面図The top view of the 2nd semiconductor device in (Embodiment 5) of this invention 従来の半導体装置の断面図とＡ−Ａ線に沿う第２の半導体装置の平面図Sectional drawing of the conventional semiconductor device, and the top view of the 2nd semiconductor device along an AA line 一方の半導体装置が変形した場合の断面図Sectional view when one semiconductor device is deformed

符号の説明Explanation of symbols

１０ 半導体装置
１０ａ 第１の半導体装置
１０ｂ 第２の半導体装置
１１ａ 第１キャリア基板
１２ａ 半導体素子
１２ｂ 半導体素子
１２ｃ 半導体素子
１３ａ，１３ｂ，１３ｃ，１３ｄ ランド
１４ 外部電極
１５ 導電性ワイヤ
１６ 封止樹脂
１７ 中間電極
１８ フラックス
Ｃ コーナー部分
２１ 中間電極１７の形成領域の外郭
２２ 中間電極１７の形成領域の内郭
２３ 中間電極１７の形成領域の外郭
２４ 中間電極１７の形成領域の内郭
２５ 中間電極１７の形成領域の外郭
２６ 第２キャリア基板１１ｂの中心
２７ 中間電極１７の形成領域の内郭
２８ 中間電極１７の形成領域の外郭
２９ 第２キャリア基板１１ｂの中心
３０ 中間電極１７の形成領域の内郭
３２ 中間電極１７の形成領域の内郭
３１ 第２キャリア基板１１ｂの中心 10 Semiconductor device 10a First semiconductor device 10b Second semiconductor device 11a First carrier substrate 12a Semiconductor element 12b Semiconductor element 12c Semiconductor elements 13a, 13b, 13c, 13d Land 14 External electrode 15 Conductive wire 16 Sealing resin 17 Intermediate Electrode 18 Flux C Corner portion 21 Outline 22 of formation area of intermediate electrode 17 Outline 23 of formation area of intermediate electrode 17 Outline 24 of formation area of intermediate electrode 17 Formation 25 of outline of formation area of intermediate electrode 17 Formation of intermediate electrode 17 Outer part of region 26 Center 27 of second carrier substrate 11b Inner part 28 of formation region of intermediate electrode 17 Outer part of formation region of intermediate electrode 17 Center 30 of second carrier substrate 11b Inner part 32 of formation region of intermediate electrode 17 Intermediate Inner 31 of formation area of electrode 17 Center of second carrier substrate 11b

Claims (16)

第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、
第２の半導体装置のコーナー部を避けて前記中間電極が形成されるように前記中間電極の形成領域の外郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に形成した
半導体装置。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode A device,
The outer surface of the intermediate electrode forming region is formed in a polygonal shape having more sides than the outer shape of the substrate of the second semiconductor device so that the intermediate electrode is formed so as to avoid the corner portion of the second semiconductor device. The formed semiconductor device. 前記中間電極の形成領域の内郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に形成した
請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein an inner region of the formation region of the intermediate electrode is formed in a polygonal shape having more sides than the outer shape of the substrate of the second semiconductor device. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、
前記中間電極の形成領域の内郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に形成した
半導体装置。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode A device,
A semiconductor device in which an inner electrode forming region is formed in a polygonal shape having more sides than the outer shape of the substrate of the second semiconductor device. 第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心が、一致していることを特徴とする
請求項１〜請求項３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein a center of the substrate of the first semiconductor device is coincident with a center of the substrate of the second semiconductor device. 5. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、
第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の外郭を、第２の半導体装置のコーナー部を避けて前記中間電極が形成されるように第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に配列し、
前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続する
半導体装置の製造方法。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode In forming the device,
The substrate of the second semiconductor device is formed so that the intermediate electrode is formed so as to avoid the corner portion of the second semiconductor device around the outer region of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device. Arranged in a polygonal shape with more sides than the outer shape of
A method of manufacturing a semiconductor device, wherein a land formed in a first semiconductor device and a land formed in a second semiconductor device are connected via the intermediate electrode. 前記中間電極の形成領域の内郭を、
第１の半導体装置または第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に配列する
請求項５記載の半導体装置の製造方法。 The inner area of the intermediate electrode formation region is
6. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is arranged in a polygonal shape having more sides than the outer shape of the substrate of the first semiconductor device or the second semiconductor device. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、
第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の内郭を、第２の半導体装置の基板の外形形状よりも辺の数が多い多角形状に配列し、
前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続する
半導体装置の製造方法。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode In forming the device,
The inner contour of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is arranged in a polygonal shape having more sides than the outer shape of the substrate of the second semiconductor device,
A method of manufacturing a semiconductor device, wherein a land formed in a first semiconductor device and a land formed in a second semiconductor device are connected via the intermediate electrode. 第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心を一致させた状態で、前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続する
請求項５〜請求項７のいずれかに記載の半導体装置の製造方法。 A land and a second semiconductor formed in the first semiconductor device through the intermediate electrode in a state where the center of the substrate of the first semiconductor device and the center of the substrate of the second semiconductor device are aligned. The method for manufacturing a semiconductor device according to claim 5, wherein a land formed on the device is connected. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、
前記中間電極の形成領域の外郭を、第２の半導体装置の基板の中心に対して同心円状に配列し、かつ第２の半導体装置のコーナー部を避けて前記中間電極を配列した
半導体装置。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode A device,
A semiconductor device in which an outer region of the formation region of the intermediate electrode is arranged concentrically with respect to the center of the substrate of the second semiconductor device, and the intermediate electrode is arranged avoiding a corner portion of the second semiconductor device. 前記中間電極の形成領域の内郭を、第２の半導体装置の基板の中心に対して同心円状となるように形成した
請求項９に記載の半導体装置。 The semiconductor device according to claim 9, wherein an inner region of the intermediate electrode formation region is formed to be concentric with respect to a center of a substrate of the second semiconductor device. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置であって、
前記中間電極の形成領域の内郭を、第２の半導体装置の基板の中心に対して同心円状に配列した
半導体装置。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode A device,
A semiconductor device in which the outline of the formation region of the intermediate electrode is arranged concentrically with respect to the center of the substrate of the second semiconductor device. 第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心が、一致していることを特徴とする
請求項９〜請求項１１のいずれかに記載の半導体装置。 The semiconductor device according to claim 9, wherein a center of the substrate of the first semiconductor device and a center of the substrate of the second semiconductor device are coincident with each other. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、
第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の外郭を、第２の半導体装置のコーナー部を避けて前記中間電極が形成されるように同心円状に配列し、
中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続する
半導体装置の製造方法。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode In forming the device,
An outline of a formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is arranged concentrically so that the intermediate electrode is formed so as to avoid the corner portion of the second semiconductor device,
A method for manufacturing a semiconductor device, wherein a land formed in a first semiconductor device and a land formed in a second semiconductor device are connected via an intermediate electrode. 前記中間電極の形成領域の内郭を、第１の半導体装置または第２の半導体装置の基板の中心に対して同心円状となるように形成する
請求項１３記載の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 13, wherein the inner electrode forming region is formed so as to be concentric with the center of the substrate of the first semiconductor device or the second semiconductor device. 第１の半導体装置の上に第２の半導体装置を積層し、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとの間に中間電極を介して接続した半導体装置を形成するに際し、
第１の半導体装置または第２の半導体装置に形成した中間電極の形成領域の内郭を、第２の半導体装置の基板の中心に対して同心円状に配列し、前記中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続する
半導体装置の製造方法。 A semiconductor device in which a second semiconductor device is stacked on a first semiconductor device, and a land formed on the first semiconductor device and a land formed on the second semiconductor device are connected via an intermediate electrode In forming the device,
The outline of the formation region of the intermediate electrode formed in the first semiconductor device or the second semiconductor device is concentrically arranged with respect to the center of the substrate of the second semiconductor device, and the intermediate electrode is interposed through the intermediate electrode. A method for manufacturing a semiconductor device, comprising connecting a land formed in one semiconductor device and a land formed in a second semiconductor device. 第１の半導体装置の前記基板の中心と第２の半導体装置の前記基板の中心を一致させた状態で、中間電極を介して、第１の半導体装置に形成されたランドと第２の半導体装置に形成されたランドとを接続する
請求項１３〜請求項１５のいずれかに記載の半導体装置の製造方法。 A land formed on the first semiconductor device and the second semiconductor device via an intermediate electrode in a state where the center of the substrate of the first semiconductor device is aligned with the center of the substrate of the second semiconductor device The method for manufacturing a semiconductor device according to claim 13, wherein the land formed on the semiconductor device is connected to the land.
JP2005333466A 2005-11-18 2005-11-18 Semiconductor device, and method of manufacturing same Pending JP2007142124A (en)

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