JP5128180B2 - Chip built-in substrate - Google Patents

Description

  The present invention relates to a chip built-in substrate, and more particularly to a chip built-in substrate in which a chip is built between a pair of substrates on which wiring is formed.

  Currently, the performance of electronic equipment using a semiconductor device in which a semiconductor chip is embedded is being improved, and the density of the semiconductor chip mounted on the substrate is increased, and the size of the substrate on which the semiconductor chip is mounted is reduced. There is a need for space saving. For this reason, a substrate in which a chip component such as a semiconductor chip is embedded, a so-called chip-embedded wiring substrate (hereinafter referred to as a chip-embedded substrate) has been proposed, and various structures for incorporating the chip component in the substrate have been proposed. Has been.

An example of this chip-embedded substrate is disclosed in Patent Document 1, for example. In the chip built-in substrate disclosed in Patent Document 1, bumps functioning as chip components and spacers are disposed on a first substrate. Further, a sealing resin is disposed on the first substrate so as to seal the chip and the bump. The second substrate is disposed on the first substrate so as to be electrically connected to the bumps, whereby the chip is built between the first and second substrates.
JP 2003-347722 A

  However, since the conventional chip-embedded substrate has a configuration in which the chip component is embedded between the flat first substrate and the second substrate, the chip component inevitably becomes the upper surface of the first substrate (the chip is mounted). And the lower surface of the second substrate (the surface facing the first substrate).

  For this reason, the separation distance between the first substrate and the second substrate is determined by the thickness of the chip component, and when a thick chip component is used, the separation distance between the first substrate and the second substrate. As a result, the problem arises that the chip-embedded substrate becomes larger.

  In addition, the conventional chip-embedded substrate has a first substrate and a second substrate formed so as to face the upper and lower surfaces of the semiconductor chip. Further, the upper and lower surfaces are arranged between the first substrate and the second substrate. Since a connecting member for electrical connection between the substrates is provided, there is a problem that it is difficult to secure a built-in space for electronic components other than the semiconductor chip and to improve the mounting density by stacking the chips.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a chip-embedded substrate capable of improving the mounting density while reducing the thickness.

According to one aspect of the present invention, the above problem is
A first semiconductor chip ;
A first substrate on which the first wiring is formed and the first semiconductor chip is mounted;
A second substrate on which a second wiring is formed and stacked on the first substrate;
A connection member that electrically connects the first substrate and the second substrate; and a sealing resin disposed between the first substrate and the second substrate;
A chip-embedded substrate in which an opening is formed in the second substrate,
The first of the second semiconductor chip larger shape than the first semiconductor chip to a substrate by flip-chip bonding, at least a portion the of the second semiconductor chip and at least part of the first semiconductor chip The second semiconductor chip is located in the opening and the upper part of the first semiconductor chip is configured,
The sealing resin is filled between the first semiconductor chip and the second semiconductor chip , between the second semiconductor chip and the second substrate, and in the opening ,
This can be solved by a chip built-in substrate configured such that the back surface of the second semiconductor chip in the opening and the surface of the second substrate are flush with each other.

  According to the present invention, an opening is formed in the second substrate, and when the second substrate is stacked on the first substrate, at least a part of the chip component is positioned in the opening. The distance between the first substrate and the second substrate need not be greater than the thickness of the chip component, so that the chip-embedded substrate can be made thinner and smaller. In addition, it is possible to mount a built-in component other than the chip component in the opening, so that the chip-embedded substrate can be increased in density and multifunction.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings.

  For convenience of explanation, a reference example which is a premise of the present invention will be described prior to description of the chip-embedded substrate according to the present invention. FIG. 1 shows a chip built-in substrate 300A according to a reference example as a premise of the present invention. In the following description, the side indicated by the arrow Z1 in FIG. 1 is the upper side, and the side indicated by the arrow Z2 is the lower side. The same applies to each figure after FIG.

  The chip built-in substrate 300A is roughly composed of the first substrate 100, the second substrate 200, the semiconductor chip 110A (corresponding to the chip component described in the claims), the electrode 112, the sealing resin 115, and the like. .

  The first substrate 100 includes a core substrate 101, build-up layers 101A and 101B, wiring patterns 103A and 103B, inner layer wiring 103C, solder resist layers 104A and 104B, and the like.

  The core substrate 101 is made of a prepreg material (a material in which a glass fiber is impregnated with an epoxy resin or the like), and inner layer wiring 103C made of Cu, for example, is formed on both surfaces thereof. Further, the inner layer wirings 103 </ b> C formed on both surfaces of the core substrate 101 are electrically connected by via plugs 102 formed through the core substrate 101.

  A buildup layer 101A is formed on the upper surface of the core substrate 101 in the figure, and a buildup layer 101B is formed on the lower surface. A wiring pattern 103A made of Cu, for example, is formed on the upper surface of the buildup layer 101A, and a wiring pattern 103B made of Cu, for example, is formed on the lower surface of the buildup layer 101B. The wiring pattern 103A is connected to the inner layer wiring 103C through the interlayer via 105A, and the wiring pattern 103B is connected to the inner layer wiring 103C through the interlayer via 105B.

  A solder resist layer 104A is formed on the upper surface of the buildup layer 101A in the figure. The solder resist layer 104A is formed with a connection hole 117A (see FIG. 3D) by removing a bonding position between a semiconductor chip 110A and an electrode 112, which will be described later. The wiring pattern 103A is exposed from the connection hole 117A.

  Further, a solder resist layer 104B is formed on the lower surface of the buildup layer 101B in the drawing. In the solder resist layer 104B, a connection hole 117B is formed at a position where a solder ball 111 described later is connected. The wiring pattern 103B is exposed from the connection hole 117B.

  Of the wiring patterns 103A and 103B exposed from the connection holes 117A and 117B, at a position where an electrode 112 or a solder ball 111, which will be described later, is soldered, for example, Ni / Au (on the wiring pattern 103A) to improve solderability. Further, a connection layer made up of a Ni layer and an Au layer in this order) may be formed (the connection layer is not shown). Further, in the wiring patterns 103A and 103B exposed from the connection holes 117A and 117B, the connection layer 107 made of, for example, solder is formed by a printing method, an electrolytic plating method, or the like at a position where the semiconductor chip 110A is flip-chip bonded. ing.

  The semiconductor chip 110A is mounted on the first substrate 100 by flip chip bonding. The semiconductor chip 110A has bumps 108 formed on its main surface. Then, by bonding the bumps 108 to the connection layer 107, the semiconductor chip 110A is bonded to the first substrate 100 face down. In addition, an underfill 109 is disposed between the semiconductor chip 110A and the upper surface 100a of the first substrate 100 in order to improve bonding reliability.

  In this reference example, the semiconductor chip 110A is used as the chip component. However, the chip component is not limited to the semiconductor chip, and other chip components (for example, a semiconductor chip, a capacitor, a resistor, an inductor) Etc.) can also be used in combination.

  The solder ball 111 functions as an external connection terminal, and is disposed on the lower surface 100 b of the first substrate 100. Specifically, as described above, the solder resist layer 104B has the connection hole 117B in which the wiring pattern 103B is exposed, and the solder ball 111 is joined to the wiring pattern 103B exposed from the connection hole 117B.

  On the other hand, the second substrate 200 includes a core substrate 201, wiring patterns 203A and 203B, solder resist layers 204A and 204B, and the like.

  Similar to the core substrate 101 of the first substrate 100 described above, the core substrate 201 is made of a prepreg material, and wiring patterns 203A and 203B made of Cu, for example, are formed on the upper and lower surfaces thereof. The wiring patterns 203A and 203B are electrically connected by a via plug 202 formed through the core substrate 201.

  In addition, a solder resist layer 204A is formed on the upper surface of the core substrate 201 on which the wiring patterns 203A and 203B are formed, and a solder resist layer 204B is formed on the lower surface. In the solder resist layer 204B located on the lower side, a connection hole 116B (see FIG. 3A) is formed at a bonding position of an electrode 112 described later. The wiring pattern 203B is exposed from the connection hole 116B. The connection hole 116A formed in the upper solder resist layer 204A is provided for mounting surface-mounted components and chip components, and for stacking (stacking) a plurality of chip-embedded substrates 300A. In the case where the lamination is not performed, it is not necessarily provided.

  The first substrate 100 and the second substrate 200 configured as described above are bonded together by a sealing connection layer. This sealing connection layer is composed of the electrode 112 and the sealing resin 115.

  The electrode 112 has a configuration in which a solder coating 114 is formed on the surface of a spherical copper core 113. The lower portion of the electrode 112 is soldered to the wiring pattern 103A exposed from the connection hole 117A of the first substrate 100, and the upper portion thereof is bonded to the wiring pattern 203B exposed from the connection hole 116B of the second substrate 200. .

  As a result, the wiring pattern 103 </ b> A of the first substrate 100 and the wiring pattern 203 </ b> B of the second substrate 200 are electrically and mechanically joined via the electrode 112. The copper core 113 functions as a spacer that keeps the distance between the first substrate 100 and the second substrate 200 constant.

  The sealing resin 115 is formed in a space between the first substrate 100 and the second substrate 200 and in an opening 206 formed in the second substrate 200 described later. Since the sealing resin 115 also functions as an adhesive, the first substrate 100 and the second substrate 200 are firmly bonded by the sealing resin 115.

  As described above, since the chip-embedded substrate 300A joins the first substrate 100 and the second substrate 200 by the sealing resin 115 in addition to the joining by the electrode 112, the chip-embedded substrate 300A. Even if the thickness is reduced, the first substrate 100 and the second substrate 200 are not peeled off, and high reliability can be realized.

  Next, the opening 206 will be described. The opening 206 is formed in the second substrate 200. The opening 206 is formed so as to penetrate the second substrate 200, and the formation position thereof is set to correspond to the mounting position of the semiconductor chip 110A.

  The shape of the opening 206 is set larger than the shape of the semiconductor chip 110A. Specifically, the area of the opening 206 in plan view is set larger than the area of the semiconductor chip 110A. Then, the semiconductor chip 110 </ b> A is configured to be positioned inside the opening 206 in a state where the second substrate 200 is bonded to the first substrate 100 (hereinafter referred to as a bonded state).

  In the bonded state, the inside of the opening 206 is filled with the sealing resin 115, so that the semiconductor chip 110 </ b> A is sealed in the opening 206 with the sealing resin 115. As a result, the semiconductor chip 110 </ b> A is embedded between the first substrate 100 and the second substrate 200. Even if the opening 206 is formed in the second substrate 200, the semiconductor chip 110 </ b> A is reliably protected by the sealing resin 115 filled in the opening 206.

  In addition, the upper surface of the sealing resin 115 filled in the opening 206 is configured to be flush with the upper surface 200 a of the second substrate 200. As described above, by making the upper surface of the sealing resin 115 flush with the upper surface 200a of the second substrate 200, the handling property when the chip-embedded substrate 300A is mounted on a mounting substrate or the like (not shown) is improved. It is possible to improve the mounting efficiency. Specifically, the chip built-in substrate 300A can be transported (handled) by sucking the upper surface of the chip built-in substrate 300A using a collet or the like.

  Here, the separation distance between the first substrate 100 and the second substrate 200, specifically, the separation distance between the upper surface 100a of the first substrate 100 and the lower surface 200b of the second substrate 200 (in the drawing, an arrow H1 And the height of the semiconductor chip 110A from the upper surface 100a of the first substrate 100 (indicated by an arrow H2 in the figure) will be described below.

  In the chip-embedded substrate 300A according to this reference example, the opening 206 is formed in the second substrate 200, the semiconductor chip 110A is inserted into the opening 206, and at least a part of the semiconductor chip 110A is located in the opening 206. It is configured to Thus, the chip-embedded substrate 300A according to the present reference example has a height H2 of the semiconductor chip 110A from the first substrate 100 larger than the separation distance H1 between the first substrate 100 and the second substrate 200. (H2> H1).

  In the conventional chip-embedded substrate in which the opening 206 is not provided, the separation distance H1 between the first substrate and the second substrate is necessarily larger than the height H2 of the semiconductor chip from the first substrate. Had to (H1> H2 had to be met). For this reason, as described above, the conventional chip-embedded substrate is increased in size.

  On the other hand, the chip-embedded substrate 300A according to the present reference example is configured so that at least a part of the semiconductor chip 110A is positioned in the opening 206 as described above. Z2 direction), the semiconductor chip 110A and the second substrate 200 can be overlapped by the dimension indicated by the arrow ΔH in the drawing. Therefore, compared with the conventional configuration, the chip built-in substrate 300A can be reduced in thickness and size by the overlapping amount ΔH.

  FIG. 2 shows a chip built-in substrate 300B which is a modification of the chip built-in substrate 300A shown in FIG. In FIG. 2, the same reference numerals are given to the components corresponding to those shown in FIG. 1, and the description thereof will be omitted.

  In the chip-embedded substrate 300A according to the present reference example, the height H1 of the built-in semiconductor chip 110A from the first substrate 100 is relatively small. In contrast, the semiconductor chip 110B incorporated in the chip-embedded substrate 300B according to this modification has a height (indicated by an arrow H3) that is higher than that of the semiconductor chip 110A of this reference example (H3> H2). It is an example used.

  Since the chip-embedded substrate 300B according to this modification has a high height H3 of the semiconductor chip 110B, the back surface 127 of the semiconductor chip 110B (an opposite side surface to the main surface of the semiconductor chip 110B) is selected by appropriately selecting the diameter of the electrode 112. Is configured to be flush with the upper surface 200 a of the second substrate 200.

  With this configuration, the back surface 127 of the semiconductor chip 110B is exposed to the outside, so that heat generated in the semiconductor chip 110B can be efficiently radiated. Further, since the back surface 127 of the semiconductor chip 110B and the upper surface 200a of the second substrate 200 are flush with each other, the handling property when the chip-embedded substrate 300B is mounted on a mounting substrate or the like as described above can be improved.

  Next, a manufacturing method of the chip built-in substrate 300A shown in FIG. 1 will be described.

  3 to 5 are diagrams showing a manufacturing method of the chip-embedded substrate 300A along the manufacturing procedure. 3 to 5, the same reference numerals are given to the components corresponding to those shown in FIG. 1, and the description thereof is partially omitted.

  In order to manufacture the chip built-in substrate 300A, first, the second substrate 200 shown in FIG. 3A is manufactured. In order to manufacture the second substrate 200, via plugs 202 penetrating the core substrate 201 are formed on the core substrate 201 made of, for example, a prepreg material.

  A wiring pattern 203A is formed on the upper surface of the core substrate 201 (the surface opposite to the surface facing the semiconductor chip), and a wiring pattern 203B is formed on the lower surface of the core substrate 201 (the surface facing the semiconductor chip). . Further, the wiring pattern 203 </ b> A and the wiring pattern 203 </ b> B formed on each surface of the core substrate 201 are electrically connected by the via plug 202. The wiring patterns 203A and 203B and the via plug 202 can be formed of Cu, for example.

  Also, a solder resist layer 204A having a connection hole 116A at a predetermined position is formed on the upper surface of the core substrate 201. A connection layer made of Ni / Au or the like may be formed on the wiring pattern 203A exposed from the connection hole 116A of the solder resist layer 204A.

  Similarly, a solder resist layer 204B having connection holes 116B at predetermined positions is formed on the lower surface of the core substrate 201. A connection layer made of, for example, Ni / Au may be formed on the wiring pattern 203B exposed from the connection hole 116B of the solder resist layer 204B.

  When the second substrate 200 shown in FIG. 3A is manufactured, an opening 206 is subsequently formed in the second substrate 200. As a method for forming the opening 206, for example, router processing can be used. As described above, the opening 206 is formed in a shape that allows the semiconductor chip 110A to be inserted therein. This router processing is known as drilling processing, and therefore the opening 206 can be easily formed. FIG. 3B illustrates the second substrate 200 in which the opening 206 is formed.

  When the formation process of the opening 206 is completed, the electrode 112 is subsequently bonded to the second substrate 200. The electrode 112 is configured such that the solder coating 114 is provided on the outer periphery of the spherical copper core 113 as described above.

  In order to bond the electrode 112 to the second substrate 200, a flux is applied to the electrode 112, and then the electrode 112 is temporarily fixed to the wiring pattern 203B exposed from the connection hole 116B. Subsequently, the electrode 112 is soldered to the wiring pattern 203B by performing a reflow process on the second substrate 200 on which the electrode 112 is temporarily fixed. When this soldering process is completed, flux cleaning is performed to remove the flux residue. FIG. 3C shows the second substrate 200 to which the electrode 112 is soldered.

  On the other hand, in order to manufacture the chip built-in substrate 300A, the first substrate 100 shown in FIG. 3D is manufactured. In order to manufacture the chip built-in substrate 300A, for example, a core substrate 101 made of a prepreg material is prepared, via plugs 102 penetrating the core substrate 101 are formed, and inner layer wiring 103C is formed on the upper and lower surfaces of the core substrate 101. Form. Inner layer wirings 103 </ b> C formed on the upper and lower surfaces of the core substrate 101 are electrically connected by via plugs 102. The via plug 102 and the inner layer wiring 103C can be formed of Cu, for example.

  Subsequently, the buildup layer 101A is formed on the upper surface of the core substrate 101 on which the inner layer wiring 103C is formed, and the buildup layer 101B is further formed on the lower surface of the core substrate 101. As the build-up layers 101A and 101B, for example, an insulating film made of an epoxy resin, a polyimide resin, or the like can be used.

  Next, a wiring pattern 103A is formed on the upper surface of the buildup layer 101A. The wiring pattern 103A and the inner layer wiring 103C are electrically connected by an interlayer via 105A formed through the build-up layer 101A. A wiring pattern 103B is formed on the lower surface of the buildup layer 101A. The wiring pattern 103B and the inner layer wiring 103C are electrically connected by an interlayer via 105B formed through the buildup layer 101B.

  Subsequently, a solder resist layer 104A is formed on the upper surface of the buildup layer 101A on which the wiring pattern 103A is formed. When the solder resist layer 104A is formed, a connection hole 117A is formed at a position where a semiconductor chip 110A described later is bonded and a position where the electrode 112 is bonded. Further, a connection layer made of, for example, Ni / Au may be formed on the wiring pattern 103A exposed from the connection hole 117A.

  In addition, among the plurality of connection holes 117A, the connection layer 107 made of, for example, solder is applied to the wiring pattern 103A exposed from the connection holes 117A to which the semiconductor chip 110A is bonded in a later step, by a printing method or an electrolytic plating method. Etc. are formed.

  On the other hand, a solder resist layer 104B is formed on the lower surface of the buildup layer 101B on which the wiring pattern 103B is formed. When the solder resist layer 104B is formed, a connection hole 117B is formed at a position where a solder ball 111 described later is joined. Further, a connection layer made of, for example, Ni / Au may be formed on the wiring pattern 103B exposed from the connection hole 117B.

  Subsequently, the semiconductor chip 110A is mounted on the first substrate 100 manufactured as described above. In order to mount the semiconductor chip 110A on the first substrate 100, bumps 108 are provided in advance on the main surface of the semiconductor chip 110A, the semiconductor chip 110A is face down, and the bumps 108 formed on the main surface are connected to the connection layer. Join to 107.

  When the semiconductor chip 110A is flip-chip bonded to the first substrate 100, the underfill 109 is subsequently filled between the semiconductor chip 110A and the first substrate 100 (upper surface 100a). As a result, the semiconductor chip 110A is bonded to the first substrate 100 with high reliability. FIG. 3E shows a state where the semiconductor chip 110 </ b> A is flip-chip bonded to the first substrate 100.

  In addition, the manufacturing process with respect to the 2nd board | substrate 200 demonstrated using above-mentioned FIG. 3 (A)-(C), and the manufacturing process with respect to the 1st board | substrate 100 demonstrated using FIG. 3 (D), (E). Any of these may be performed first or in parallel.

  When the first substrate 100 and the second substrate 200 are manufactured as described above, a step of subsequently bonding the second substrate 200 to the first substrate 100 is performed.

  In order to join the second substrate 200 to the first substrate 100, first, the flux 118 is applied to the electrode 112, and the opening 206 and the semiconductor chip 110 </ b> A are opposed to each other. The second substrate 200 is positioned above the first substrate 100 so as to face each other. FIG. 4A shows a state in which this positioning has been performed.

  Subsequently, the second substrate 200 is brought into contact with the first substrate 100. As a result, the electrode 112 is temporarily fixed to the wiring pattern 103A using the flux 118. At the same time, the semiconductor chip 110 </ b> A is in a state where at least a part thereof is located inside the opening 206.

  As described above, when the second substrate 200 is temporarily fixed to the first substrate 100, the first and second substrates 100 and 200 are mounted in the reflow furnace while maintaining the temporarily fixed state. A heating step is performed. As a result, the solder coating 114 of the electrode 112 is melted and soldered to the wiring pattern 103A, and the first substrate 100 and the second substrate 200 are joined and stacked by the electrode 112. FIG. 4B shows a state in which the first substrate 100 and the second substrate 200 are joined by the electrode 112.

  Subsequently, a cleaning process for removing the flux residue remaining at the soldering position of the electrode 112 is performed. FIG. 4C shows a state where the cleaning process is performed and the flux residue is removed.

  Subsequently, the first and second substrates 100 and 200 that have completed the cleaning process are mounted in a mold (not shown), and a transfer molding process for molding the sealing resin 115 is performed. In the case of injecting the sealing resin 115 into the mold at the time of molding, in this reference example, the resin is injected by sucking the mold so that the inside of the mold is negative. As a result, the sealing resin 115 can be reliably filled even in a portion where the distance between the first substrate 100 and the second substrate 200 is small.

  In addition, since the sealing resin 115 is filled in the opening 206 when the resin is filled, the semiconductor chip 110 </ b> A located in the opening 206 is sealed with the sealing resin 115. Therefore, the semiconductor chip 110 </ b> A is reliably protected by the sealing resin 115 even when the opening 206 is provided in the second substrate 200. When the transfer molding of the sealing resin 115 is completed, the first and second substrates 100 and 200 on which the sealing resin 115 is formed are taken out from the mold. FIG. 5A shows the first and second substrates 100 and 200 on which the sealing resin 115 is formed.

  After forming the sealing resin 115 as described above, the chip built-in substrate 300A shown in FIG. 5B is manufactured by separating into individual pieces and removing unnecessary portions. In the individualization process, as shown in FIG. 5A, in this reference example, the second substrate 200 is a single substrate, and the first substrate 100 is a substrate that performs so-called multi-cavity.

  Therefore, FIG. 5A illustrates a state in which only one second substrate 200 is bonded to the upper portion of the first substrate 100 for the sake of convenience of illustration, but the upper portion of the first substrate 100 is actually illustrated. A plurality of second substrates 200 are bonded to each other, and a process for cutting the substrates is performed for each individual chip-embedded substrate 300A. However, the configuration relating to the separation of each of the substrates 100 and 200 is not limited to this reference example, and the first substrate 100 located on the upper side is used as a multi-piece substrate, and the second located on the lower side. The substrate 200 may be an individualized substrate, and both the substrates 100 and 200 positioned above and below may be used as a substrate for picking a large number.

  When the singulation process is completed, the solder balls 111 are soldered to the wiring patterns 103B exposed from the connection holes 117B formed in the solder resist layer 104B as necessary, whereby the chip built-in substrate 300A shown in FIG. Is manufactured.

  As described above, according to the manufacturing method according to this reference example, the chip-embedded substrate 300A that can be thinned can be manufactured easily and efficiently. In addition, the process of forming the opening 206 in the second substrate 200 can be performed by using a general-purpose machining (router processing), and thus can be manufactured in a short time with high productivity.

  Further, in the process of filling the sealing resin 115, the flow resistance of the sealing resin 115 is reduced at the position where the opening 206 is formed, so that the filling property of the sealing resin 115 is improved and the generation of voids is suppressed. You can also.

  Next, the chip built-in substrate according to the first embodiment of the present invention will be described.

  FIG. 6 shows a chip built-in substrate 300C according to the first embodiment. In FIG. 6, the components corresponding to the chip-embedded substrate 300A according to the reference example shown in FIG.

  The chip-embedded substrate 300A according to the reference example described above is configured such that one semiconductor chip 110A is positioned inside the opening 206. On the other hand, the chip-embedded substrate 300C according to the present embodiment is characterized in that it is mounted so that other built-in components are located in the opening 206 in addition to the first semiconductor chip 120A. In particular, the present embodiment shows an example in which the second semiconductor chip 120B is mounted as another built-in component.

  As shown in FIG. 6, in the chip-embedded substrate 300C according to the present embodiment, the first semiconductor chip 120A is relatively thin. Accordingly, in the case where the thin first semiconductor chip 120A is mounted on the first substrate 100 as described above, when the opening 206 is formed in the second substrate 200, a wide space is formed in the opening 206. In this embodiment, the second semiconductor chip 120B (built-in component) other than the first semiconductor chip 120A is mounted in the space formed in the opening 206 in this way. Is.

  The second semiconductor chip 120B is larger in shape than the first semiconductor chip 120A, and the difference in shape is such that the second semiconductor chip 120B can be positioned above the first semiconductor chip 120A. . The second semiconductor chip 120B is flip-chip bonded to the wiring pattern 103A of the first substrate 100 using solder balls 121. Therefore, the second semiconductor chip 120B is configured to be disposed in the opening 206 in a state of straddling the first semiconductor chip 120A.

  As described above, the chip-embedded substrate 300C according to the present embodiment has a configuration in which the plurality of semiconductor chips 120A and 120B are positioned in the opening 206. Therefore, in the chip-embedded substrate 300C that can be made thinner, Densification can be achieved.

  Furthermore, in this embodiment, the diameters of the solder balls 121 and the electrodes 112 are set so that the back surface of the second semiconductor chip 120B is flush with the top surface 200a of the second substrate 200. Thereby, also in the chip built-in substrate 300 </ b> C according to the present embodiment, the handling property at the time of mounting is improved.

  Next, a manufacturing method of the chip built-in substrate 300C shown in FIG. 6 will be described.

  7 and 8 are diagrams showing a manufacturing method of the chip-embedded substrate 300C in accordance with the manufacturing procedure. 7 and 8, the same reference numerals are given to the components corresponding to those shown in FIGS. 1 to 6, and the description thereof is partially omitted.

  In the manufacturing process of the chip-embedded substrate 300C, the manufacturing method of the second substrate 200 shown in FIGS. 3A to 3C is similarly performed in the manufacturing process of the chip-embedded substrate 300C. Therefore, the description of the manufacturing method of the second substrate 200 is omitted, and the process of mounting the first and second semiconductor chips 120A and 120B on the first substrate 100 will be described.

  FIG. 7A shows the first substrate 100 before the semiconductor chips 120A and 120B are mounted. The first substrate 100 shown in the figure is the same as the first substrate shown in FIG. 3D except that a connection hole 117A for mounting the second semiconductor chip 120B is formed in the solder resist layer 104A. The configuration is the same as that of the substrate 100.

  The first semiconductor chip 120A is first mounted on the first substrate 100. In order to mount the first semiconductor chip 120A on the first substrate 100, bumps 108 are provided in advance on the main surface of the first semiconductor chip 120A, and the first semiconductor chip 120A is face-down. The bumps 108 formed on the connecting layer 107 are bonded to the connection layer 107.

  When the first semiconductor chip 120A is flip-chip bonded to the first substrate 100, the underfill 109 is filled between the first semiconductor chip 120A and the first substrate 100. Thereby, the first semiconductor chip 120A is bonded to the first substrate 100 with high reliability. FIG. 7B shows a state where the first semiconductor chip 120 </ b> A is flip-chip bonded to the first substrate 100.

  When the first semiconductor chip 120A is mounted on the first substrate 100, a process of mounting the second semiconductor chip 120B on the first substrate 100 is subsequently performed. The second semiconductor chip 120B has solder balls 121 formed in advance on its main surface. In order to mount the second semiconductor chip 120 </ b> B on the first substrate 100, a flux 119 is applied to the solder balls 121. FIG. 7C shows a state in which the flux 119 is applied to the solder balls 121 of the second semiconductor chip 120B.

  Subsequently, the second semiconductor chip 120B is positioned with respect to the first substrate 100 so that the solder balls 121 face the soldering position on the first substrate 100 (position where the predetermined connection hole 117A is formed). . Subsequently, the second semiconductor chip 120B is brought into contact with the first substrate 100. As a result, the solder balls 121 are temporarily fixed by the flux 119 to the wiring pattern 103A exposed from the connection holes 117A.

  As described above, when the second semiconductor chip 120B is temporarily fixed to the first substrate 100, the first substrate 100 is mounted in a reflow furnace to perform a heating process. As a result, the solder balls 121 are soldered to the wiring pattern 103 </ b> A, so that the second semiconductor chip 120 </ b> B is bonded to the first substrate 100. FIG. 7D illustrates a state in which the second semiconductor chip 120B is bonded to the first substrate 100.

  Subsequently, a cleaning process for removing the flux residue remaining at the soldering position of the solder ball 121 is performed. FIG. 8A shows a state where the cleaning process is performed and the flux residue is removed.

  As described above, when the first and second semiconductor chips 120A and 120B are mounted on the first substrate 100, a step of subsequently bonding the second substrate 200 to the first substrate 100 is performed.

  In order to join the second substrate 200 to the first substrate 100, first, flux 118 is applied to the electrode 112, and the electrode 112 is connected so that the opening 206 and the second semiconductor chip 120B face each other. The second substrate 200 is positioned above the first substrate 100 so as to face the hole 117A. FIG. 8B shows a state in which this positioning has been performed.

  Subsequently, the second substrate 200 is brought into contact with the first substrate 100. As a result, the electrode 112 is temporarily fixed by the flux 118 to the wiring pattern 103A exposed from the connection hole 117A. At the same time, the first and second semiconductor chips 120 </ b> A and 120 </ b> B are in a state where at least a part thereof is located inside the opening 206. In particular, in this embodiment, the back surface of the second semiconductor chip 120B is configured to be flush with the top surface 200a of the second substrate 200.

  As described above, when the second substrate 200 is temporarily fixed to the first substrate 100, the first and second substrates 100 and 200 are mounted in the reflow furnace while maintaining the temporarily fixed state. A heating step is performed. Thereby, the solder coating 114 of the electrode 112 is melted and soldered to the wiring pattern 103A, and the first substrate 100 and the second substrate 200 are joined and laminated by the electrode 112.

  At this time, as the solder alloy constituting the solder coating 114, it is desirable to select a material having a melting point lower than that of the solder alloy constituting the solder ball 121. FIG. 8C shows a state in which the first substrate 100 and the second substrate 200 are joined by the electrode 112.

  Subsequently, a cleaning process for removing the flux residue remaining at the soldering position of the electrode 112 is performed. FIG. 8D shows a state where the cleaning process is performed and the flux residue is removed.

  When the second substrate 200 is mounted on the first substrate 100 as described above, the first and second substrates 100 and 200 after the cleaning step are mounted in a mold (not shown), A transfer molding process for molding the sealing resin 115 is performed. In addition, in the formation process of sealing resin 115, since the same process as the process demonstrated using FIG. 5 (A), (B) is implemented, the description is abbreviate | omitted.

  As described above, according to the manufacturing method according to the present embodiment, it is possible to easily and efficiently manufacture the chip-embedded substrate 300C that can achieve high density while achieving thinning.

  In the above-described manufacturing method, the example of the process of soldering the electrode 112 to the first substrate 100 after soldering the solder ball 121 to the first substrate 100 has been described. However, the solder of the second semiconductor chip 120B is described. Instead of immediately performing the reflow process after temporarily fixing the ball 121 to the first substrate 100, the reflow process may be performed after the electrode 112 is temporarily fixed to the first substrate 100. Thereby, since the soldering process of the solder ball 121 and the electrode 112 can be performed simultaneously, it is possible to improve the manufacturing efficiency and to prevent the semiconductor chips 120A and 120B from being affected by heating. Furthermore, the solder balls 121 and the solder coating 114 can be made of the same solder alloy (material having the same melting point).

  Next, chip built-in substrates 300D to 300G according to second to fifth embodiments of the present invention will be described with reference to FIGS. 9 to 12, the components corresponding to those in the reference example shown in FIGS. 1 and 6 and the chip-embedded substrates 300A and 300C according to the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. .

  FIG. 9 shows a chip built-in substrate 300D according to the second embodiment. In the chip-embedded substrates 300 </ b> A to 300 </ b> C according to the reference example and the example described above, the semiconductor chips 110 </ b> A, 110 </ b> B, 120 </ b> A, 120 </ b> B are flip-chip bonded to the first substrate 100. On the other hand, in the chip-embedded substrate 300D according to the present embodiment, the semiconductor chip 110C is mounted on the first substrate 100 face up, and the semiconductor chip 110C and the first substrate 100 are wire-bonded using the wire 125. It is characterized by being connected.

  The wire bonding method can reduce the cost as compared with the flip chip method, but is disadvantageous in terms of thinning because the wire loop is also formed on the semiconductor chip. However, in this embodiment, since the semiconductor chip 110C has a configuration in which a part of the opening 206 formed in the second substrate 200 is located, a space is formed above the semiconductor chip 110C.

  For this reason, in this embodiment, a space is used above the semiconductor chip 110C, and a wire loop of the wire 125 is formed in the space. Therefore, according to the chip-embedded substrate 300D according to the present embodiment, the semiconductor chip 110C and the first substrate 100 can be thinned and the cost can be reduced even if the wires 125 are used.

  FIG. 10 shows a chip built-in substrate 300E according to the third embodiment. In the chip-embedded substrates 300A to 300D according to each of the embodiments described above, an opening 206 is formed in the second substrate 200, and a part of the semiconductor chips 110A, 110B, 110C, 120A, 120B is formed inside the opening 206. It was set as the structure which aims at thickness reduction of the chip | tip built-in board | substrates 300A-300D by comprising so that it may be located.

  In contrast, in the chip-embedded substrate 300E according to the present embodiment, the concave step portion 126 that is recessed from the upper surface 100a is formed on the first substrate 100, and the semiconductor chip 110A is mounted inside the step portion 126. It is characterized by.

  According to the chip-embedded substrate 300E according to the present embodiment, since a part of the semiconductor chip 110A is configured to be located at least in the stepped portion 126, the height direction (the directions of arrows Z1 and Z2 in the drawing) Since the semiconductor chip 110A and the first substrate 100 can be overlapped, the chip-embedded substrate 300E can be reduced in thickness and size.

  FIG. 11 shows a chip built-in substrate 300F according to the fourth embodiment. The chip built-in substrate 300C according to the first embodiment described above with reference to FIG. 6 is configured such that the second semiconductor chip 120B is positioned as an internal component in the opening 206 in addition to the first semiconductor chip 120A. As a result, the chip-embedded substrate 300C is configured to have a higher density and a thinner thickness.

  In contrast, the chip-embedded substrate 300F according to the present embodiment is configured such that the silicon interposer 130 is positioned in the opening 206 instead of the second semiconductor chip 120B in the first embodiment. (This silicon interposer 130 corresponds to a built-in component recited in the claims.

  The silicon interposer 130 is configured such that a wiring pattern 132 is formed on the lower surface of a silicon substrate body 131 and a plurality of through vias 133 penetrating the substrate body 131 are formed at the center position thereof. One end of the wiring pattern 132 is connected to the lower end of the through via 133, and the solder ball 121 is connected to the other end of the wiring pattern 132.

  Since the through via 133 is formed in the substrate body 131 made of silicon, it can be finely processed. Therefore, the pitch of the adjacent through via 133 can be narrowed. For this reason, it becomes possible to mount a semiconductor device or an electronic device (hereinafter referred to as a high-density component) having a higher density than the semiconductor chip 110A on the silicon interposer 130.

  Therefore, according to the chip-embedded substrate 300F according to the present embodiment, when the high-density component is mounted, it is not necessary to match all the first substrate 100 and the second substrate 200 with the accuracy of the high-density component, and the silicon interposer 130. The accuracy of the first and second substrates 100 and 200 can be set to be equal to or less than that of the high-density component. As a result, it is possible to mount high-density components while reducing costs.

  FIG. 12 shows a chip built-in substrate 300G according to the fifth embodiment. The chip-embedded substrate 300G according to the present embodiment is characterized in that the heat sink 140 is positioned in the opening 206 instead of the second semiconductor chip 120B in the first embodiment.

  The heat sink 140 can be made of a metal having high thermal conductivity such as aluminum. The heat sink 140 is fixed to the back surface of the semiconductor chip 110A using a heat conductive adhesive sheet 141. The upper surface of the heat sink 140 is set so as to be exposed from the second substrate 200 (sealing resin 115).

  With this configuration, the heat generated in the semiconductor chip 110 </ b> A is conducted to the heat sink 140 via the heat conductive adhesive sheet 141, and is radiated to the outside of the apparatus through the heat sink 140. Therefore, according to the chip-embedded substrate 300G according to the present embodiment, it is possible to improve the heat dissipation characteristics of the heat generated in the semiconductor chip 110A. Thereby, generation | occurrence | production of the defect by the heat | fever of the semiconductor chip 110A can be suppressed, and the reliability of the chip built-in substrate 300G can be improved.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments described above, and various modifications can be made within the scope of the present invention described in the claims. It can be modified and changed.

  For example, in each of the above-described embodiments, the solder ball 121 is used for flip-chip bonding the semiconductor chip 120B and the silicon interposer 130 which are built-in components to the first substrate 100. However, instead of the solder ball 121, a core (for example, It is also possible to use a solder ball coated on the outer periphery of a copper ball.

FIG. 1 is a cross-sectional view of a chip built-in substrate which is a reference example of the present invention. FIG. 2 is a cross-sectional view of a chip built-in substrate which is a modification of the reference example. FIG. 3 is a diagram for explaining a manufacturing method of a cross-sectional view of a chip built-in substrate as a reference example (part 1). FIG. 4 is a diagram for explaining a method of manufacturing a cross-sectional view of a chip built-in substrate as a reference example (part 2). FIG. 5 is a view for explaining a method for manufacturing a cross-sectional view of a chip-embedded substrate as a reference example (part 3). FIG. 6 is a cross-sectional view of the chip built-in substrate according to the first embodiment of the present invention. FIG. 7 is a drawing for explaining the method of manufacturing the cross-sectional view of the chip built-in substrate according to the first embodiment (No. 1). FIG. 8 is a drawing for explaining the method of manufacturing the cross-sectional view of the chip built-in substrate according to the first embodiment (No. 2). FIG. 9 is a sectional view of a chip built-in substrate according to the second embodiment of the present invention. FIG. 10 is a sectional view of a chip built-in substrate according to a third embodiment of the present invention. FIG. 11 is a sectional view of a chip built-in substrate according to the fourth embodiment of the present invention. FIG. 12 is a sectional view of a chip built-in substrate according to the fifth embodiment of the present invention.

Explanation of symbols

100 First substrate 101 Core substrate 102, 202 Via plug 103A, 103B, 203A, 203B Wiring pattern 103C, 203C Inner layer wiring 104A, 104B, 204A, 204B Solder resist layer 109 Underfill 110A-110C Semiconductor chip 111, 121 Solder ball 112 Electrode 113 Copper core 114 Solder coating 115 Sealing resin 120A First semiconductor chip 120B Second semiconductor chip 125 Wire 126 Stepped portion 130 Silicon interposer 140 Heat sink 141 Thermally conductive adhesive sheet 200, 200A Second substrate 201 Core substrate 206 Opening 300A ~ 300G Chip built-in substrate

Claims (2)

A first semiconductor chip ;
A first substrate on which the first wiring is formed and the first semiconductor chip is mounted;
A second substrate on which a second wiring is formed and stacked on the first substrate;
A connection member that electrically connects the first substrate and the second substrate; and a sealing resin disposed between the first substrate and the second substrate;
A chip-embedded substrate in which an opening is formed in the second substrate,
The first of the second semiconductor chip larger shape than the first semiconductor chip to a substrate by flip-chip bonding, at least a portion the of the second semiconductor chip and at least part of the first semiconductor chip The second semiconductor chip is located in the opening and the upper part of the first semiconductor chip is configured,
The sealing resin is filled between the first semiconductor chip and the second semiconductor chip , between the second semiconductor chip and the second substrate, and in the opening ,
A chip-embedded substrate configured such that a back surface of the second semiconductor chip in the opening and a surface of the second substrate are flush with each other.   The chip built-in substrate according to claim 1, wherein a surface of the sealing resin in the opening and a surface of the second substrate are flush with each other.

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