JP2006228897A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- JP2006228897A JP2006228897A JP2005039468A JP2005039468A JP2006228897A JP 2006228897 A JP2006228897 A JP 2006228897A JP 2005039468 A JP2005039468 A JP 2005039468A JP 2005039468 A JP2005039468 A JP 2005039468A JP 2006228897 A JP2006228897 A JP 2006228897A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 163
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 229920005989 resin Polymers 0.000 claims description 16
- 239000011347 resin Substances 0.000 claims description 16
- 238000007789 sealing Methods 0.000 claims description 14
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive Effects 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 230000002093 peripheral Effects 0.000 description 7
- 229920001721 Polyimide Polymers 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000000875 corresponding Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000149 penetrating Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
Description
本発明は、基板上の接続端子と半導体素子（チップ）の表面上の電極とが電気的に接続される半導体装置に関する。 The present invention relates to a semiconductor device in which connection terminals on a substrate and electrodes on the surface of a semiconductor element (chip) are electrically connected.
近年、半導体装置の動作速度の高速化が著しく、半導体素子の集積化に伴い、扱われる信号の総数が増加してきている。 In recent years, the operating speed of semiconductor devices has been remarkably increased, and the total number of signals handled has increased with the integration of semiconductor elements.
高速信号を扱う場合に、半導体素子の動作を安定させる上で、電源電圧用及びグランド電位用の電源電流の供給が重要であり、信号の周波数がギガヘルツ（ＧＨｚ）帯となるような高速動作を安定させるためには、扱われる信号の総数と同数以上の電源電圧用電源パッド及びグランド電位用電極パッドをその半導体装置に配設することが必要である。 When handling high-speed signals, it is important to supply power supply current for power supply voltage and ground potential in order to stabilize the operation of the semiconductor element, and high-speed operation is performed so that the signal frequency is in the gigahertz (GHz) band. In order to stabilize, it is necessary to provide power supply pads for power supply voltages and electrode pads for ground potential in the semiconductor device that are equal to or more than the total number of signals to be handled.
さらに、高速動作時の安定性を確保するには、電源電圧用及びグランド電位用電極パッドは、電気抵抗をできる限り小さくすることが望まれる。電気抵抗を小さくするためには、電源電圧用及びグランド電位用パッドは、断面積を大きく、配線長を短くすることが望まれる。 Furthermore, in order to ensure stability during high-speed operation, it is desired that the power supply voltage and ground potential electrode pads have as small an electrical resistance as possible. In order to reduce the electrical resistance, it is desirable that the power supply voltage and ground potential pads have a large cross-sectional area and a short wiring length.
一方、特許文献１には、複数の半導体素子（チップ）を積層した半導体装置（マルチチップモジュール）において、複数の半導体素子が同一位置に同一属性のパッドを有し、キャリア等を介さずに積層配置され、かつ、同一属性のパッド同士が、一方の面から他方の面へ貫通する形状を有するチップ間接続電極を介して電気的接続がなされる構成が提案されている。ここで、同一属性のパッドとは、各半導体素子における役割が同一であるパッドを意味する。例えば、電源電圧用パッド、グランド電位用パッド、データ出力用パッド、アドレス信号用パッド、或いはクロック信号用パッド同士をそれぞれ同一属性のパッドという。
しかし、従来の半導体装置においては、半導体素子（チップ）の周辺部に配設される電極がワイヤボンディングにより、基板上のボンディングパッドと接続される構成であるため、配設されるワイヤや配線の長さに応じて半導体装置の電気的特性が劣化してしまうという問題がある。 However, in the conventional semiconductor device, since the electrode disposed on the periphery of the semiconductor element (chip) is connected to the bonding pad on the substrate by wire bonding, the wires and wirings disposed are arranged. There is a problem that the electrical characteristics of the semiconductor device are degraded depending on the length.
また、従来の半導体装置においては、フリップチップ実装方式を用いることにより、半導体素子の電極パッドに半田バンプ等のバンプを設けて基板に接続して、電源供給のための配線長を小さくすることができる。しかし、半導体装置に搭載される半導体素子の動作高速化や、半導体素子で扱われる信号数の増加に対応させるためにフリップチップ実装を適用する場合、基板の配線ピッチが、半導体素子のファインピッチに対応できないという課題がある。 Also, in the conventional semiconductor device, by using the flip chip mounting method, bumps such as solder bumps are provided on the electrode pads of the semiconductor element and connected to the substrate, thereby reducing the wiring length for supplying power. it can. However, when flip-chip mounting is applied in order to increase the operation speed of a semiconductor element mounted on a semiconductor device or increase the number of signals handled by the semiconductor element, the wiring pitch of the substrate becomes the fine pitch of the semiconductor element. There is a problem that it cannot respond.
本発明は、上記の点に鑑みてなされたものであり、外部からの電源電圧を半導体素子上の電源、グランド電極へ供給するための電源、グランド用配線の経路を最短にして、従来のワイヤボンディング方式に見られる電気特性の劣化を防止できる半導体装置を提供することを目的とする。 The present invention has been made in view of the above points. The conventional wire has a shortest path for a power source for supplying an external power source voltage to a power source on a semiconductor element, a ground electrode, and a ground wiring. An object of the present invention is to provide a semiconductor device capable of preventing the deterioration of electrical characteristics found in the bonding method.
上記の課題を解決するため、本発明の半導体装置は、外部接続端子と接続される接続端子を有する基板と、表面の中央部に配設される電源系電極、周辺部に配設される信号系電極、及び表面と反対側の裏面に露出して形成される内部電極、前記電源系電極と前記内部電極とを電気的に接続する貫通ビアを有し、前記基板上に配設される半導体素子と、前記内部接続端子と前記信号系電極とを電気的に接続するワイヤとを備え、前記半導体素子の表面中央部の前記電源系電極が前記貫通ビアを介し前記基板の前記内部接続端子へ接続されることを特徴とする。 In order to solve the above problems, a semiconductor device according to the present invention includes a substrate having a connection terminal connected to an external connection terminal, a power supply electrode disposed in the center of the surface, and a signal disposed in the periphery. A semiconductor electrode disposed on the substrate, having a system electrode, an internal electrode exposed on the back surface opposite to the front surface, and a through via that electrically connects the power supply system electrode and the internal electrode An element and a wire for electrically connecting the internal connection terminal and the signal system electrode, and the power supply system electrode at the center of the surface of the semiconductor element is connected to the internal connection terminal of the substrate through the through via. It is connected.
上記の課題を解決するため、本発明の半導体装置は、外部接続端子と接続される接続端子を有する基板と、表面の中央部に配設される電源系電極、周辺部に配設される信号系電極、及び表面と反対側の裏面に露出して形成される内部電極、前記電源系電極と前記内部電極とを電気的に接続する貫通ビアを有し、前記基板上に配設される第１の半導体素子と、表面の中央部に配設される電源系電極、周辺部に配設される信号系電極、表面と反対側の裏面に露出して形成される内部電極、前記電源系電極と前記内部電極とを電気的に接続する貫通ビアを有し、前記第１の半導体素子上に積層配設される第２の半導体素子と、前記内部接続端子と前記第１及び前記第２の半導体素子の前記信号系電極とを電気的に接続するワイヤとを備え、前記第２の半導体素子の表面中央部の前記電源系電極が前記第２及び前期第１の半導体素子の各貫通ビアを介し前記基板の前記内部接続端子へ接続されることを特徴とする。 In order to solve the above problems, a semiconductor device according to the present invention includes a substrate having a connection terminal connected to an external connection terminal, a power supply electrode disposed in the center of the surface, and a signal disposed in the periphery. A system electrode, an internal electrode exposed on the back surface opposite to the front surface, a through via that electrically connects the power system electrode and the internal electrode, and is disposed on the substrate. 1 semiconductor element, a power supply system electrode disposed in the center of the surface, a signal system electrode disposed in the periphery, an internal electrode formed exposed on the back surface opposite to the surface, the power supply system electrode A through via electrically connecting the internal electrode and the internal electrode, a second semiconductor element stacked on the first semiconductor element, the internal connection terminal, the first and the second A wire for electrically connecting the signal system electrode of the semiconductor element, the second Wherein the power supply based electrode of the central surface portion of the semiconductor element is connected to the internal connection terminal of the substrate through the through vias of the second and year first semiconductor element.
上記の半導体装置は、前記半導体素子の前記電源系電極に導電性接着材を介し接着固定される金属部材をさらに備え、前記金属部材が封止樹脂により完全に封止されて、封止樹脂の外表面に露出しないように配設される構成としてもよい。 The semiconductor device further includes a metal member that is bonded and fixed to the power supply system electrode of the semiconductor element via a conductive adhesive, and the metal member is completely sealed with a sealing resin. It is good also as a structure arrange | positioned so that it may not be exposed to an outer surface.
あるいは、上記の半導体装置は、前記半導体素子の前記電源系電極に導電性接着材を介し接着固定される金属部材をさらに備え、前記金属部材が封止樹脂により部分的に封止され、封止樹脂の外表面に露出するように配設される構成としてもよい。 Alternatively, the semiconductor device further includes a metal member that is bonded and fixed to the power supply system electrode of the semiconductor element via a conductive adhesive, and the metal member is partially sealed with a sealing resin. It is good also as a structure arrange | positioned so that it may be exposed to the outer surface of resin.
上記の半導体装置は、前記半導体素子の前記電源系電極と前記基板の前記内部接続端子とが半田バンプ又は金バンプを介して接続される構成としてもよい。 The semiconductor device may be configured such that the power supply system electrode of the semiconductor element and the internal connection terminal of the substrate are connected via a solder bump or a gold bump.
本発明の半導体装置において、電源、グランド電極は半導体素子表面の中央部に余裕をもって配置し、貫通ビアにより、半導体素子裏面に形成される内部電極へ接続し、半田バンプ等により基板の接続端子にフリップチップ接続する。また、半導体素子表面の周辺部の信号系電極はファインピッチ対応のワイヤボンディング方式で対応する。電源系配線は、半導体素子の表面中央部の電極が貫通ビアを介し接続される裏面の内部電極でフリップチップ接続することにより、配線長を最短にすることができ、従来のワイヤボンディング方式に見られるような電気特性の劣化を防止することができる。 In the semiconductor device of the present invention, the power supply and ground electrodes are arranged with a margin at the center of the semiconductor element surface, connected to internal electrodes formed on the back surface of the semiconductor element by through vias, and connected to the connection terminals of the substrate by solder bumps or the like. Flip chip connection. Further, the signal system electrodes in the peripheral part of the surface of the semiconductor element are supported by a wire bonding method compatible with fine pitch. Power supply wiring can be shortened by flip-chip connection with the internal electrode on the back surface where the electrode at the center of the front surface of the semiconductor element is connected via a through via, which is similar to the conventional wire bonding method. It is possible to prevent the deterioration of electrical characteristics.
次に、本発明を実施するための形態について図面を用いて説明する。 Next, embodiments for carrying out the present invention will be described with reference to the drawings.
図１は本発明の一実施形態に係る半導体装置の構成を示す平面図である。図２は図１の半導体装置の構成を示す略断面図である。 FIG. 1 is a plan view showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing the configuration of the semiconductor device of FIG.
図１と図２において、１は半導体素子（チップ）、２は半導体素子１の表面側の周辺部に配設される信号系電極パッド、３は半導体素子１の表面側中央部に配設される電源系電極パッド（電源電圧用及びグランド電位用）、４は半導体素子１の裏面側に配設される電源系電極パッド（電源電圧用及びグランド電位用）、５は貫通ビア、６は半田バンプ、７は基板、８はアンダーフィル、９はボンディングワイヤ、１０は封止樹脂、１１は半田ボールをそれぞれ示す。 1 and FIG. 2, 1 is a semiconductor element (chip), 2 is a signal system electrode pad disposed in a peripheral portion on the surface side of the semiconductor element 1, and 3 is disposed in a central portion on the surface side of the semiconductor element 1. Power supply system electrode pads (for power supply voltage and ground potential), 4 is a power supply system electrode pad (for power supply voltage and ground potential) disposed on the back side of the semiconductor element 1, 5 is a through via, and 6 is solder. Bumps, 7 are substrates, 8 is underfill, 9 is a bonding wire, 10 is a sealing resin, and 11 is a solder ball.
この実施形態の半導体装置において、基板７は、マザーボード等と半田ボール１１（外部接続端子）を介して接続されるボンディングパッド７ａ（内部接続端子）を備える。半導体素子１は、アンダーフィル８により基板７上に搭載され、表面側中央部に配設される電源系電極パッド３と、表面側周辺部に配設される信号系電極パッド２と、裏面側に露出して形成される電極パッド４とを備える。 In the semiconductor device of this embodiment, the substrate 7 includes bonding pads 7a (internal connection terminals) connected to a mother board or the like via solder balls 11 (external connection terminals). The semiconductor element 1 is mounted on a substrate 7 by an underfill 8 and is provided with a power supply system electrode pad 3 disposed in the center portion on the front surface side, a signal system electrode pad 2 disposed on the peripheral portion on the front surface side, and a back surface side. And an electrode pad 4 formed to be exposed to the surface.
電源系電極パッド３は、半導体素子１内の電源層（図示せず）に電気的に接続されている。ボンディングワイヤ９は、基板７のボンディングパッド７ａと半導体素子１の信号系電極パッド２とを電気的に接続する。貫通ビア５は、半導体素子１内に形成され、表面側の電源系電極パッド３と裏面側の電極パッド４とを電気的に接続する。半導体素子１の表面中央部の電源系電極パッド３は、貫通ビア５と半田バンプ６を介して基板７の電源用パッド７ｃへ接続される。 The power supply system electrode pad 3 is electrically connected to a power supply layer (not shown) in the semiconductor element 1. The bonding wire 9 electrically connects the bonding pad 7 a of the substrate 7 and the signal system electrode pad 2 of the semiconductor element 1. The through via 5 is formed in the semiconductor element 1 and electrically connects the power supply system electrode pad 3 on the front surface side and the electrode pad 4 on the back surface side. The power supply system electrode pad 3 at the center of the surface of the semiconductor element 1 is connected to the power supply pad 7 c of the substrate 7 through the through via 5 and the solder bump 6.
従って、図２の半導体装置において、半導体素子１の電源系の配線は、電源系電極パッド３、貫通ビア５、半導体素子１裏面の電極パッド４、半田バンプ６、基板７の電源用パッド７ｃ、基板７のビア７ｄ、半田バンプ６を介して実装基板に接続される。この実施形態の半導体装置では、チップ裏面側の電極パッド４でフリップチップ接続することにより、電源系の配線長を最短にすることができ、従来のワイヤボンディング方式に見られるような電気特性の劣化を防止することができる。 Accordingly, in the semiconductor device of FIG. 2, the power supply wiring of the semiconductor element 1 includes the power supply electrode pad 3, the through via 5, the electrode pad 4 on the back surface of the semiconductor element 1, the solder bump 6, the power supply pad 7c of the substrate 7, The substrate 7 is connected to the mounting substrate via vias 7 d and solder bumps 6. In the semiconductor device of this embodiment, the wiring length of the power supply system can be minimized by performing flip chip connection with the electrode pad 4 on the back surface side of the chip, and the electrical characteristics deteriorate as seen in the conventional wire bonding method. Can be prevented.
図１の構成では、半導体素子１表面の周辺部に配設される電極パッドは全て信号系電極パッド２であり、半導体素子１表面の中央部に配設される電極パッドは全て電源系電極パッド３である例を示している。しかし、本発明は上記の構成のみに限定されない。すなわち、本発明の半導体装置において、電源系電極パッド３の配置位置は任意に設定可能である。例えば、図１の半導体素子１の周辺部の信号系電極パッド２のうち一部の電極パッドのみ、電源系電極パッド３に置き換え、かつ、中央部の電源系電極パッド３のうち一部の電極パッドを信号系電極パッド２と置き換えて配置する構成であっても適用可能である。 In the configuration of FIG. 1, all the electrode pads disposed on the periphery of the surface of the semiconductor element 1 are signal system electrode pads 2, and all of the electrode pads disposed on the center of the surface of the semiconductor element 1 are power system electrode pads. An example of 3 is shown. However, the present invention is not limited to the above configuration. That is, in the semiconductor device of the present invention, the arrangement position of the power supply system electrode pad 3 can be arbitrarily set. For example, only some of the electrode pads 2 in the peripheral part of the signal system electrode pad 2 of the semiconductor element 1 in FIG. 1 are replaced with the power system electrode pads 3, and some of the electrodes in the central part of the power system electrode pad 3 The present invention can also be applied to a configuration in which the pads are replaced with the signal system electrode pads 2.
次に、図３乃至図５を用いて上記の実施形態の半導体装置の製造工程を説明する。図３乃至図５は、図１の半導体装置の製造工程を説明するための図である。 Next, the manufacturing process of the semiconductor device of the above embodiment will be described with reference to FIGS. 3 to 5 are views for explaining a manufacturing process of the semiconductor device of FIG.
まず、図３（ａ）に示すように、半導体素子１（例えば、シリコンに集積回路が形成されたチップ）は、表面側の周辺部に配置された信号系電極パッド２と、中央部に配置された電源系電極パッド３（電源電圧用及びグランド電位用）を備えている。 First, as shown in FIG. 3A, a semiconductor element 1 (for example, a chip in which an integrated circuit is formed on silicon) is arranged at a signal system electrode pad 2 arranged at a peripheral portion on the surface side and at a central portion. The power supply system electrode pad 3 (for power supply voltage and ground potential) is provided.
また、図３（ｂ）に示すように、半導体素子１の表面中央部の各電源系電極パッド３の位置において、レーザ加工又はエッチング等を行って、半導体素子１の表面から裏面まで穴を貫通させる。この場合の穴あけ加工の直径は、例えば、０．１００ｍｍ以下である。そして、熱処理により貫通穴の内壁に絶縁膜を形成する。 Further, as shown in FIG. 3B, laser processing or etching is performed at the position of each power supply system electrode pad 3 in the center of the surface of the semiconductor element 1 to penetrate the hole from the surface to the back surface of the semiconductor element 1. Let The diameter of the drilling process in this case is 0.100 mm or less, for example. Then, an insulating film is formed on the inner wall of the through hole by heat treatment.
次に、図３（ｃ）に示すように、銅（Ｃｕ）等の導電性金属を充填して貫通穴を穴埋めすることにより、貫通ビア５を形成する。そして、アルミニウム（Ａｌ）等の金属で、この貫通ビア５と接続させ、かつ、半導体素子１の裏面に露出させた電極パッド４を形成する。 Next, as illustrated in FIG. 3C, the through via 5 is formed by filling the through hole with a conductive metal such as copper (Cu). Then, an electrode pad 4 is formed which is connected to the through via 5 with a metal such as aluminum (Al) and exposed on the back surface of the semiconductor element 1.
次に、図３（ｄ）に示すように、半導体素子１の表面及び裏面に、ポリイミド（ＰＩ）コート１４を塗布する。ここで、後述するワイヤボンディングを行うため、半導体素子１の表面側の信号系電極パッド２上にはＰＩコート１４を塗布しない（或いは、除去しておく）。同様に、半田バンプによるフリップチップ実装を行うため、半導体素子１の裏面側中央の内部電極パッド４上にはＰＩコート１４を塗布しない（或いは、除去しておく）。 Next, as shown in FIG. 3D, a polyimide (PI) coat 14 is applied to the front and back surfaces of the semiconductor element 1. Here, in order to perform wire bonding described later, the PI coat 14 is not applied (or removed) on the signal system electrode pad 2 on the surface side of the semiconductor element 1. Similarly, in order to perform flip chip mounting by solder bumps, the PI coat 14 is not applied (or removed) on the internal electrode pad 4 at the center of the back surface side of the semiconductor element 1.
次に、半導体素子１の裏面側の内部電極パッド４に半田バンプ６を形成するための工程が行われる。まず、図４（ａ）に示すように、半導体素子１の表面側に、レジストでバリアメタル形成用のマスク１５を形成する。また、チタン（Ｔｉ）、クロム（Ｃｒ）等の中間金属を用いて、半導体素子１の裏面側の内部電極パッド４のアルミニウム電極上にスパッタリングを行う。ニッケル（Ｎｉ）等で電解めっき法を行い、ニッケルめっき層を形成する。 Next, a process for forming solder bumps 6 on the internal electrode pads 4 on the back side of the semiconductor element 1 is performed. First, as shown in FIG. 4A, a mask 15 for forming a barrier metal is formed with a resist on the surface side of the semiconductor element 1. Further, sputtering is performed on the aluminum electrode of the internal electrode pad 4 on the back surface side of the semiconductor element 1 using an intermediate metal such as titanium (Ti) or chromium (Cr). An electroplating method is performed with nickel (Ni) or the like to form a nickel plating layer.
さらに、図４（ｂ）に示すように、半田めっきを行い、マスク１５を除去した後、半田リフローを行うことにより、バリアメタル１６を形成する。この場合のバリアメタル１６は、中間金属層、ニッケルめっき層、及び半田めっき層を含む多層金属膜で形成される。 Further, as shown in FIG. 4B, after performing solder plating and removing the mask 15, the barrier metal 16 is formed by performing solder reflow. In this case, the barrier metal 16 is formed of a multilayer metal film including an intermediate metal layer, a nickel plating layer, and a solder plating layer.
次に、図４（ｃ）に示すように、基板７の表面中央部の、半導体素子１の裏面側の内部電極パッド４と対応する位置に配設される電源用パッド７ｃ上にフリップチップ実装用の半田バンプ６を形成する。この例では、基板７の材質は、例えば、ガラスエポキシ材又はポリイミド樹脂が用いられる。 Next, as shown in FIG. 4C, flip-chip mounting is performed on the power supply pad 7c disposed at a position corresponding to the inner electrode pad 4 on the back surface side of the semiconductor element 1 at the center of the front surface of the substrate 7. A solder bump 6 is formed. In this example, the material of the substrate 7 is, for example, a glass epoxy material or a polyimide resin.
上述した図４（ｃ）の例では、基板７側に半田バンプ６を形成する工程を説明したが、その代わりに、図４（ｂ）で形成した半導体素子１の裏面側のバリアメタル１６上にフリップチップ実装用の半田バンプ６を形成してもよい。 In the example of FIG. 4C described above, the process of forming the solder bumps 6 on the substrate 7 side has been described. Instead, on the barrier metal 16 on the back surface side of the semiconductor element 1 formed in FIG. 4B. Alternatively, solder bumps 6 for flip chip mounting may be formed.
また、上述した例では、半田バンプ６を形成する工程を説明したが、半田バンプ６の代わりに、金バンプ（Ａｕスタッドバンプ）を形成してフリップチップ実装用に用いてもよい。 In the above-described example, the process of forming the solder bump 6 has been described. However, instead of the solder bump 6, a gold bump (Au stud bump) may be formed and used for flip chip mounting.
次に、図５（ａ）に示すように、半田バンプ６を用いてフリップチップ実装を行い、半導体素子１を基板７上に搭載する。また、半導体素子１の裏面と基板７の表面の間隙部に、エポキシ樹脂を注入し、加熱して樹脂を硬化させることにより、アンダーフィル８を形成する。このアンダーフィル８により、半導体素子１と基板７とのバンプ接続部が補強され、半導体素子１は基板７上に接着固定される。 Next, as shown in FIG. 5A, flip chip mounting is performed using the solder bumps 6 to mount the semiconductor element 1 on the substrate 7. An underfill 8 is formed by injecting an epoxy resin into the gap between the back surface of the semiconductor element 1 and the surface of the substrate 7 and heating to cure the resin. The underfill 8 reinforces the bump connection portion between the semiconductor element 1 and the substrate 7, and the semiconductor element 1 is bonded and fixed onto the substrate 7.
次に、図５（ｂ）に示すように、ワイヤボンディングを行うことにより、基板７の表面周辺部のボンディングパッド７ａと、半導体素子１の表面周辺部の信号系電極パッド２とをワイヤ９で接続する。 Next, as shown in FIG. 5B, by wire bonding, the bonding pads 7a around the surface of the substrate 7 and the signal system electrode pads 2 around the surface of the semiconductor element 1 are connected with wires 9. Connecting.
その後、樹脂封止を行うことにより、基板７上の半導体素子１及びワイヤ９が封止樹脂１０で一体的に封止される。また、図２に示すように、半田ボール１１が基板７の裏面に配置されたパッド７ｂ上に搭載される。最後に、パッケージサイズに切り出して半導体装置が完成する。 Thereafter, the semiconductor element 1 and the wire 9 on the substrate 7 are integrally sealed with the sealing resin 10 by performing resin sealing. Further, as shown in FIG. 2, the solder balls 11 are mounted on the pads 7 b arranged on the back surface of the substrate 7. Finally, the semiconductor device is completed by cutting into package sizes.
従来のワイヤボンディング方式では、ワイヤの配線長が１〜２ｍｍであったのに比べ、上記の実施形態によれば、貫通ビア５の配線長は略チップの厚さと等しいため、電源系の配線長を０．０５〜０．２ｍｍと極めて小さくできる。 In the conventional wire bonding method, the wiring length of the through via 5 is substantially equal to the thickness of the chip according to the above embodiment, compared with the wiring length of 1 to 2 mm. Can be as small as 0.05 to 0.2 mm.
また、上記の実施形態では、半導体素子１の表面中央に電源電圧用及びグランド電位用電極を配置することにより、半導体素子１の周辺部に配置する場合と比べて、チップ内の配線長も短くできる。この場合の配線長の差は、半導体素子１の配線が微細化されるほど、大きくなる。 Further, in the above embodiment, the power supply voltage and ground potential electrodes are arranged at the center of the surface of the semiconductor element 1, so that the wiring length in the chip is shorter than the case where the electrodes are arranged in the peripheral part of the semiconductor element 1. it can. In this case, the difference in the wiring length increases as the wiring of the semiconductor element 1 is miniaturized.
図６は、本発明の他の実施形態に係る半導体装置の構成を示す略断面図である。この実施形態では、複数の半導体素子を積層配置した半導体装置において、本発明の貫通ビアの裏面電極を利用した構成を適用したものである。 FIG. 6 is a schematic cross-sectional view showing a configuration of a semiconductor device according to another embodiment of the present invention. In this embodiment, a configuration using a back electrode of a through via of the present invention is applied to a semiconductor device in which a plurality of semiconductor elements are stacked.
なお、図６において、上記の実施形態の説明に用いた図２の構成と同一の構成については同一符号を付して、その説明を省略する。 In FIG. 6, the same components as those in FIG. 2 used for the description of the above embodiment are denoted by the same reference numerals, and the description thereof is omitted.
図６において、１ａは上段の半導体素子、１ｂは下段の半導体素子、２ａと２ｂは半導体素子１ａ、１ｂの表面側周辺部に配設される各信号系電極パッド、３ａと３ｂは半導体素子１ａ、１ｂの表面側中央部に配設される各電源系電極パッド、４ａと４ｂは半導体素子１ａ、１ｂの裏面側に配設される各電源系電極パッド、５ａと５ｂは半導体素子１ａ、１ｂの各貫通ビア、６ａと６ｂは半導体素子１ａ、１ｂの各半田バンプ、７は基板、８はアンダーフィル、９ａと９ｂはワイヤ、１１は半田ボールをそれぞれ示す。 In FIG. 6, reference numeral 1a denotes an upper semiconductor element, 1b denotes a lower semiconductor element, 2a and 2b denote signal system electrode pads disposed on the surface side periphery of the semiconductor elements 1a and 1b, and 3a and 3b denote semiconductor elements 1a. 1b, power supply system electrode pads 4a and 4b arranged on the front side of the front surface side of the semiconductor element 1a, 1b, power supply system electrode pads 5a and 5b of the semiconductor elements 1a and 1b. 6a and 6b are solder bumps of the semiconductor elements 1a and 1b, 7 is a substrate, 8 is an underfill, 9a and 9b are wires, and 11 is a solder ball.
図６の半導体装置において、基板７は、マザーボード等と半田ボール１１（外部接続端子）を介して接続されるボンディングパッド７ａ（内部接続端子）を備える。下段の半導体素子１ｂは、アンダーフィル８により基板７上に搭載され、表面側中央部に配設される電源系電極パッド３ｂと、表面側周辺部に配設される信号系電極パッド２ｂと、裏面側に露出して形成される電極パッド４ｂとを備える。上段の半導体素子１ａは、フリップチップ実装により下段の半導体素子１ｂ上に搭載され、表面側中央部に配設される電源系電極パッド３ａと、表面側周辺部に配設される信号系電極パッド２ａと、裏面側に露出して形成される電極パッド４ａとを備える。 In the semiconductor device of FIG. 6, the substrate 7 includes bonding pads 7a (internal connection terminals) connected to a mother board or the like via solder balls 11 (external connection terminals). The lower semiconductor element 1b is mounted on the substrate 7 by the underfill 8, and includes a power supply system electrode pad 3b disposed in the center portion on the front surface side, a signal system electrode pad 2b disposed on the peripheral portion on the front surface side, And an electrode pad 4b formed exposed on the back side. The upper semiconductor element 1a is mounted on the lower semiconductor element 1b by flip-chip mounting, and the power supply system electrode pad 3a disposed in the center portion on the surface side and the signal system electrode pad disposed in the periphery portion on the surface side. 2a and an electrode pad 4a formed exposed on the back surface side.
ボンディングワイヤ９ａ、９ｂは、基板７のボンディングパッド７ａと、半導体素子１ａ、１ｂの各信号系電極パッド２ａ、２ｂとをそれぞれ電気的に接続する。貫通ビア５ａ、５ｂは、半導体素子１ａ、１ｂ内にそれぞれ形成され、表面側の電源系電極パッド３ａ、３ｂと裏面側の電極パッド４ａ、４ｂとをそれぞれ電気的に接続する。上段の半導体素子１ａの表面中央部の電源系電極パッド３ａは、貫通ビア５ａと半田バンプ６ａを介して下段の半導体素子１ｂの表面中央部の電源系電極パッド３ｂへ接続される。また、下段の半導体素子１ｂの表面中央部の電源系電極パッド３ｂは、貫通ビア５ｂと半田バンプ６ｂを介して基板７の内部接続端子（パッド７ａ）へ接続される。 The bonding wires 9a and 9b electrically connect the bonding pad 7a of the substrate 7 and the signal system electrode pads 2a and 2b of the semiconductor elements 1a and 1b, respectively. The through vias 5a and 5b are formed in the semiconductor elements 1a and 1b, respectively, and electrically connect the power supply system electrode pads 3a and 3b on the front side and the electrode pads 4a and 4b on the back side. The power supply system electrode pad 3a at the center of the surface of the upper semiconductor element 1a is connected to the power supply system electrode pad 3b at the center of the surface of the lower semiconductor element 1b through the through via 5a and the solder bump 6a. The power supply system electrode pad 3b at the center of the surface of the lower semiconductor element 1b is connected to the internal connection terminal (pad 7a) of the substrate 7 through the through via 5b and the solder bump 6b.
従って、図６の半導体装置において、電源系の配線は、半導体素子１ａ、１ｂ側の電源系電極パッド３ａ、３ｂ、貫通ビア５ａ、５ｂ、及び電極パッド４ａ、４ｂと、基板７側の内部接続端子７ａとを半田バンプ６ａ、６ｂを介して接続することにより構成される。この実施形態の半導体装置では、チップ裏面側の電極パッド４ａ、４ｂでフリップチップ実装することにより、電源系の配線長を最短にすることができ、従来のワイヤボンディング方式に見られるような電気特性の劣化を防止することができる。 Therefore, in the semiconductor device of FIG. 6, the power supply system wiring includes the power supply system electrode pads 3a and 3b on the semiconductor elements 1a and 1b side, the through vias 5a and 5b, and the electrode pads 4a and 4b, and the internal connection on the substrate 7 side. The terminal 7a is connected by solder bumps 6a and 6b. In the semiconductor device of this embodiment, the wiring length of the power supply system can be minimized by flip-chip mounting with the electrode pads 4a and 4b on the back side of the chip, and the electrical characteristics as seen in the conventional wire bonding system Can be prevented.
この実施形態の積層型半導体装置は、上述の図３乃至図５で説明した半導体装置の製造工程を用いて同様に製造することができるので、この実施形態の半導体装置の製造工程の説明は省略する。 Since the stacked semiconductor device of this embodiment can be manufactured in the same manner by using the manufacturing process of the semiconductor device described with reference to FIGS. 3 to 5, the description of the manufacturing process of the semiconductor device of this embodiment is omitted. To do.
図７は、本発明のさらに別の実施形態に係る半導体装置の構成を示す略断面図である。この実施形態の半導体装置は、熱特性を向上させるため、放熱用金属板を搭載したものである。 FIG. 7 is a schematic cross-sectional view showing a configuration of a semiconductor device according to still another embodiment of the present invention. The semiconductor device of this embodiment is equipped with a heat radiating metal plate in order to improve thermal characteristics.
なお、上記の実施形態の説明に用いた図２の構成と同一の構成については同一符号を付して、その説明を省略する。 In addition, the same code | symbol is attached | subjected about the structure same as the structure of FIG. 2 used for description of said embodiment, and the description is abbreviate | omitted.
図７において、１２（又は１２ａ）は放熱用金属板を、１３は導電性接着材をそれぞれ示す。この実施形態の半導体装置において、放熱用金属板１２は、裏面側の、半導体素子１の表面中央部の電源系電極パッド３とそれぞれ対応する箇所から下方に突出する複数の足部を備える。半導体素子１を基板７にフリップチップ実装した後、放熱用金属板１２の各足部の裏面に導電性接着剤１３を塗布して、放熱用金属板１２の各足部を、半導体素子１の表面中央部の対応する電源系電極パッド３に接着固定する。図２の実施形態と同様に、樹脂封止を行って、基板７上の半導体素子１、ワイヤ９、及び放熱用金属板１２が封止樹脂１０で一体的に封止される
図７（ａ）に示す放熱用金属板１２は、封止樹脂１０により完全に封止されて封止樹脂１０の外表面に露出しないように配設される。図７（ｂ）に示す放熱用金属板１２ａは、封止樹脂１０により部分的に封止され、封止樹脂１０の外表面に露出するように配設される。放熱用金属板の配設のしかたは、図７（ａ）に示すような外部に露出しない構成であってもよいし、図７（ｂ）に示すような外部に露出した構成であってもよい。
In FIG. 7, 12 (or 12a) indicates a metal plate for heat dissipation, and 13 indicates a conductive adhesive. In the semiconductor device of this embodiment, the heat radiating metal plate 12 includes a plurality of legs projecting downward from locations corresponding to the power supply system electrode pads 3 at the center of the front surface of the semiconductor element 1 on the back surface side. After flip-chip mounting the semiconductor element 1 on the substrate 7, a conductive adhesive 13 is applied to the back surface of each foot portion of the heat radiating metal plate 12, and each foot portion of the heat radiating metal plate 12 is attached to the semiconductor element 1. It is bonded and fixed to the corresponding power supply system electrode pad 3 at the center of the surface. As in the embodiment of FIG. 2, resin sealing is performed, and the semiconductor element 1, the wires 9, and the heat radiating metal plate 12 on the substrate 7 are integrally sealed with the sealing resin 10. The heat dissipating metal plate 12 shown in FIG. 3 is completely sealed by the sealing resin 10 and is disposed so as not to be exposed on the outer surface of the sealing resin 10. The heat radiating metal plate 12 a shown in FIG. 7B is partially sealed with the sealing resin 10 and disposed so as to be exposed on the outer surface of the sealing resin 10. The disposition of the metal plate for heat dissipation may be a configuration that is not exposed to the outside as shown in FIG. 7A or a configuration that is exposed to the outside as shown in FIG. 7B. Good.
図８は、本発明の他の実施形態に係る半導体装置の構成を示す略断面図である。 FIG. 8 is a schematic cross-sectional view showing a configuration of a semiconductor device according to another embodiment of the present invention.
この実施形態の半導体装置は、上述した図２のＢＧＡパッケージの形態を変更して、ＬＧＡ（ランド・グリッド・アレイ）パッケージとしたものである。 The semiconductor device of this embodiment is an LGA (Land Grid Array) package by changing the form of the BGA package of FIG. 2 described above.
図８に示すように、この実施形態では、図２の構成における基板７の裏面側に半田ボール１１を配設することなく、基板７の裏面側にはパッド７ｂのランドパターンのみが形成される構成である。この実施形態のＬＧＡパッケージの場合には、半田ボール１１が無い分だけパーケージの取り付け高さを低くでき、半導体装置の薄型化に有利である。また、ＢＧＡパッケージの場合よりもファインピッチ化が可能であり、多ピン化にも有利である。さらに、この実施形態の半導体装置を実装ボードに搭載する場合、半田ボールの材質を実装側で選択することができる。 As shown in FIG. 8, in this embodiment, only the land pattern of the pad 7b is formed on the back surface side of the substrate 7 without providing the solder balls 11 on the back surface side of the substrate 7 in the configuration of FIG. It is a configuration. In the case of the LGA package of this embodiment, the mounting height of the package can be lowered as much as there is no solder ball 11, which is advantageous for making the semiconductor device thinner. In addition, a fine pitch can be achieved compared to the case of the BGA package, which is advantageous for increasing the number of pins. Furthermore, when the semiconductor device of this embodiment is mounted on a mounting board, the material of the solder ball can be selected on the mounting side.
以上説明したように、本発明の半導体装置によれば、半導体素子の表面側の任意の位置に電源電圧用電極、グランド電位用電極を設け、貫通ビアで半導体素子の裏面側に内部電極を配置して、フリップチップ実装により半導体素子を基板に実装する。外部からの電源電圧を外部接続端子を介し半導体素子の電源系電極へ供給するための電源系配線の経路を最短で確保することが可能となり、電気特性の劣化を防止できる。また、半導体素子の周辺部に配置される信号系電極はローコストでファインピッチに対応可能なワイヤボンディング方式で接続することにより、安価でファインピッチの電極パッドに対応した、高周波信号を扱う半導体パッケージを提供することができる。 As described above, according to the semiconductor device of the present invention, the power supply voltage electrode and the ground potential electrode are provided at arbitrary positions on the front surface side of the semiconductor element, and the internal electrode is disposed on the back surface side of the semiconductor element with the through via. Then, the semiconductor element is mounted on the substrate by flip chip mounting. It is possible to secure the power supply system wiring path for supplying the power supply voltage from the outside to the power supply system electrode of the semiconductor element via the external connection terminal, and to prevent the deterioration of electrical characteristics. In addition, the signal system electrodes arranged at the periphery of the semiconductor element are connected by a wire bonding method that can handle fine pitch at low cost, so that a low-cost semiconductor package that handles high-frequency signals compatible with fine pitch electrode pads can be obtained. Can be provided.
１ 半導体素子
２ 電極パッド（信号系）
３ 表面側電極パッド（電源系）
４ 裏面側電極パッド（電源系）
５ 貫通ビア
６ 半田バンプ
７ 基板
７ａ ボンディングパッド
７ｂ パッド
７ｃ 電源用パッド
７ｄ ビア
８ アンダーフィル
９ ボンディングワイヤ
１０ 封止樹脂
１１ 半田ボール
１２、１２ａ 放熱用金属板
１３ 導電性接着剤
１４ ポリイミドコート
１５ マスク
１６ バリアメタル
1 Semiconductor Device 2 Electrode Pad (Signal System)
3 Front-side electrode pad (power supply system)
4 Back side electrode pad (Power supply system)
DESCRIPTION OF SYMBOLS 5 Through-via 6 Solder bump 7 Board | substrate 7a Bonding pad 7b Pad 7c Power supply pad 7d Via 8 Underfill 9 Bonding wire 10 Sealing resin 11 Solder ball 12, 12a Metal plate for heat dissipation 13 Conductive adhesive 14 Polyimide coating 15 Mask 16 Barrier metal
Claims (5)
表面の中央部に配設される電源系電極、周辺部に配設される信号系電極、及び表面と反対側の裏面に露出して形成される内部電極、前記電源系電極と前記内部電極とを電気的に接続する貫通ビアを有し、前記基板上に配設される半導体素子と、
前記内部接続端子と前記信号系電極とを電気的に接続するワイヤと
を備え、前記半導体素子の表面中央部の前記電源系電極が前記貫通ビアを介し前記基板の前記内部接続端子へ接続されることを特徴とする半導体装置。 A substrate having an internal connection terminal connected to the external connection terminal;
A power supply system electrode disposed at the center of the surface, a signal system electrode disposed at the periphery, an internal electrode formed exposed on the back surface opposite to the front surface, the power supply system electrode and the internal electrode; A semiconductor element having a through via for electrically connecting, and disposed on the substrate;
A wire for electrically connecting the internal connection terminal and the signal system electrode, and the power supply system electrode at the center of the surface of the semiconductor element is connected to the internal connection terminal of the substrate through the through via. A semiconductor device.
表面の中央部に配設される電源系電極、周辺部に配設される信号系電極、及び表面と反対側の裏面に露出して形成される内部電極、前記電源系電極と前記内部電極とを電気的に接続する貫通ビアを有し、前記基板上に配設される第１の半導体素子と、
表面の中央部に配設される電源系電極、周辺部に配設される信号系電極、及び表面と反対側の裏面に露出して形成される内部電極、前記電源系電極と前記内部電極とを電気的に接続する貫通ビアを有し、前記第１の半導体素子上に積層配設される第２の半導体素子と、
前記内部接続端子と前記第１及び前記第２の半導体素子の前記信号系電極とを電気的に接続するワイヤと
を備え、前記第２の半導体素子の表面中央部の前記電源系電極が前記第２及び前期第１の半導体素子の各貫通ビアを介し前記基板の前記内部接続端子へ接続されることを特徴とする半導体装置。 A substrate having an internal connection terminal connected to the external connection terminal;
A power supply system electrode disposed at the center of the surface, a signal system electrode disposed at the periphery, an internal electrode formed exposed on the back surface opposite to the front surface, the power supply system electrode and the internal electrode; A first semiconductor element having a through via for electrically connecting, and disposed on the substrate;
A power supply system electrode disposed at the center of the surface, a signal system electrode disposed at the periphery, an internal electrode formed exposed on the back surface opposite to the front surface, the power supply system electrode and the internal electrode; A second semiconductor element having a through via electrically connecting the first semiconductor element and a second semiconductor element stacked on the first semiconductor element;
A wire electrically connecting the internal connection terminal and the signal system electrode of the first and second semiconductor elements, and the power supply system electrode at the center of the surface of the second semiconductor element is the first 2 and the first semiconductor element connected to the internal connection terminal of the substrate through each through via of the first semiconductor element.
5. The semiconductor device according to claim 1, wherein the power supply system electrode of the semiconductor element and the internal connection terminal of the substrate are connected via a solder bump or a gold bump. 6.
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| US7615487B2 (en) | 2007-03-15 | 2009-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power delivery package having through wafer vias |
| JP2011204979A (en) * | 2010-03-26 | 2011-10-13 | Oki Electric Industry Co Ltd | Semiconductor chip, semiconductor multilayer circuit, and method of manufacturing semiconductor chip |
| JP2012502470A (en) * | 2008-09-09 | 2012-01-26 | エルエスアイ コーポレーション | Powered and grounded package via via |
| US8153521B2 (en) | 2007-12-27 | 2012-04-10 | Samsung Electronics Co., Ltd. | Wafer-level stack package |
| JP5621593B2 (en) * | 2008-06-23 | 2014-11-12 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2007189231A (en) * | 2006-01-13 | 2007-07-26 | Agere Systems Inc | Integrated circuit having second substrate for easy distribution of grounding and core power supply |
| US7615487B2 (en) | 2007-03-15 | 2009-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Power delivery package having through wafer vias |
| US8153521B2 (en) | 2007-12-27 | 2012-04-10 | Samsung Electronics Co., Ltd. | Wafer-level stack package |
| JP5621593B2 (en) * | 2008-06-23 | 2014-11-12 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP2012502470A (en) * | 2008-09-09 | 2012-01-26 | エルエスアイ コーポレーション | Powered and grounded package via via |
| JP2013085007A (en) * | 2008-09-09 | 2013-05-09 | Lsi Corp | Package supplied power and connected to ground through via |
| JP2011204979A (en) * | 2010-03-26 | 2011-10-13 | Oki Electric Industry Co Ltd | Semiconductor chip, semiconductor multilayer circuit, and method of manufacturing semiconductor chip |
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