JP2021019081A - Semiconductor package - Google Patents

Abstract

To improve the connection reliability between rewiring and a passive component in a semiconductor with fan-out structure in which the passive component is covered with a mold resin together with a semiconductor chip.SOLUTION: In a semiconductor package with fan-out structure, a recess 21 that exposes a side surface 31b of a pair of electrodes of a passive component 3 is formed on an undersurface 2a of a mold resin 2 that covers a semiconductor chip 1 and the passive component 3. A passive component wiring 421 that electrically connects a terminal 11 of the semiconductor chip 1 and the passive component 3 has a shape in which part of it is along the recess 21 and covers part exposed from the mold resin 2 of a side surface 31b of an electrode 31 of the passive component 3. As a result, connection area between the passive component wiring 421 and the passive component 3 becomes larger and the connection reliability improves.SELECTED DRAWING: Figure 3

Description

The present invention relates to a semiconductor package having a fan-out structure including a semiconductor chip and electronic components.

Conventionally, as a semiconductor package having a fan-out structure in which a semiconductor chip is covered with a mold resin and rewiring connected to a terminal of the semiconductor chip is extended to the outside of the outer shape of the semiconductor chip, for example, the one described in Patent Document 1. Can be mentioned.

In the semiconductor package described in Patent Document 1, an IC chip on which terminals are formed, a sealing material covering the terminals, one end is connected to the terminals, and the other end is outside the outer shape of the IC chip in a plan view. Provided with a rewiring layer containing extended wiring. This semiconductor package is a BGA (ball grid array) package having a fan-out structure in which the other end of the wiring is exposed from the rewiring layer and bumps made of solder or the like are formed. The fan-out structure semiconductor package has excellent mountability because the bumps used for mounting on a substrate or the like are expanded by a rewiring layer.

JP-A-2019-80030

By the way, in recent years, in the field of semiconductor packages, high frequencies and high currents have been increasing. On the other hand, as the frequency and current increase, the noise of the high frequency signal increases, and it is required to eliminate this noise and improve the electrical characteristics of the semiconductor device using the semiconductor package. In order to remove noise from high-frequency signals, it is effective to arrange electronic components such as capacitors and inductors, that is, passive components in the vicinity of the semiconductor chip.

The present inventors have devised a semiconductor package having a fan-out structure in which a passive component is covered with a mold resin together with a semiconductor chip from the viewpoint of achieving both mountability and improvement of electrical characteristics of the semiconductor package. Specifically, this semiconductor package includes a semiconductor chip and a passive component covered with one mold resin, and also includes a rewiring layer including a plurality of wires having one end connected to a terminal of the semiconductor chip. The part is connected to one electrode of the passive component.

However, as a result of diligent studies by the present inventors, this semiconductor package may have a small bonding area between the passive component and the wiring in the rewiring layer, resulting in insufficient bonding reliability. Further, since the passive component is covered with the mold resin together with the semiconductor chip, the number of wirings in the rewiring layer increases, and there is a concern that the degree of freedom in wiring arrangement is reduced.

In view of the above points, the first aspect of the present invention is to provide a semiconductor package having a fan-out structure in which a passive component is covered with a mold resin together with a semiconductor chip and the connection area between the rewiring and the passive component is increased. The purpose of. A second object of the present invention is to provide a semiconductor package having a fan-out structure having a high degree of freedom in wiring arrangement even if the number of wirings in the rewiring layer increases as compared with the conventional case.

In order to achieve the above object, the semiconductor package according to claim 1 is a semiconductor package having a fan-out structure, and is a semiconductor chip (1) having one side (1a) and having a plurality of terminals (11) on one side. ), A passive component (3) having a pair of electrodes (31, 32), and a mold resin (3) covering a portion of the semiconductor chip that is different from one surface and a portion of the passive component that is different from a portion of the pair of electrodes. A lower surface (2a) that includes 2) and a rewiring layer (4) that covers one surface of the semiconductor chip and includes a plurality of wirings (42), and forms one flat surface together with one surface of the semiconductor chip among the mold resins. Is formed with a recess (21) that exposes a part of the side surface (31b) connected to the bottom surface (31a, 32a) exposed from the mold resin on the lower surface side of the pair of electrodes. It has a passive component wiring (421) with one end connected to a terminal and the other end connected to one of a pair of electrodes, and the passive component wiring is partially shaped along a recess and Of the pair of electrodes, it covers a part of the bottom surface and side surfaces exposed from the mold resin.

As a result, a part of the bottom surface and the side surface of the electrode of the passive component is exposed from the mold resin, and the wiring in the rewiring layer for the passive component that connects the semiconductor chip and the passive component is the electrode of the passive component. It is a semiconductor package with a fan-out structure that is connected to the bottom and side surfaces. Since the wiring for the passive component is connected not only to the bottom surface of the electrode of the passive component but also to a part of the side surface, the connection area of these is increased, and the connection reliability is high.

The semiconductor package according to claim 6 is a semiconductor package having a fan-out structure, and is paired with a semiconductor chip (1) having one surface (1a) and having a plurality of terminals (11) on one surface side. A passive component (3) provided with electrodes (31, 32), a mold resin (2) covering a portion of the semiconductor chip different from one surface, and a portion of the passive component different from a part of a pair of electrodes, and a semiconductor. A plurality of rewiring layers (4) that cover one surface of the chip and are provided with a plurality of wirings (42), and one flat surface of the mold resin that forms one flat surface with one surface of the semiconductor chip as a lower surface (2a). Some of the wirings in the above are thick film portions whose thickness in the normal direction with respect to the lower surface is partially thickened, and the thickness of the thick film portion in the plane parallel to the lower surface is the rest of the wiring. Smaller than the width.

As a result, the rewiring layer has a wiring having a thick film portion that is partially thickened, and the thick film portion can be narrower than other parts of the wiring having the thick film portion, and the number of wirings can be reduced. Even if the number increases, the semiconductor package will have a fan-out structure with a high degree of freedom in its arrangement.

The reference numerals in parentheses attached to each component or the like indicate an example of the correspondence between the component or the like and the specific component or the like described in the embodiment described later.

It is sectional drawing which shows the semiconductor package of 1st Embodiment. It is a top view which shows the appearance of the semiconductor package of FIG. 1 seen from the rewiring layer side. It is an enlarged cross-sectional view which shows by enlarging the region shown by the broken line of FIG. It is a figure which shows the process of temporary fixing of a semiconductor package and a passive component in the manufacturing process of the semiconductor package of FIG. It is a figure which shows the process following FIG. 4A. It is a figure which shows the process following FIG. 4B. It is a figure which shows the process following FIG. 4C. It is a figure which shows the process following FIG. 4D. It is a figure which shows the process following FIG. 4E. It is a figure which shows the process following FIG. 4F. It is a figure which shows the process which follows FIG. 4G. It is a figure which shows the process following FIG. 4H. It is a top view which shows the state when the passive part was seen from the surface side exposed from the mold resin in the process of FIG. 4C. FIG. 5 is a cross-sectional view showing an example of a configuration corresponding to a cross section between VI and VI of FIG. 5 in which wiring is formed without forming a recess. It is sectional drawing which shows the semiconductor package of 2nd Embodiment. It is a top view which shows the appearance of the semiconductor package of FIG. 7 seen from the rewiring layer side. It is a top view which shows the appearance of the semiconductor package seen from the rewiring layer side, and shows the wiring example in the case where the wiring in a rewiring layer is not partially thickened. It is sectional drawing which shows an example of the semiconductor package which concerns on another embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, parts that are the same or equal to each other will be described with the same reference numerals.

(First Embodiment)
The semiconductor package P1 of the first embodiment will be described with reference to FIGS. 1 to 3.

In FIG. 1, in order to make the configuration easy to understand, the thickness and width of each component are exaggerated, and the cross-sectional configuration between I and I shown in FIG. 2 is shown. In FIG. 2, for easy viewing, a part of the components of the semiconductor package P1 that does not appear in the appearance is shown by a solid line, and the bump 5 described later is shown by a chain double-dashed line. Further, in FIG. 2, for the same purpose, the cross section is not shown, but the wiring 42 described later is hatched, and the portion covered by the wiring 42 is shown by a broken line.

(Constitution)
As shown in FIG. 1, the semiconductor package P1 of the present embodiment includes a semiconductor chip 1, a mold resin 2, a passive component 3, a rewiring layer 4, and a bump 5.

The semiconductor chip 1 is mainly made of a semiconductor material such as silicon, and is formed by a normal semiconductor process. The semiconductor chip 1 includes an integrated circuit (IC) (not shown), and is, for example, a switching element such as a MOSFET. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. As shown in FIG. 1, for example, the semiconductor chip 1 is covered with a mold resin 2 together with a passive component 3 described later, except for one side 1a. The semiconductor chip 1 has a rectangular plate shape having one surface 1a, and a plurality of terminals 11 are formed on the one surface 1a side.

The terminal 11 is made of a metal material such as Al (aluminum). As shown in FIG. 2, for example, the plurality of terminals 11 are arranged side by side so as to be separated from each other when viewed from the normal direction with respect to one surface 1a. The terminal 11 is connected to one end of the wiring 42 formed in the rewiring layer 4. The number, arrangement, dimensions, and the like of the plurality of terminals 12 may be appropriately changed.

The mold resin 2 is a sealing material that covers the semiconductor chip 1 and the passive component 3. The mold resin 2 is made of any resin material such as an epoxy resin.

Hereinafter, for the sake of simplification of the description, as shown in FIG. 1, the surface of the semiconductor chip 1 on the one side 1a side is referred to as "lower surface 2a", and the opposite surface is referred to as "upper surface 2b".

As shown in FIG. 3, for example, in the mold resin 2, a recess 21 recessed on the upper surface 2b side is formed in a part of the lower surface 2a. The recess 21 is formed so as to expose a part of the side surface 31b of the first electrode 31 located on the semiconductor chip 1 side of the passive component 3 from the mold resin 2.

The term "side surface 31b" as used herein refers to the surface of the first electrode 31, which forms a flat surface together with the lower surface 2a of the mold resin 2, as the "bottom surface 31a", and refers to the bottom surface 31a of the first electrode 31 and the opposite surface thereof. Refers to the surface that connects the.

The depth of the recess 21 is preferably within the range of 1/3 to 1/2 of the depth of the first electrode 31, for example, with the dimension in the normal direction with respect to the lower surface 2a as the depth. This is to improve the contact area between the wiring 421 and the side surface 31b of the first electrode 31, which will be described later, and to prevent a defect from occurring in the portion of the wiring 421 along the side surface 31b. The details will be described later. Further, the recess 21 may expose the side surfaces 31b and 32b to which the passive component wiring 421 is connected out of the pair of electrodes 31 and 32 of the passive component 3 described later from the mold resin 2, and the shape, dimensions and the like thereof may be exposed. Is optional.

The passive component 3 is, for example, an electronic component such as an inductor, a capacitor, and a resistor, and is sealed in the mold resin 2 together with the semiconductor chip 1. The passive component 3 has a pair of electrodes 31 and 32, and a part of the first electrode 31 and the second electrode 32 is exposed from the mold resin 2.

As shown in FIG. 3, a part of the bottom surface 31a and the side surface 31b of the first electrode 31 is exposed from the mold resin 2, and this exposed portion is covered with the wiring 421 described later. The first electrode 31 is electrically connected to the terminal 11 of the semiconductor chip 1 via the wiring 421.

The surface of the second electrode 32 on the same side as the bottom surface 31a of the first electrode 31 is exposed from the mold resin 2, and this exposed portion is covered with the wiring 42. The second electrode 32 is electrically connected to the bump 5 via the wiring 42.

As shown in FIG. 1, for example, the rewiring layer 4 includes a first insulating film 41, a plurality of wirings 42, and a second insulating film 43. The rewiring layer 4 is formed so as to cover the lower surface 2a side of the mold resin 2, and covers a part of the semiconductor chip 1 and the passive component 3 together with the lower surface 2a of the mold resin 2.

The first insulating film 41 and the second insulating film 43 are made of any insulating resin material such as polyimide, which is used in a normal rewiring step.

The wiring 42 is made of a conductive material used in a normal rewiring step, for example, a metal material such as Cu (copper), Ag (silver) or Au (gold). A plurality of wirings 42 are formed by, for example, electrolytic plating. As shown in FIG. 1, one end of the wiring 42 is connected to the terminal 11 or the second electrode 32 of the passive component 3. One end of the plurality of wires 42 is connected to the terminal 11, that is, the "chip wiring" has the other end connected to the passive component 3 or the bump 5. As shown in FIG. 2, for example, some of the wirings for chips 42 have the other end side extending to the outside of the outer shell of the semiconductor chip 1 in a plan view.

Hereinafter, for convenience of explanation, a part of the wiring 42 of the plurality of chip wirings, the other end of which is extended to the outside of the outer shell of the semiconductor chip 1 in a plan view, is referred to as “external extension wiring”. It is called. Further, as shown in FIG. 1, the external extension wiring that electrically connects the terminal 11 and the passive component 3 is referred to as "passive component wiring 421". Further, the wiring 42 of the rewiring layer 4 may also be referred to as “rewiring”.

The passive component wiring 421 is a wiring that electrically connects the terminal 11 of the semiconductor chip 1 and one of the pair of electrodes 31 and 32 of the passive component 3. As shown in FIG. 3, for example, a part of the passive component wiring 421 has a shape that follows a part of the first insulating film 41 that covers the recess 21 and a part of the side surface 31b of the first electrode 31. ing. In other words, the passive component wiring 421 is electrically connected to the portion of the side surface 31b of the first electrode 31 exposed from the mold resin 2 while having a partially recessed shape on the upper surface 2b side of the lower surface 2a. ing. As a result, the contact area between the passive component 3 and the wiring 42 connected to the passive component 3 can be increased as compared with the case where the rewiring layer 4 is formed without forming the recess 21 in the mold resin 2, and the joining reliability of these can be increased. The improvement effect of is obtained. The details will be described later.

The bump 5 is a joining member used when mounting the semiconductor package P1 on a wiring board or the like, and is, for example, solder. The bump 5 is formed by, for example, electroplating, mounting a solder ball, and reflowing.

The above is the basic configuration of the semiconductor package P1 of the present embodiment. That is, the semiconductor package P1 incorporates the passive component 3 together with the semiconductor chip 1, and is an external extension wiring extending to a part of a plurality of terminals 11 formed on the semiconductor chip 1 to the outside of the outer shell of the semiconductor chip 1. It has a fan-out structure to which is connected.

(Production method)
Next, an example of the method for manufacturing the semiconductor package P1 of the present embodiment will be described with reference to FIGS. 4A to 4I. Here, an example in which a plurality of semiconductor packages P1 are manufactured at one time will be described as a typical example, but the same is basically true even when the semiconductor packages P1 are manufactured in package units.

First, as shown in FIG. 4A, a plurality of semiconductor chips 1 and passive components 3 are prepared, and these are attached to predetermined positions on the holding substrate 100. The holding substrate 100 may be any substrate made of, for example, a silicon resin, as long as it can temporarily hold the semiconductor chip 1 and the passive component 3 until the molding of the mold resin 2 is completed.

Subsequently, a mold (not shown) having a cavity along the outer shape of the mold resin 2 is prepared, and the work shown in FIG. 4A is set. Then, the resin material constituting the mold resin 2 is put into the cavity, heated and cured to mold the mold resin 2. Then, when the work is released from a mold (not shown), the mold resin 2 covering the semiconductor chip 1 and the passive component 3 can be molded as shown in FIG. 4B. Then, as shown in FIG. 4C, the holding substrate 100 is peeled off.

Next, as shown in FIG. 4D, a recess 21 is formed in a portion of the lower surface 2a of the mold resin 2 located near the first electrode 31 of the passive component 3 by irradiating a laser beam or the like, and the first electrode 31 is formed. A part of the side surface 31b of the above is exposed.

The depth of the recess 21 at this time is preferably about 1/3 to 1/2 of the height of the first electrode 31. This is to improve the joint reliability between the passive component wiring 421 and the passive component 3 while suppressing the occurrence of defects such as cracks in the passive component wiring 421. Specifically, if the depth of the recess 21 is too shallow, the exposed area of the side surface 31b becomes small, so that the contact area between the passive component wiring 421 and the side surface 31b becomes small, and the effect of improving the joint strength between them is obtained. Not enough. On the contrary, if the depth of the recess 21 is too deep, a large step is generated in the passive component wiring 421 formed along the side surface 31b, and defects such as cracks are likely to occur.

Then, a solution containing, for example, a photosensitive insulating material is formed on the lower surface 2a side of the mold resin 2 of the work shown in FIG. 4D by a wet process such as spin coating, and then dried to remove the solvent. Form an insulating film. Then, a portion of the insulating film covering the electrodes 31 and 32 of the passive component 3 and a portion covering the terminal 11 of the semiconductor chip 1 are removed by a photolithography etching method using a mask (not shown), and as shown in FIG. 4E, The first insulating film 41 is formed.

Subsequently, as shown in FIG. 4F, the terminal 11, the first electrode 31, the second electrode 32, and the wiring 42 surrounding them are formed. Specifically, for example, after forming a seed layer (not shown) made of Cu or the like by sputtering, an insulating mask (not shown) that covers only a portion where the wiring 42 is not formed by a photolithography etching method like the first insulating film 41. To form. After that, a wiring 42 made of Cu is formed in a portion of the seed layer (not shown) exposed from the mask by electrolytic plating. Then, after removing the mask (not shown) with the stripping solution, the portion of the seed layer (not shown) exposed from the wiring 42 is removed with an etching solution or the like. For example, by the above process, the work is in the state shown in FIG. 4F.

Next, as shown in FIG. 4G, a second insulating film 43 that covers a part of the first insulating film 41 and the wiring 42 is formed by the same process as that of the first insulating film 41. The second insulating film 43 is formed so as to cover all of the passive component wiring 421 and other wirings 42 other than the portion where the bump 5 is formed.

Then, for example, as shown in FIG. 4H, a ball made of solder is placed in each portion of the wiring 42 exposed from the second insulating film 43, melted by a reflow process, and cured again by a ball mounting method or the like. , Bump 5 is formed.

Finally, as shown in FIG. 4I, the semiconductor package P1 of the present embodiment can be manufactured by dividing into package units by dicing cut.

(effect)
Next, the effect of the semiconductor package P1 of the present embodiment will be described.

When the work after the process of FIG. 4C is viewed from the lower surface 2a side of the mold resin 2, the work has a part of the bottom surfaces of the electrodes 31 and 32 of the passive parts 3 from the mold resin 2, as shown in FIG. 5, for example. It is in an exposed state.

Specifically, as shown in FIG. 6, the bottom surfaces of the first electrode 31 and the second electrode 32 of the passive component 3 are not flat surfaces in cross-sectional view, and some of them have a curved surface shape. It has become. Therefore, when the mold resin 2 is molded with the passive component 3 temporarily fixed to the holding substrate 100, only a part of the bottom surfaces of the electrodes 31 and 32 is exposed from the mold resin 2. That is, the exposed area of the first electrode 31 from the mold resin 2 becomes small.

Here, as shown in FIG. 6, the rewiring layer is formed without going through the process of forming the recess 21 shown in FIG. 4D, that is, without considering the curved surface shape of the bottom surfaces of the electrodes 31 and 32 of the passive component 3. Consider the case.

In FIG. 6, the wiring formed in the temporary process is shown as "wiring X" in order to distinguish it from the rewiring layer 4 and the wiring 421.

When the rewiring layer is formed without forming the recess 21, the wiring X is in contact with only a part of the bottom surface 31a of the first electrode 31 as shown in FIG. Therefore, the contact area between the wiring X and the first electrode 31 is small, which may reduce the joining reliability.

On the other hand, as shown in FIG. 3, the semiconductor package P1 of the present embodiment has a configuration in which a recess 21 is formed in a portion of the mold resin 2 in contact with the passive component 3. As a result, the region of the first electrode 31 from the bottom surface 31a to a part of the side surface 31b is exposed from the mold resin 2, and the exposed area of the first electrode 31 from the mold resin 2 is large. Further, since the passive component wiring 421 covers the exposed portions on the bottom surface 31a and the side surface 31b of the first electrode 31, the contact area between the first electrode 31 and the passive component wiring 421 is increased, and the joining reliability is improved. To do.

According to this embodiment, a semiconductor package having a fan-out structure in which the passive component 3 is covered with the mold resin 2 together with the semiconductor chip 1 and the bonding area between the wiring 42 of the rewiring layer 4 and the passive component 3 is increased. Become. As a result, the distance between the semiconductor chip 1 and the passive component 3 is reduced, so that noise in the transmission of high-frequency signals is efficiently suppressed, the electrical characteristics are improved, and the connection reliability between the wiring 42 and the passive component 3 is improved. Is an enhanced semiconductor package P1.

(Second Embodiment)
The semiconductor package P2 of the second embodiment will be described with reference to FIGS. 7 and 8.

In FIG. 8, as in FIG. 2, a part of the components of the semiconductor package P2 that do not appear in the appearance is shown by a solid line, and the bump 5 is shown by a chain double-dashed line. Further, in FIG. 8, for the same purpose, the cross section is not shown, but the passive component wiring 421 and the other wiring 422 are hatched, and the portion covered by the wiring 42 is shown by a broken line.

The semiconductor package P2 of the present embodiment is different from the first embodiment in that the joint portion of the passive component 3 with the first electrode 31 of the passive component wiring 421 is partially thickened. In this embodiment, this difference will be mainly described.

In the present embodiment, as shown in FIG. 7, the joint portion of the first electrode 31 with the bottom surface 31a and the side surface 31b of the passive component wiring 421 is thicker than the other portion of the wiring in the cross-sectional view. Has been done. As a result, the inductance of the wiring 421 for passive components becomes smaller than that of the first embodiment, and the semiconductor package P2 has a configuration capable of suppressing noise generation of a higher frequency signal.

The manufacturing method of the semiconductor package P2 is basically the same as that of the semiconductor package P1 of the first embodiment, but the process of forming the wiring 42 is partially different. Specifically, after the step shown in FIG. 4F, a pattern mask (not shown) covering a part of the formed wiring 421 for passive parts other than the thickened part is formed by a photolithography etching method. After that, the rest of the passive component wiring 421 is laminated by electrolytic plating on the portion exposed from the pattern mask (not shown). After that, by removing the pattern mask (not shown) with a stripping solution or the like, a partially thickened passive component wiring 421 can be formed. After that, the semiconductor package P2 can be manufactured by sequentially performing the steps shown in FIGS. 4G to 4I.

In the above description, the configuration in which the passive component wiring 421 is partially thickened has been described, but similarly, the wiring 42 of the rewiring layer 4 different from the passive component wiring 421 is also partially thickened. The film may be thickened.

For example, as shown in FIG. 8, the wiring 42 different from the wiring 421 for passive components, and the wiring 422 connecting the terminal 11 of the semiconductor chip 1 and the bump 5 has a thickness in the normal direction with respect to the lower surface 2a. It may be a thick film portion that is thickened. As shown in FIG. 8, the wiring 422 has a structure in which the width of the thick film portion of the wiring 422 in the plane parallel to the lower surface 2a is smaller than the width of the remaining portion of the wiring 422 when viewed in a plan view.

As a result, the wiring 422 is partially thickened so that the width of the thick film portion is made smaller than that of the other portions, but the inductance of the entire wiring 422 is kept small. Further, by narrowing the width of the wiring 422, the semiconductor package P2 has a high degree of freedom in its arrangement.

Specifically, when the wiring 422 is not partially thickened, as shown in FIG. 9, the wiring 422 needs to have a wiring width of a predetermined value or more when viewed in a plan view so that its inductance does not increase. There is. In this case, the arrangement of the wiring 422 is limited by the wiring width, and the distance connecting the terminal 11 to the bump 5 in a plan view becomes longer than necessary, which may result in an increase in inductance. Therefore, the wiring 42 other than the wiring 421 for the passive component may also have a partially thickened structure.

According to the present embodiment, in addition to the effect of the first embodiment, the wiring 421 for passive components is partially thickened, so that the inductance of the wiring is small, noise can be easily removed, and more electricity can be obtained. The effect of improving the characteristics can be obtained. Further, when a plurality of wirings 42 different from the wirings 421 for passive components are partially thickened, the wirings 42 are compared with the semiconductor package of the first embodiment or the conventional fan-out structure. The semiconductor package P2 has a high degree of freedom.

(Other embodiments)
Although the present invention has been described in accordance with Examples, it is understood that the present invention is not limited to the Examples and structures. The present invention also includes various modifications and modifications within a uniform range. In addition, various combinations and forms, as well as other combinations and forms including only one element thereof, more or less, are also within the scope and ideology of the present invention.

In each of the above embodiments, the configuration in which one semiconductor chip 1 and one passive component 3 are covered with the mold resin 2 has been described, but the present invention is not limited to this. For example, as shown in FIG. 10, a semiconductor package P3 having a structure in which one semiconductor chip 1 and a plurality of passive components 3 are covered with a mold resin 2 may be formed.

In this case, for example, the rewiring layer 4 is configured to have a passive component wiring 423 that electrically connects the two passive components 3. Further, the mold resin 2 is configured to have a recess 21 formed in the passive component 3 to expose a part of the side surface of the electrode other than the electrode connected to the bump 5. In other words, in this case, the recess 21 is formed in a portion of the lower surface 2a of the mold resin 2 adjacent to the side surfaces 31b, 32b of the electrodes 31, 32 of the passive component 3 to which the passive component wiring 423 is connected. Part of the side surface is exposed. As a result, even if the configuration includes a plurality of passive components 3, the semiconductor package P3 has high connection reliability between the wiring 42 in the rewiring layer 4 and the passive components 3.

1 ... Semiconductor chip, 1a ... One side, 11 ... Terminal, 2 ... Mold resin,
2a ... bottom surface, 21 ... recessed part, 3 ... passive component, 31, 32 ... pair of electrodes,
31a, 32a ... bottom surface, 31b ... side surface, 4 ... rewiring layer, 42 ... wiring,
421 ... Wiring for passive components 423 ... Wiring between passive components

Claims (6)

It is a semiconductor package with a fan-out structure.
A semiconductor chip (1) having one surface (1a) and having a plurality of terminals (11) on the one surface side.
A passive component (3) with a pair of electrodes (31, 32) and
A mold resin (2) that covers a portion of the semiconductor chip that is different from the one surface and a portion of the passive component that is different from a portion of the pair of electrodes.
A rewiring layer (4) that covers the one side of the semiconductor chip and includes a plurality of wirings (42) is provided.
The lower surface (2a) of the mold resin forming one flat surface together with the one surface of the semiconductor chip is connected to the bottom surfaces (31a, 32a) exposed from the mold resin on the lower surface side of the pair of electrodes. A recess (21) is formed to expose a part of the side surface (31b).
The plurality of wirings have a passive component wiring (421) having one end connected to the terminal and the other end connected to one of the pair of electrodes.
A semiconductor package in which a part of the wiring for a passive component is shaped along the recess and covers a part of the bottom surface and the side surface of the pair of electrodes exposed from the mold resin. The semiconductor package according to claim 1, wherein the passive component wiring has a portion of the pair of electrodes in contact with a part of the side surface thereof, which is thicker than the other portion of the passive component wiring. The semiconductor package according to claim 1 or 2, wherein the number of passive components is 2 or more. The rewiring layer comprises passive inter-component wiring (423) that electrically connects the two passive components.
The recess is also formed in a portion of the lower surface of the mold resin adjacent to the side surface of the electrode of the passive component to which the wiring between the passive components is connected.
The semiconductor package according to claim 3, wherein the passive component wiring is partially shaped along the recess. A part of the wiring different from the wiring for the passive component among the plurality of wirings is a thick film portion having a partially thickened thickness in the normal direction with respect to the lower surface.
The semiconductor package according to any one of claims 1 to 4, wherein the thick film portion has a width in a plane parallel to the lower surface smaller than the width of the remaining portion of the wiring having the thick film portion. It is a semiconductor package with a fan-out structure.
A semiconductor chip (1) having one surface (1a) and having a plurality of terminals (11) on the one surface side.
A passive component (3) with a pair of electrodes (31, 32) and
A mold resin (2) that covers a portion of the semiconductor chip that is different from the one surface and a portion of the passive component that is different from a portion of the pair of electrodes.
A rewiring layer (4) that covers the one side of the semiconductor chip and includes a plurality of wirings (42) is provided.
A surface of the mold resin that forms one flat surface together with the one surface of the semiconductor chip is defined as a lower surface (2a), and some of the wirings among the plurality of wirings have a partial thickness in the normal direction with respect to the lower surface. It has a thickened film part,
The thick film portion is a semiconductor package in which the width of the plane parallel to the lower surface is smaller than the width of the remaining portion of the wiring having the thick film portion.

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