JP4168494B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4168494B2
JP4168494B2 JP27245598A JP27245598A JP4168494B2 JP 4168494 B2 JP4168494 B2 JP 4168494B2 JP 27245598 A JP27245598 A JP 27245598A JP 27245598 A JP27245598 A JP 27245598A JP 4168494 B2 JP4168494 B2 JP 4168494B2
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Prior art keywords
wiring
insulating film
forming
connection pad
silicon substrate
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JP2000091496A (en
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昭一 児谷
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers

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  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase mounting density in the mounting technology for semiconductor chips which is referred to as MCM(multichip module). SOLUTION: Wirings 22, 25 formed on the upper surface of a silicon substrate 12 of a semiconductor package 11, which is referred to as CSP(chip size package) is connected through a connecting part 27 formed on the side face of the silicon substrate 12 and wiring 18 formed on the lower surface of the silicon substrate 12, with a columnar electrode 19 formed beneath the silicon substrate 12. A bare chip 31 is mounted on the semiconductor package 11. The semiconductor package 11 is mounted on a wiring board 41 through anisotropic conductive adhesive 51. According to this structure, the bare chip 31 and the semiconductor package 11 can be mounted three-dimensionally on a wiring board 41.

Description

【０００１】
【発明の属する技術分野】
この発明は半導体装置及びその製造方法に関する。
【０００２】
【従来の技術】
例えば、ＭＣＭ(multi chip module)と呼ばれる半導体チップの実装技術では、ベアチップやＣＳＰ(chip size package)と呼ばれる半導体パッケージ等を配線基板上に搭載することがある。また、同配線基板上に抵抗やコンデンサ等のチップ部品を搭載することもある。
【０００３】
【発明が解決しようとする課題】
しかしながら、従来のこのような実装技術では、配線基板上にベアチップ等の各種電子部品を平面的に配置しているので、実装密度に限界があるという問題があった。
この発明の課題は、実装密度を高くすることである。
【０００４】
【課題を解決するための手段】
請求項１記載の発明に係る半導体装置の製造方法は、ウエハの一の面上に形成された絶縁膜に形成された開口部を介して露出された接続パッド上から前記絶縁膜上にかけて接続パッド部を有する第１の配線を形成するとともに、ダイシングストリートの部分における前記絶縁膜上から前記絶縁膜上の他の部分にかけてッド部上に第１及び第２の柱状電極を形成する工程と、前記第１及び第２の柱状電極を除く前記絶縁膜上に封止膜を形成する工程と、前記ウエハの他の面上に第３の配線を形成する工程と、前記第３の配線形成後に、前記封止膜の下面を本研磨し、第２の柱状電極の下端面を露出させる工程と、前記ウエハのダイシングストリートの部分に貫通孔を形成して該貫通孔内に前記第２の配線と前記第３の配線とを接続する接続部を形成する工程と、前記ウエハ等をダイシングして複数の半導体装置を得る工程とを具備するものである。請求項２記載の発明に係る半導体装置の製造方法は、請求項１記載の発明において、ダイシング後に、前記ウエハの他の面上に電子部品を前記第３の配線に接続させて搭載するようにしたものである。そして、請求項１記載の発明によれば、ウエハの他の面上に配線を形成しているので、請求項２記載の発明のように、ウエハの他の面上に電子部品を搭載することができ、したがってウエハ及び該ウエハの他の面上に搭載された電子部品を配線基板上に立体的に搭載することができ、ひいては実装密度を高くすることができる。また、他面側の配線形成後に、封止膜の下面を研磨し、柱状電極の下端面を露出させているので、柱状電極の下端面が封止膜で保護されており傷むことがないので、半田ボールを接合しやすくすることができる。
【０００５】
【発明の実施の形態】
図１及び図２はこの発明の一実施形態における半導体装置の実装構造の各断面図を示したものである。この実施形態における半導体装置１は、半導体パッケージ（ＣＳＰ）１１上にベアチップ３１が搭載されたものからなり、配線基板４１上に異方導電性接着剤５１を介して搭載されている。そして、図１は主として半導体パッケージ１１用の第１の柱状電極１７の部分の断面図を示し、図２は主としてベアチップ３１用の第２の柱状電極１９の部分の断面図を示す。
【０００６】
まず、図１を参照して説明する。半導体パッケージ１１は平面方形状のシリコン基板（半導体基板）１２を備えている。シリコン基板１２の下面の外周部には複数の接続パッド１３が形成されている。接続パッド１３の中央部を除くシリコン基板１２の下面全体には絶縁膜１４が形成され、接続パッド１３の中央部が絶縁膜１４に形成された開口部１５を介して露出されている。この露出された接続パッド１３の下面から絶縁膜１４の下面の所定の箇所にかけて２層構造の第１の配線１６が形成されている。この場合、第１の配線１６は、接続パッド１３下に形成された接続部１６ａと、絶縁膜１４の下面の所定の箇所に形成された接続パッド部１６ｂと、その間に形成された引き回し線１６ｃとからなっている。接続パッド部１６ｂの下面には第１の柱状電極１７が形成されている。
【０００７】
次に、主として図２を参照して説明する。絶縁膜１４の下面端部から絶縁膜１４の下面の他の所定の箇所にかけて２層構造の第２の配線１８が形成されている。この場合、第２の配線１８は、絶縁膜１４の下面の他の所定の箇所に形成された接続パッド部１８ａと、この接続パッド部１８ａから絶縁膜１４の下面端部まで延びる引き回し線１８ｂとからなっている。接続パッド部１８ａの下面には第２の柱状電極１９が形成されている。そして、第１及び第２の柱状電極１７、１９を除く絶縁膜１４の下面全体には封止膜２０が形成されている。この場合、第１及び第２の柱状電極１７、１９の下端面は、封止膜２０の下面と同一平面とされ、露出されている。
【０００８】
シリコン基板１２の上面には第１の絶縁膜２１が形成されている。第１の絶縁膜２１の上面には第３の配線２２が形成されている。この場合、第３の配線２２は、第１の絶縁膜２１の上面の所定の箇所に形成された接続パッド部２２ａと、この接続パッド部２２ａから第１の絶縁膜２１の上面端部まで延びる引き回し線２２ｂとからなっている。接続パッド部２２ａの中央部を除く第１の絶縁膜２１の上面全体には第２の絶縁膜２３が形成され、接続パッド部２２ａの中央部が第２の絶縁膜２３に形成された開口部２４を介して露出されている。この露出された接続パッド２２ａの上面から第２の絶縁膜２３の上面の所定の箇所にかけて第４の配線２５が形成されている。この場合、第４の配線２５は、接続パッド２２ａ上に形成された接続部２５ａと、第２の絶縁膜２３の上面の所定の箇所に形成された接続パッド部２５ｂと、その間に形成された引き回し線２５ｃとからなっている。
【０００９】
シリコン基板１２の側面の所定の箇所には平面ほぼ半円形状の溝２６が上下方向に延びて形成されている。溝２６内には接続部２７が形成されている。この接続部２７の下端部は第２の配線１８の引き回し線１８ｂの先端部に接続され、上端部は第３の配線２２の引き回し線２２ｂの先端部に接続されている。これにより、第４の配線２５は、第３の配線２２、接続部２７及び第２の配線１８を介して第２の柱状電極１９に接続されている。なお、接続部２７を含む溝２６の部分は前述の封止膜２０によって覆われている。
【００１０】
ベアチップ３１は平面方形状のシリコン基板３２を備えている。この場合、シリコン基板３２の平面サイズは半導体パッケージ１１のシリコン基板１２の平面サイズよりも適宜に小さくなっている。シリコン基板３２の下面の外周部には複数の柱状電極３３が形成されている。配線基板４１は、ガラスエポキシ等からなる基板４２の上面に第１及び第２の接続パッド４３、４４を含む配線（図示せず）が形成されたものからなっている。この場合、第１の接続パッド４３は半導体パッケージ１１用のものであり、第２の接続パッド４４はベアチップ３１用のものである。異方導電性接着剤５１は、絶縁性接着剤５２中に導電性粒子５３をほぼ均一に混入したものからなっている。
【００１１】
そして、ベアチップ３１の柱状電極３３が半導体パッケージ１１の第４の配線２５の接続パッド２５ａにボンディングされていることにより、ベアチップ３１は半導体パッケージ１１上に搭載され、これにより半導体装置１が構成されている。また、半導体パッケージ１１の第１及び第２の柱状電極１７、１９の下端面を含む封止膜２０の下面が配線基板４１の接続パッド４３、４４の部分に異方導電性接着剤５１を介して接合されていることにより、半導体装置１は配線基板４１上に搭載されている。この状態では、第１及び第２の柱状電極１７、１９の各下端面は導電性粒子５３を介して配線基板４１の第１及び第２の接続パッド４３、４４に接続されている。これにより、ベアチップ３１の柱状電極３３は、第４の配線２５、第３の配線２２、接続部２７、第２の配線１８、第２の柱状電極１９及び導電性粒子５３を介して配線基板４１の第２の接続パッド４４に接続されている。
【００１２】
このように、この半導体装置の実装構造では、ベアチップ３１を半導体パッケージ１１上に搭載して半導体装置１を構成し、この半導体装置１を配線基板４１上に搭載しているので、ベアチップ３１及び半導体パッケージ１１を配線基板４１上に立体的に搭載することができ、したがって実装密度を高くすることができる。
【００１３】
次に、半導体パッケージ１１の製造方法の一例について、図３〜図１６を順に参照して説明する。なお、図１に示す第１の配線１６及び第１の柱状電極１７の形成は、図２に示す第２の配線１８及び第２の柱状電極１９の形成と同時に形成されるので、第１の配線１６及び第１の柱状電極１７の形成については省略する。さて、まず図３に示すように、ウエハ状態のシリコン基板１２の下面に接続パッド１３が形成されたものを用意する。この場合、シリコン基板１２の下面の接続パッド１３の中央部を除く部分にパッシベーション膜が形成されていてもよい。なお、図３において符合６１で示す領域はダイシングストリートである。
【００１４】
次に、図４に示すように、シリコン基板１２の下面全体にポリイミド等からなる絶縁膜１４を形成し、次いでこの絶縁膜１４に図１に示す開口部１５を形成する。次に、開口部１５を含む絶縁膜１４の下面全体に下地金属層６２を形成する。次に、下地金属層６２の下面において図２に示す第２の配線１８及び溝２６を形成すべき領域を除く部分にメッキレジスト層６３を形成する。次に、下地金属層６２をメッキ電流路として金等の電解メッキを行うことにより、下地金属層６２の下面において図２に示す第２の配線１８及び溝２６を形成すべき領域にメッキ層６４を形成する。この後、メッキレジスト層６３を剥離する。
【００１５】
次に、図５に示すように、シリコン基板１２の上面全体にポリイミド等からなる第１の絶縁膜２１を形成する。次に、図６に示すように、ダイシングストリート６１の所定の複数箇所に対応する部分におけるシリコン基板１２等に平面ほぼ円形状の貫通孔（図２の溝２６に相当するもの）２６をウェットエッチング、ドライエッチング、レーザの照射等により形成する。この場合、貫通孔２６内に露出されたシリコン基板１２の壁面に自然酸化膜からなる絶縁膜（図示せず）が形成される。この絶縁膜の膜厚が薄すぎる場合には、加熱処理により、この絶縁膜の膜厚を厚くするようにしてもよい。
【００１６】
次に、図７に示すように、スパッタにより、第１の絶縁膜２１の上面及び貫通孔２６の内壁面に銅等からなる金属膜６５を形成する。この状態では、貫通孔２６内に形成された金属膜６５の下端部は下地金属層６２及びメッキ層６４に接続されている。なお、貫通孔２６内に形成された金属膜６５の導電性に問題があるような場合には、貫通孔２６内に導電ペーストを充填するようにしてもよい。また、貫通孔２６内に形成する金属膜６５をスルーホールメッキ処理により形成するようにしてもよい。
【００１７】
次に、図８に示すように、シリコン基板１２の下面側にドライフィルムレジスト６６をラミネートし、次いでこのドライフィルムレジスト６６の図２における第２の配線１８の接続パッド部１８ａに対応する部分に開口部６７を形成する。次に、下地金属層６２をメッキ電流路として金等の電解メッキを行うことにより、開口部６７内におけるメッキ層６４下に第２の柱状電極１９を形成する。次に、ドライフィルムレジスト６６を剥離すると、図９に示すようになる。次に、メッキ層６４をマスクとして下地金属層６２をエッチングすると、図１０に示すように、２層構造の第２の配線１８が形成される。
【００１８】
次に、図１１に示すように、シリコン基板１２の下面側及び貫通孔２６内にエポキシ樹脂等からなる封止膜２０を形成する。この場合、第２の柱状電極１９を完全に覆うように、封止膜２０の膜厚をある程度厚くし、次いで封止膜２０の下面を仮研磨して平坦化する。この平坦化は後の工程を容易とするためである。また、この平坦化した状態でも、第２の柱状電極１９の下端面は封止膜２０によって覆われている。これは、後の工程において第２の柱状電極１９の下端面を保護するためである。次に、金属膜６５の上面において図２に示す第３の配線２２を形成すべき領域及び貫通孔２６の部分にレジスト層６８を形成する。次に、レジスト層６８をマスクとして金属膜６５をエッチングすると、図１２に示すように、第３の配線２２及び接続部２７が形成される。この後、レジスト層６８を剥離する。
【００１９】
次に、図１３に示すように、シリコン基板１２の上面側にポリイミド等からなる第２の絶縁膜２３を形成し、次いでこの第２の絶縁膜２３に図１に示す開口部２４を形成する。次に、図１４に示すように、開口部２４を含む第２の絶縁膜２３の上面全体に銅等からなる金属膜６９を形成する。次に、金属膜６９の上面において図２に示す第４の配線２５を形成すべき領域にレジスト層７０を形成する。次に、レジスト層７０をマスクとして金属膜６９をエッチングすると、図１５に示すように、第４の配線２５が形成される。この後、レジスト層７０を剥離する。次に、図１６に示すように、封止膜２０の下面を本研磨し、第２の柱状電極１９の下端面を露出させる。次に、ダイシングストリート６１の中央部でダイシングすると、図１及び図２に示す半導体パッケージ１１が得られる。
【００２０】
なお、上記実施形態では、例えば図２に示すように、第２の柱状電極１９と配線基板４１の第２の接続パッド４４とを異方導電性接着剤５１の導電性粒子５３を介して接続した場合について説明したが、これに限らず、例えば図１７に示すように、第２の接続パッド４４上または第２の柱状電極１９下に予め設けられた半田ボール７１を介して接続するようにしてもよい。また、上記実施形態では、例えば図２に示すように、第４の配線２５をむき出しとした場合について説明したが、これに限らず、例えば図１７に示すように、レジスト等からなる保護膜７２によって覆うようにしてもよい。また、上記実施形態では、半導体パッケージ１１用の第１の柱状電極１７とベアチップ３１用の第２の柱状電極１９とを別々とした場合について説明したが、これに限らず、例えば電源やグランド用の第２の配線１８を同じく電源やグランド用の第１の配線１６に接続し、電源やグランド用の第１の柱状電極１７を共有化するようにしてもよい。さらに、上記実施形態では、半導体パッケージ１１上に１個のベアチップ３１を搭載した場合について説明したが、これに限らず、複数個のベアチップ３１や他のチップ部品を搭載するようにしてもよい。この場合、例えば図１７に示すように、シリコン基板１２上の中央部に第３及び第４の配線２２ａ、２５ａを適宜に形成するようにしてもよい。
【００２１】
また、第２の配線１８及び第２の柱状電極１９を形成せずに、例えば図１８に示すようにしてもよい。すなわち、シリコン基板１２及び封止膜２０等の側面に溝２６を形成し、この溝２６内に導電ペースト等からなる接続部２７を第３の配線２２に接続させて形成し、この接続部２７の下端面を配線基板４１の第２の接続パッド４４に異方導電性接着剤５１の導電性粒子５３を介して接続するようにしてもよい。なお、この場合も、例えば電源やグランド用の第２の配線１８及び第２の柱状電極１９のみを形成し、電源やグランド用の第１の柱状電極１７を共有化するようにしてもよい。加えて、シリコン基板１２の上面側に形成する配線は、第３と第４の配線２２、２５からなる２層構造に限ることなく、単層構造あるいは３層以上の構造としてもよい。また、第１の配線１６は、場合によっては下地金属層のみによって形成するようにしてもよい。さらに、接続部２７等を形成せずに、シリコン基板１２の上面側に形成された配線を配線基板４１の第２の接続パッド４４にワイヤボンディングにより接続するようにしてもよい。
【００２２】
【発明の効果】
以上説明したように、この発明によれば、半導体基板の他の面上に配線を形成しているので、半導体基板の他の面上に電子部品を搭載することができ、したがって半導体基板及び該半導体基板の他の面上に搭載された電子部品を配線基板上に立体的に搭載することができ、ひいては実装密度を高くすることができる。
【図面の簡単な説明】
【図１】この発明の一実施形態における半導体装置の実装構造の主として半導体パッケージ用の第１の柱状電極の部分の断面図。
【図２】同実装構造の主としてベアチップ用の第２の柱状電極の部分の断面図。
【図３】図１及び図２に示す半導体パッケージの製造に際し、当初用意したものの一部の断面図。
【図４】図３に続く製造工程の断面図。
【図５】図４に続く製造工程の断面図。
【図６】図５に続く製造工程の断面図。
【図７】図６に続く製造工程の断面図。
【図８】図７に続く製造工程の断面図。
【図９】図８に続く製造工程の断面図。
【図１０】図９に続く製造工程の断面図。
【図１１】図１０に続く製造工程の断面図。
【図１２】図１１に続く製造工程の断面図。
【図１３】図１２に続く製造工程の断面図。
【図１４】図１３に続く製造工程の断面図。
【図１５】図１４に続く製造工程の断面図。
【図１６】図１５に続く製造工程の断面図。
【図１７】この発明の他の実施形態における半導体装置の実装構造の要部の断面図。
【図１８】この発明のさらに他の実施形態における半導体装置の実装構造の要部の断面図。
【符号の説明】
１ 半導体装置
１１ 半導体パッケージ
１６ 第１の配線
１７ 第１の柱状電極
１８ 第２の配線
１９ 第２の柱状電極
２２ 第３の配線
２５ 第４の配線
２７ 接続部
３１ ベアチップ
４１ 配線基板
５１ 異方導電性接着剤[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
For example, in a semiconductor chip mounting technique called an MCM (multi chip module), a semiconductor package called a bare chip or a CSP (chip size package) may be mounted on a wiring board. In addition, chip parts such as resistors and capacitors may be mounted on the same wiring board.
[0003]
[Problems to be solved by the invention]
However, such conventional mounting technology has a problem in that the mounting density is limited because various electronic components such as bare chips are arranged in a plane on the wiring board.
An object of the present invention is to increase the mounting density.
[0004]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a connection pad extending from a connection pad exposed through an opening formed in an insulating film formed on one surface of a wafer to the insulating film; Forming a first wiring having a portion and forming first and second columnar electrodes on the pad portion from the insulating film in the dicing street portion to another portion on the insulating film; Forming a sealing film on the insulating film excluding the first and second columnar electrodes, forming a third wiring on the other surface of the wafer, and after forming the third wiring A step of polishing the lower surface of the sealing film to expose a lower end surface of the second columnar electrode, and forming a through hole in a dicing street portion of the wafer to form the second wiring in the through hole. And a connecting portion for connecting the third wiring A step of forming, in which includes the step of obtaining a plurality of semiconductor devices by dicing the wafer and the like. According to a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the first aspect of the invention, wherein after dicing, an electronic component is mounted on the other surface of the wafer by being connected to the third wiring. It is a thing. Then, according to the invention described in claim 1, since the wiring is formed on the other surface of the wafer, as in the invention of claim 2, mounting the electronic component on the other surface of the wafer Therefore, the wafer and electronic components mounted on the other surface of the wafer can be three-dimensionally mounted on the wiring board, and the mounting density can be increased. In addition, after forming the wiring on the other surface side, the lower surface of the sealing film is polished and the lower end surface of the columnar electrode is exposed. , Solder balls can be easily joined.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
1 and 2 show cross-sectional views of a semiconductor device mounting structure according to an embodiment of the present invention. The semiconductor device 1 in this embodiment is configured by mounting a bare chip 31 on a semiconductor package (CSP) 11 and mounted on a wiring substrate 41 via an anisotropic conductive adhesive 51. 1 mainly shows a cross-sectional view of a portion of the first columnar electrode 17 for the semiconductor package 11, and FIG. 2 shows a cross-sectional view of a portion of the second columnar electrode 19 for the bare chip 31 mainly.
[0006]
First, a description will be given with reference to FIG. The semiconductor package 11 includes a planar rectangular silicon substrate (semiconductor substrate) 12. A plurality of connection pads 13 are formed on the outer peripheral portion of the lower surface of the silicon substrate 12. An insulating film 14 is formed on the entire lower surface of the silicon substrate 12 except for the central portion of the connection pad 13, and the central portion of the connection pad 13 is exposed through an opening 15 formed in the insulating film 14. A first wiring 16 having a two-layer structure is formed from the exposed lower surface of the connection pad 13 to a predetermined position on the lower surface of the insulating film 14. In this case, the first wiring 16 includes a connection portion 16a formed under the connection pad 13, a connection pad portion 16b formed at a predetermined position on the lower surface of the insulating film 14, and a lead line 16c formed therebetween. It is made up of. A first columnar electrode 17 is formed on the lower surface of the connection pad portion 16b.
[0007]
Next, a description will be given mainly with reference to FIG. A second wiring 18 having a two-layer structure is formed from the lower surface end of the insulating film 14 to another predetermined portion of the lower surface of the insulating film 14. In this case, the second wiring 18 includes a connection pad portion 18 a formed at another predetermined position on the lower surface of the insulating film 14, and a lead line 18 b extending from the connection pad portion 18 a to the lower surface end of the insulating film 14. It is made up of. A second columnar electrode 19 is formed on the lower surface of the connection pad portion 18a. A sealing film 20 is formed on the entire lower surface of the insulating film 14 excluding the first and second columnar electrodes 17 and 19. In this case, the lower end surfaces of the first and second columnar electrodes 17 and 19 are flush with the lower surface of the sealing film 20 and are exposed.
[0008]
A first insulating film 21 is formed on the upper surface of the silicon substrate 12. A third wiring 22 is formed on the upper surface of the first insulating film 21. In this case, the third wiring 22 extends to a connection pad portion 22 a formed at a predetermined position on the upper surface of the first insulating film 21 and from the connection pad portion 22 a to the upper surface end portion of the first insulating film 21. It consists of a lead wire 22b. A second insulating film 23 is formed on the entire top surface of the first insulating film 21 excluding the central portion of the connection pad portion 22a, and an opening portion in which the central portion of the connecting pad portion 22a is formed in the second insulating film 23. 24 is exposed. A fourth wiring 25 is formed from the exposed upper surface of the connection pad 22 a to a predetermined location on the upper surface of the second insulating film 23. In this case, the fourth wiring 25 is formed between the connection portion 25a formed on the connection pad 22a, the connection pad portion 25b formed at a predetermined position on the upper surface of the second insulating film 23, and the like. It consists of a routing line 25c.
[0009]
A planar substantially semicircular groove 26 is formed at a predetermined location on the side surface of the silicon substrate 12 so as to extend in the vertical direction. A connecting portion 27 is formed in the groove 26. The lower end portion of the connection portion 27 is connected to the distal end portion of the routing line 18 b of the second wiring 18, and the upper end portion is connected to the distal end portion of the routing line 22 b of the third wiring 22. Thereby, the fourth wiring 25 is connected to the second columnar electrode 19 via the third wiring 22, the connection portion 27, and the second wiring 18. A portion of the groove 26 including the connection portion 27 is covered with the sealing film 20 described above.
[0010]
The bare chip 31 includes a planar rectangular silicon substrate 32. In this case, the planar size of the silicon substrate 32 is appropriately smaller than the planar size of the silicon substrate 12 of the semiconductor package 11. A plurality of columnar electrodes 33 are formed on the outer peripheral portion of the lower surface of the silicon substrate 32. The wiring substrate 41 is formed by forming wirings (not shown) including first and second connection pads 43 and 44 on the upper surface of a substrate 42 made of glass epoxy or the like. In this case, the first connection pad 43 is for the semiconductor package 11, and the second connection pad 44 is for the bare chip 31. The anisotropic conductive adhesive 51 is made of an insulating adhesive 52 in which conductive particles 53 are mixed almost uniformly.
[0011]
The columnar electrode 33 of the bare chip 31 is bonded to the connection pad 25 a of the fourth wiring 25 of the semiconductor package 11, whereby the bare chip 31 is mounted on the semiconductor package 11, thereby configuring the semiconductor device 1. Yes. Further, the lower surface of the sealing film 20 including the lower end surfaces of the first and second columnar electrodes 17 and 19 of the semiconductor package 11 is connected to the connection pads 43 and 44 of the wiring substrate 41 with an anisotropic conductive adhesive 51 interposed therebetween. Thus, the semiconductor device 1 is mounted on the wiring substrate 41. In this state, the lower end surfaces of the first and second columnar electrodes 17 and 19 are connected to the first and second connection pads 43 and 44 of the wiring substrate 41 through the conductive particles 53. Thereby, the columnar electrode 33 of the bare chip 31 is connected to the wiring substrate 41 via the fourth wiring 25, the third wiring 22, the connection portion 27, the second wiring 18, the second columnar electrode 19, and the conductive particles 53. The second connection pad 44 is connected.
[0012]
As described above, in this semiconductor device mounting structure, the bare chip 31 is mounted on the semiconductor package 11 to constitute the semiconductor device 1, and the semiconductor device 1 is mounted on the wiring substrate 41. The package 11 can be three-dimensionally mounted on the wiring board 41, so that the mounting density can be increased.
[0013]
Next, an example of a method for manufacturing the semiconductor package 11 will be described with reference to FIGS. The first wiring 16 and the first columnar electrode 17 shown in FIG. 1 are formed at the same time as the second wiring 18 and the second columnar electrode 19 shown in FIG. The formation of the wiring 16 and the first columnar electrode 17 is omitted. First, as shown in FIG. 3, a wafer having a connection pad 13 formed on the lower surface of a silicon substrate 12 in a wafer state is prepared. In this case, a passivation film may be formed on a portion of the lower surface of the silicon substrate 12 excluding the central portion of the connection pad 13. In FIG. 3, the area indicated by reference numeral 61 is a dicing street.
[0014]
Next, as shown in FIG. 4, an insulating film 14 made of polyimide or the like is formed on the entire lower surface of the silicon substrate 12, and then an opening 15 shown in FIG. 1 is formed in the insulating film 14. Next, the base metal layer 62 is formed on the entire lower surface of the insulating film 14 including the opening 15. Next, a plating resist layer 63 is formed on the lower surface of the base metal layer 62 except for the region where the second wiring 18 and the groove 26 shown in FIG. 2 are to be formed. Next, by performing electroplating of gold or the like using the base metal layer 62 as a plating current path, the plating layer 64 is formed in a region where the second wiring 18 and the groove 26 shown in FIG. Form. Thereafter, the plating resist layer 63 is peeled off.
[0015]
Next, as shown in FIG. 5, a first insulating film 21 made of polyimide or the like is formed on the entire top surface of the silicon substrate 12. Next, as shown in FIG. 6, a substantially circular planar through-hole (corresponding to the groove 26 in FIG. 2) 26 is wet-etched in the silicon substrate 12 or the like in a portion corresponding to a predetermined plurality of locations of the dicing street 61. , Dry etching, laser irradiation or the like. In this case, an insulating film (not shown) made of a natural oxide film is formed on the wall surface of the silicon substrate 12 exposed in the through hole 26. When the thickness of the insulating film is too thin, the thickness of the insulating film may be increased by heat treatment.
[0016]
Next, as shown in FIG. 7, a metal film 65 made of copper or the like is formed on the upper surface of the first insulating film 21 and the inner wall surface of the through hole 26 by sputtering. In this state, the lower end portion of the metal film 65 formed in the through hole 26 is connected to the base metal layer 62 and the plating layer 64. When there is a problem with the conductivity of the metal film 65 formed in the through hole 26, the through hole 26 may be filled with a conductive paste. Further, the metal film 65 formed in the through hole 26 may be formed by a through hole plating process.
[0017]
Next, as shown in FIG. 8, a dry film resist 66 is laminated on the lower surface side of the silicon substrate 12, and the dry film resist 66 is then applied to a portion corresponding to the connection pad portion 18a of the second wiring 18 in FIG. An opening 67 is formed. Next, the second columnar electrode 19 is formed under the plating layer 64 in the opening 67 by performing electrolytic plating of gold or the like using the base metal layer 62 as a plating current path. Next, when the dry film resist 66 is peeled off, it becomes as shown in FIG. Next, when the base metal layer 62 is etched using the plating layer 64 as a mask, the second wiring 18 having a two-layer structure is formed as shown in FIG.
[0018]
Next, as shown in FIG. 11, a sealing film 20 made of an epoxy resin or the like is formed on the lower surface side of the silicon substrate 12 and in the through hole 26. In this case, the thickness of the sealing film 20 is increased to some extent so as to completely cover the second columnar electrode 19, and then the lower surface of the sealing film 20 is temporarily polished and planarized. This flattening is to facilitate later steps. Even in this flattened state, the lower end surface of the second columnar electrode 19 is covered with the sealing film 20. This is to protect the lower end surface of the second columnar electrode 19 in a later step. Next, a resist layer 68 is formed on the upper surface of the metal film 65 in the region where the third wiring 22 shown in FIG. Next, when the metal film 65 is etched using the resist layer 68 as a mask, the third wiring 22 and the connecting portion 27 are formed as shown in FIG. Thereafter, the resist layer 68 is peeled off.
[0019]
Next, as shown in FIG. 13, a second insulating film 23 made of polyimide or the like is formed on the upper surface side of the silicon substrate 12, and then the opening 24 shown in FIG. 1 is formed in the second insulating film 23. . Next, as shown in FIG. 14, a metal film 69 made of copper or the like is formed on the entire upper surface of the second insulating film 23 including the opening 24. Next, a resist layer 70 is formed in a region where the fourth wiring 25 shown in FIG. Next, when the metal film 69 is etched using the resist layer 70 as a mask, the fourth wiring 25 is formed as shown in FIG. Thereafter, the resist layer 70 is peeled off. Next, as shown in FIG. 16, the lower surface of the sealing film 20 is finally polished to expose the lower end surface of the second columnar electrode 19. Next, when dicing is performed at the center of the dicing street 61, the semiconductor package 11 shown in FIGS. 1 and 2 is obtained.
[0020]
In the above embodiment, for example, as shown in FIG. 2, the second columnar electrode 19 and the second connection pad 44 of the wiring substrate 41 are connected via the conductive particles 53 of the anisotropic conductive adhesive 51. However, the present invention is not limited to this. For example, as shown in FIG. 17, the connection is made via the solder ball 71 provided in advance on the second connection pad 44 or the second columnar electrode 19. May be. In the above-described embodiment, the case where the fourth wiring 25 is exposed as shown in FIG. 2, for example, is described. However, the present invention is not limited to this. For example, as shown in FIG. You may make it cover by. Moreover, although the said embodiment demonstrated the case where the 1st columnar electrode 17 for semiconductor packages 11 and the 2nd columnar electrode 19 for bare chips 31 were separated, it is not restricted to this, For example, for power supplies or ground Similarly, the second wiring 18 may be connected to the first wiring 16 for power supply or ground, and the first columnar electrode 17 for power supply or ground may be shared. Furthermore, in the above embodiment, the case where one bare chip 31 is mounted on the semiconductor package 11 has been described. However, the present invention is not limited to this, and a plurality of bare chips 31 and other chip components may be mounted. In this case, for example, as shown in FIG. 17, third and fourth wirings 22 a and 25 a may be appropriately formed in the central portion on the silicon substrate 12.
[0021]
Further, the second wiring 18 and the second columnar electrode 19 may be omitted as shown in FIG. That is, a groove 26 is formed on the side surfaces of the silicon substrate 12 and the sealing film 20, and a connection portion 27 made of a conductive paste or the like is formed in the groove 26 by being connected to the third wiring 22. May be connected to the second connection pads 44 of the wiring substrate 41 via the conductive particles 53 of the anisotropic conductive adhesive 51. In this case as well, for example, only the second wiring 18 and the second columnar electrode 19 for power supply and ground may be formed, and the first columnar electrode 17 for power supply and ground may be shared. In addition, the wiring formed on the upper surface side of the silicon substrate 12 is not limited to the two-layer structure including the third and fourth wirings 22 and 25, and may have a single-layer structure or a structure of three or more layers. In some cases, the first wiring 16 may be formed of only a base metal layer. Furthermore, the wiring formed on the upper surface side of the silicon substrate 12 may be connected to the second connection pads 44 of the wiring substrate 41 by wire bonding without forming the connection portion 27 and the like.
[0022]
【The invention's effect】
As described above, according to the present invention, since the wiring is formed on the other surface of the semiconductor substrate, the electronic component can be mounted on the other surface of the semiconductor substrate. Electronic components mounted on the other surface of the semiconductor substrate can be three-dimensionally mounted on the wiring substrate, and as a result, the mounting density can be increased.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a portion of a first columnar electrode mainly for a semiconductor package of a semiconductor device mounting structure according to an embodiment of the present invention;
FIG. 2 is a sectional view of a portion of a second columnar electrode mainly for a bare chip of the mounting structure.
FIG. 3 is a cross-sectional view of a part of what was initially prepared in manufacturing the semiconductor package shown in FIGS. 1 and 2;
FIG. 4 is a cross-sectional view of the manufacturing process following FIG. 3;
FIG. 5 is a cross-sectional view of the manufacturing process following FIG. 4;
6 is a cross-sectional view of the manufacturing process following FIG. 5. FIG.
7 is a cross-sectional view of a manufacturing step that follows FIG. 6. FIG.
FIG. 8 is a cross-sectional view of the manufacturing process following FIG. 7;
FIG. 9 is a cross-sectional view of the manufacturing process following FIG. 8;
10 is a cross-sectional view of a manufacturing step that follows FIG. 9; FIG.
FIG. 11 is a cross-sectional view of the manufacturing process following FIG. 10;
FIG. 12 is a cross-sectional view of the manufacturing process following FIG. 11;
13 is a cross-sectional view of a manufacturing step that follows FIG. 12. FIG.
FIG. 14 is a cross-sectional view of the manufacturing process following FIG. 13;
FIG. 15 is a cross-sectional view of the manufacturing process following FIG. 14;
FIG. 16 is a cross-sectional view of the manufacturing process following FIG. 15;
FIG. 17 is a cross-sectional view of a main part of a semiconductor device mounting structure according to another embodiment of the present invention;
FIG. 18 is a cross-sectional view of a substantial part of a semiconductor device mounting structure according to still another embodiment of the present invention;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Semiconductor package 16 1st wiring 17 1st columnar electrode 18 2nd wiring 19 2nd columnar electrode 22 3rd wiring 25 4th wiring 27 Connection part 31 Bare chip 41 Wiring board 51 Anisotropic conduction Adhesive

Claims (2)

ウエハの一の面上に形成された絶縁膜に形成された開口部を介して露出された接続パッド上から前記絶縁膜上にかけて接続パッド部を有する第１の配線を形成するとともに、ダイシングストリートの部分における前記絶縁膜上から前記絶縁膜上の他の部分にかけて接続パッド部を有する第２の配線を形成する工程と、前記第１及び第２の配線の各接続パッド部上に第１及び第２の柱状電極を形成する工程と、前記第１及び第２の柱状電極を除く前記絶縁膜上に封止膜を形成する工程と、前記ウエハの他の面上に第３の配線を形成する工程と、前記ウエハのダイシングストリートの部分に貫通孔を形成して該貫通孔内に前記第２の配線と前記第３の配線とを接続する接続部を形成する工程と、
前記ウエハの他の面上に第３の配線を形成する工程と、前記第３の配線形成後に、前記封止膜の下面を本研磨し、第２の柱状電極の下端面を露出させる工程と、前記ウエハをダイシングして複数の半導体装置を得る工程とを具備することを特徴とする半導体装置の製造方法。Forming a first wiring having a connection pad portion from the connection pad exposed through the opening formed in the insulating film formed on one surface of the wafer to the insulating film; Forming a second wiring having a connection pad portion over the insulating film from the insulating film to another portion of the insulating film, and the first and second wirings on each connection pad portion of the first and second wirings. Forming a columnar electrode, forming a sealing film on the insulating film excluding the first and second columnar electrodes, and forming a third wiring on the other surface of the wafer. Forming a through hole in a dicing street portion of the wafer and forming a connection portion connecting the second wiring and the third wiring in the through hole; and
Forming a third wiring on the other surface of the wafer; and, after forming the third wiring, subjecting the lower surface of the sealing film to main polishing to expose a lower end surface of the second columnar electrode; a method of manufacturing a semiconductor device characterized by comprising the steps of: obtaining a plurality of semiconductor devices by dicing the upper lobe. 請求項１記載の発明において、ダイシング後に、前記ウエハの他の面上に電子部品を前記第３の配線に接続させて搭載することを特徴とする半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein after dicing, an electronic component is mounted on the other surface of the wafer while being connected to the third wiring.
JP27245598A 1998-09-10 1998-09-10 Manufacturing method of semiconductor device Expired - Fee Related JP4168494B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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