JP5170134B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5170134B2
JP5170134B2 JP2010059007A JP2010059007A JP5170134B2 JP 5170134 B2 JP5170134 B2 JP 5170134B2 JP 2010059007 A JP2010059007 A JP 2010059007A JP 2010059007 A JP2010059007 A JP 2010059007A JP 5170134 B2 JP5170134 B2 JP 5170134B2
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chip
connection terminal
wafer
height
forming
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JP2010177682A (en
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雅基 田子
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NEC Corp
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H—ELECTRICITY
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a plurality of semiconductor chips are mounted highly densely in small-size, and connected electrically with the shortest wiring length, and to provide a manufacturing method thereof. <P>SOLUTION: In a semiconductor, a second chip 1b is mounted on the same surface as the connection terminal 4 forming surface of a first chip 1a with bumps 8 interposed therebetween, and the height of the second chip is lower than the connection terminals with respect to the first chip mounting surface. A plurality of projections 12, which are made of the same material as the bumps and have a predetermine height, are formed on the surface opposite to the second chip mounting surface, and the height of the connection terminals and the height of the projections on the second chip are set to be nearly the same with respect to the first chip mounting surface. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は半導体装置及びその製造方法に関し、特に、複数の半導体チップを高密度に積層してなる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device formed by stacking a plurality of semiconductor chips at a high density and a manufacturing method thereof.

半導体パッケージおよび半導体チップの実装に関しては、実装面積、容積の小型化、高密度化、また、コストの低減が重要な要素の一つとなっている。この目的のために、半導体チップは微細化が進められ、これらを実装する手法として、複数の半導体チップをセラミック配線基板や、シリコン配線基板またはプリント配線基板上にワイヤボンディングもしくはフリップチップ実装するというマルチチップモジュール（以下、ＭＣＭ）手法が用いられている。   Regarding the mounting of semiconductor packages and semiconductor chips, mounting area, size reduction, density increase, and cost reduction are one of the important factors. For this purpose, semiconductor chips have been miniaturized, and as a technique for mounting them, a plurality of semiconductor chips are bonded by wire bonding or flip chip mounting on a ceramic wiring board, silicon wiring board or printed wiring board. A chip module (hereinafter referred to as MCM) technique is used.

このＭＣＭ手法について図７を参照して説明する。まず、図７に示すように、従来のＭＣＭは、シリコン基板１５上にハンダバンプ１７によってＬＳＩチップ等の半導体チップ１６が平面的に固定、接続され、シリコン基板１５は更に実装基板１４に接着剤２０によって固定されている。また、シリコン基板１５上には所定の配線パターンが形成されており、シリコン基板１５の外部接続端子１８と実装基板１４のボンディングパッドとがボンディングワイヤ１９で接続され、半導体チップ１６の信号はハンダバンプ１７、シリコン基板１５上の配線パターン及びボンディングワイヤ１９を介して外部に伝達される。   This MCM method will be described with reference to FIG. First, as shown in FIG. 7, in a conventional MCM, a semiconductor chip 16 such as an LSI chip is planarly fixed and connected to a silicon substrate 15 by solder bumps 17, and the silicon substrate 15 is further bonded to a mounting substrate 14 with an adhesive 20. It is fixed by. Further, a predetermined wiring pattern is formed on the silicon substrate 15, the external connection terminals 18 of the silicon substrate 15 and the bonding pads of the mounting substrate 14 are connected by bonding wires 19, and the signal of the semiconductor chip 16 is a solder bump 17. Then, it is transmitted to the outside through the wiring pattern on the silicon substrate 15 and the bonding wire 19.

また、従来のＭＣＭの他の形態として、図８に示す構造のものもある。このＭＣＭは、基板２１上にハンダバンプ１７を介して半導体チップ１６が平面的に固定、接続され、バンプ接合面は信頼性を向上させるために封止樹脂２２によって封止されている。そして、この基板２１には半導体チップ１６の実装面と反対側の面に外部接続端子１８が形成され、基板２１の内部に立体的に形成された内部配線２３によって半導体チップ１６と外部接続端子１８とを接続している。   As another form of the conventional MCM, there is a structure shown in FIG. In this MCM, the semiconductor chip 16 is planarly fixed and connected to the substrate 21 via the solder bumps 17, and the bump bonding surface is sealed with a sealing resin 22 in order to improve reliability. Then, external connection terminals 18 are formed on the substrate 21 on the surface opposite to the mounting surface of the semiconductor chip 16, and the semiconductor chips 16 and the external connection terminals 18 are formed by internal wiring 23 formed three-dimensionally inside the substrate 21. And connected.

また、複数の半導体チップを実装する他の方法として、マルチチップパッケージ（以下ＭＣＰ）手法と呼ばれるものがあり、この手法は寸法の異なる複数のチップを立体的に積層し、ワイヤボンディングによって電気的に接続するものである。この従来のＭＣＰについて、図９を参照して説明すると、基板２１上にサイズの大きい半導体チップ１６ａが絶縁ペーストにより固定されており、半導体チップ１６ａの上には、更にサイズの小さい半導体チップ１６ｂが同様に絶縁ペーストにより固定されている。そして、各々の半導体チップ１６ａ、１６ｂの電極端子と基板上の端子とはボンディングワイヤ１９により接続されており、電気信号は基板の他面に設けた外部接続端子１８を介して外部に伝達される。また、立体的に結線したボンディングワイヤ１９の切断を防止し、信頼性を向上させるために半導体チップ１６ａ、１６ｂはモールド樹脂２４により固定されている。   In addition, as another method for mounting a plurality of semiconductor chips, there is a so-called multi-chip package (hereinafter referred to as MCP) technique, in which a plurality of chips having different dimensions are stacked three-dimensionally and electrically connected by wire bonding. To connect. The conventional MCP will be described with reference to FIG. 9. A large-sized semiconductor chip 16a is fixed on the substrate 21 with an insulating paste, and a smaller-sized semiconductor chip 16b is formed on the semiconductor chip 16a. Similarly, it is fixed with an insulating paste. The electrode terminals of the semiconductor chips 16a and 16b and the terminals on the substrate are connected by bonding wires 19, and an electric signal is transmitted to the outside through the external connection terminals 18 provided on the other surface of the substrate. . Further, the semiconductor chips 16a and 16b are fixed by a mold resin 24 in order to prevent the bonding wires 19 connected in a three-dimensional manner from being cut and to improve the reliability.

この従来のＭＣＰの製造方法について、図１０を参照して説明すると、まず、ウェハ１及びウェハ２にそれぞれ半導体チップ１６ａ、１６ｂ作り込んだ後、ウェハ１、２を所望の厚さとなるように各々裏面研磨し（Ｓ３０１、Ｓ３０３）、ダイシングによってウェハを分割して半導体チップを得る（Ｓ３０２、Ｓ３０４）。その後、半導体チップ１６ａ及び半導体チップ１６ｂを絶縁ペーストにより基板２１にマウントし（Ｓ３０５）、各々の半導体チップ１６ａ、１６ｂの端子と基板２１の端子とをボンディングワイヤ１９により接続し（Ｓ３０６）、モールド樹脂２４で封止した後（Ｓ３０７）、外部接続端子１８を形成することにより（Ｓ３０８）、ＭＣＰが完成する。   This conventional MCP manufacturing method will be described with reference to FIG. 10. First, after the semiconductor chips 16a and 16b are formed on the wafer 1 and the wafer 2, respectively, the wafers 1 and 2 are each formed to have a desired thickness. The back surface is polished (S301, S303), and the wafer is divided by dicing to obtain semiconductor chips (S302, S304). Thereafter, the semiconductor chip 16a and the semiconductor chip 16b are mounted on the substrate 21 with an insulating paste (S305), and the terminals of the respective semiconductor chips 16a and 16b and the terminals of the substrate 21 are connected by the bonding wires 19 (S306). After sealing at 24 (S307), the external connection terminal 18 is formed (S308), thereby completing the MCP.

ＭＣＭやＭＣＰのような、異なる機能デバイスを複合化し、システム化できるパッケージは、機能デバイスの製造プロセスが異なるため１つの半導体チップに集積化することがコストや技術的課題によって困難な半導体素子に用いられるものであるが、これらには以下に示す問題点がある。   Packages such as MCM and MCP that can be combined and systematized with different functional devices are used for semiconductor elements that are difficult to integrate on a single semiconductor chip due to different manufacturing processes of functional devices due to cost and technical issues. However, these have the following problems.

まず、従来のＭＣＭに関しては、半導体チップ１６を固定する基板として低コストのプリント配線板を使用した場合には、高精度な加工を実施することが困難であり、微細ピッチの半導体チップ１６を搭載する基板を低コストで製造することができない。また、シリコン基板１５を使用した場合には、貫通のビアホールを形成することができないため、外部接続端子１８をボールグリットアレイ（ＢＧＡ）タイプにすることができず、ワイヤボンディングにより外部との接続を行なわなければならない。従って、小型化という点で問題があり、また、シリコン基板１５自体の製造コストが高くなってしまう。   First, with respect to the conventional MCM, when a low-cost printed wiring board is used as a substrate for fixing the semiconductor chip 16, it is difficult to perform high-precision processing, and the semiconductor chip 16 with a fine pitch is mounted. The substrate to be manufactured cannot be manufactured at low cost. Further, when the silicon substrate 15 is used, a through via hole cannot be formed, so the external connection terminal 18 cannot be a ball grid array (BGA) type, and connection to the outside is made by wire bonding. Must be done. Therefore, there is a problem in terms of downsizing, and the manufacturing cost of the silicon substrate 15 itself increases.

また、これらのＭＣＭパッケージは、半導体チップ１６を平面的に配置し、配線基板上で互いに接続するため、実装面積としては少なくとも搭載する半導体チップ１６の面積の和とそれらを接続する配線エリアとが必要であり、必ずしも小型化、高密度化に適してはおらず、更に、配線長が長くなるために信号の遅延が生じ、所望の高速動作特性を得ることが難しいという問題がある。   In addition, these MCM packages have the semiconductor chips 16 arranged in a plane and connected to each other on the wiring board. Therefore, the mounting area includes at least the sum of the areas of the semiconductor chips 16 to be mounted and the wiring area for connecting them. This is necessary, and is not necessarily suitable for miniaturization and high density, and further, there is a problem that it is difficult to obtain desired high-speed operation characteristics because the wiring length becomes long and signal delay occurs.

一方、半導体チップを立体的に積層するＭＣＰの場合には、ＭＣＭに比べて実装面積を小さくすることができるが、半導体チップ１６ａ、１６ｂを立体的に積層してワイヤボンディングにより結線するため、パッケージ全体として厚みが増し、実装容積が増加してしまい、必ずしも高密度化には適していない。また、各々の半導体チップ１６ａ、１６ｂをボンディングワイヤ１９で接続するため、ワイヤが長くなってしまい、寄生容量や配線抵抗により動作速度遅延が発生してしまうという問題が発生する。   On the other hand, in the case of an MCP in which semiconductor chips are three-dimensionally stacked, the mounting area can be reduced as compared with the MCM. However, since the semiconductor chips 16a and 16b are three-dimensionally stacked and connected by wire bonding, the package As a whole, the thickness increases and the mounting volume increases, which is not necessarily suitable for high density. Further, since the semiconductor chips 16a and 16b are connected by the bonding wires 19, the wires become long, and there arises a problem that an operation speed delay occurs due to parasitic capacitance and wiring resistance.

更に、ＭＣＰの製造方法においては、小型、高密度化するために半導体チップ１６ａ、１６ｂを薄く加工し、絶縁ペーストなどで基板２１に実装し、ワイヤボンディングしているが、半導体チップ１６ａ、１６ｂを薄く加工するため、ダイシングした後の工程で半導体チップ１６ａ、１６ｂのハンドリングが困難であり、更に、薄く加工した半導体チップ１６ａ、１６ｂは剛性が低く、反りやうねりがペーストによる実装後に現れるため、その後のワイヤボンディング時に積層した半導体チップ１６ａ、１６ｂが破壊されてしまうという問題もある。   Further, in the MCP manufacturing method, the semiconductor chips 16a and 16b are thinly processed for miniaturization and high density, mounted on the substrate 21 with insulating paste or the like, and wire bonded. Since it is processed thinly, it is difficult to handle the semiconductor chips 16a and 16b in the process after dicing. Further, since the thinly processed semiconductor chips 16a and 16b have low rigidity and warping and waviness appear after mounting by paste, There is also a problem that the stacked semiconductor chips 16a and 16b are destroyed at the time of wire bonding.

本発明は、上記問題点に鑑みてなされたものであって、その目的の一つは、複数の半導体チップを小型でかつ高密度に実装し、電気的に最短な配線長で結線することができる半導体装置及びその製造方法を提供することにある。   The present invention has been made in view of the above problems, and one of its purposes is to mount a plurality of semiconductor chips in a small and high density and connect them with the shortest wiring length electrically. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof.

また、本発明の第２の目的は、資材コスト、製造コストの上昇を抑制し、微細化された半導体チップの実装を確実に行うことができる半導体装置及びその製造方法を提供することにある。   A second object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress an increase in material cost and manufacturing cost and can reliably mount a miniaturized semiconductor chip.

上記目的を達成するため、本発明は、外部と接続するＢＧＡからなる接続端子を有する第１のチップの前記接続端子形成面と同一面に、第２のチップがバンプを介して実装されてなる半導体装置において、前記第１のチップの実装面に対して、前記第２のチップの高さが前記接続端子よりも低く設定され、前記第２のチップの実装面と反対側の面に、前記バンプと同じ材質の、所定の高さの複数の突起を備え、前記第１のチップの実装面に対して、前記接続端子と前記第２のチップ上の前記突起とが略等しい高さとなるように前記突起の高さが設定されるものである。
To achieve the above object, according to the present invention, a second chip is mounted via bumps on the same surface as the connection terminal forming surface of a first chip having a connection terminal made of BGA connected to the outside. In the semiconductor device, the height of the second chip is set lower than the connection terminal with respect to the mounting surface of the first chip, and the surface opposite to the mounting surface of the second chip is A plurality of protrusions of the same material as the bump and having a predetermined height are provided so that the connection terminals and the protrusions on the second chip have substantially the same height with respect to the mounting surface of the first chip. The height of the protrusion is set to the above.

本発明によれば、下記記載の効果を奏する。   According to the present invention, the following effects can be obtained.

本発明の第１の効果は、複数の半導体チップの実装において、実装面積および実装容積を小さくすることができ、各々の半導体チップの接続にかかる配線長を最短とすることができるということである。   The first effect of the present invention is that in mounting a plurality of semiconductor chips, the mounting area and the mounting volume can be reduced, and the wiring length required to connect each semiconductor chip can be minimized. .

その理由は、実装基板を使用することなく、一方の半導体チップ１ａ上に再配線を設け、外部接続端子であるＢＧＡ端子の高さより十分低くなるように薄く加工した他方の半導体チップ１ｂと外部接続端子とを同一の面に設け、再配線により、半導体チップ１ａと半導体チップ１ｂと外部接続端子との相互接続を行っているからである。   The reason is that, without using a mounting substrate, a rewiring is provided on one semiconductor chip 1a, and the other semiconductor chip 1b processed to be thinner than the height of the BGA terminal which is an external connection terminal is externally connected. This is because the terminals are provided on the same surface, and the semiconductor chip 1a, the semiconductor chip 1b, and the external connection terminals are interconnected by rewiring.

また、本発明の第２の効果は、半導体チップ１ａに接続される半導体チップ１ｂの裏面に金属突起を複数配置することにより、マザーボードへの実装時に、半導体チップ２が発生する熱量の放熱する効果、グランド電位を強化する効果及び半導体装置をマザーボードに実装する際の接続補強の効果を高めることができるということである。   The second effect of the present invention is that a plurality of metal protrusions are arranged on the back surface of the semiconductor chip 1b connected to the semiconductor chip 1a, so that the amount of heat generated by the semiconductor chip 2 is radiated when mounted on the mother board. The effect of strengthening the ground potential and the effect of reinforcing the connection when the semiconductor device is mounted on the mother board can be enhanced.

また、本発明の第３の効果は、実装基板を使用することなく、再配線をウェハ上のプロセスで形成することができるため、寸法精度が高く、微細化に適し、又、資材コストを削減することができるということである。   In addition, the third effect of the present invention is that rewiring can be formed by a process on a wafer without using a mounting substrate, so that dimensional accuracy is high, suitable for miniaturization, and material cost is reduced. Is that you can.

また、本発明の第４の効果は、半導体チップ１ｂを半導体チップ１ａに実装した後、裏面研削して薄く加工するため、薄い半導体チップ１ｂをハンドリングする必要がなく、作業性を向上させることができ、また、従来の方法に比べて工程数を削減することができるため、コストを低くすることができるということである。   The fourth effect of the present invention is that, after the semiconductor chip 1b is mounted on the semiconductor chip 1a, the back surface is ground and thinned, so that it is not necessary to handle the thin semiconductor chip 1b, and the workability can be improved. In addition, since the number of steps can be reduced as compared with the conventional method, the cost can be reduced.

本発明の第１の実施例に係る半導体装置の構造を模式的に示す断面図である。1 is a cross-sectional view schematically showing the structure of a semiconductor device according to a first example of the present invention. 本発明の第１の実施例に係る半導体装置の構造を模式的に示す断面図である。1 is a cross-sectional view schematically showing the structure of a semiconductor device according to a first example of the present invention. 本発明の第２の実施例に係る半導体装置の一部の構造を模式的に示す拡大断面図である。It is an expanded sectional view showing typically the structure of a part of the semiconductor device concerning the 2nd example of the present invention. 本発明の第２の実施例に係る半導体装置の一部の構造を模式的に示す拡大断面図である。It is an expanded sectional view showing typically the structure of a part of the semiconductor device concerning the 2nd example of the present invention. 本発明の第３の実施例に係る半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Example of this invention. 本発明の第３の実施例に係る半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Example of this invention. 従来の半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor device. 従来の半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor device. 従来の半導体装置の構造を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor device. 従来の半導体装置の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the conventional semiconductor device.

本発明に係る半導体装置は、その好ましい一実施の形態において、半導体チップ１ａ上に、半導体チップ１ａと半導体チップ１ｂと外部接続端子４とを相互に配線する再配線３が形成され、再配線３上には、半導体チップ１ａ周囲の外部接続端子４形成領域及び半導体チップ１ａ中央の半導体チップ１ｂ実装領域に開口を有する絶縁樹脂６が設けられ、外部接続端子４形成領域の開口にはランド５を介してＢＧＡからなる外部接続端子４が形成され、半導体チップ１ｂの実装領域の開口には電極１１及びバンプ８を介して半導体チップ１ｂがフリップチップ接続され、バンプ８接合面は封止樹脂７により封止されるものであり、半導体チップ１ｂは、外部接続端子４と同一面に実装され、かつ、外部接続端子４よりも低くなるように裏面が研削され、高密度に実装される。   In a preferred embodiment of the semiconductor device according to the present invention, a rewiring 3 for wiring the semiconductor chip 1a, the semiconductor chip 1b, and the external connection terminal 4 to each other is formed on the semiconductor chip 1a. On the upper side, an insulating resin 6 having an opening is provided in the external connection terminal 4 formation region around the semiconductor chip 1a and the semiconductor chip 1b mounting region in the center of the semiconductor chip 1a, and a land 5 is provided in the opening in the external connection terminal 4 formation region. The external connection terminal 4 made of BGA is formed, the semiconductor chip 1b is flip-chip connected to the opening in the mounting region of the semiconductor chip 1b via the electrode 11 and the bump 8, and the bonding surface of the bump 8 is sealed by the sealing resin 7. The semiconductor chip 1b is mounted on the same surface as the external connection terminal 4 and the back surface thereof is polished so as to be lower than the external connection terminal 4. It is, are densely packed.

上記した本発明の実施の形態についてさらに詳細に説明すべく、本発明の実施例について、図面を参照して以下に説明する。   In order to describe the above-described embodiment of the present invention in more detail, examples of the present invention will be described below with reference to the drawings.

まず、本発明の第１の実施例に係る半導体装置について、図１及び図２を参照して説明する。図１及び図２は、本実施例の半導体装置の構造を模式的に示す断面図である。   First, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are cross-sectional views schematically showing the structure of the semiconductor device of this example.

図１に示すように、本実施例の半導体装置を構成する半導体チップ１ａには、半導体チップ１ａと外部接続端子４との接続、半導体チップ１ａと半導体チップ１ｂとの接続、半導体チップ１ｂと外部接続端子４との接続、および半導体チップ１ａと半導体チップ１ｂと外部接続端子４との相互接続がなされる再配線３が形成され、この再配線３は所定の開口を有する絶縁樹脂６により絶縁され、半導体チップ１ａ周囲の開口部にはランド５を介してＢＧＡからなる外部接続端子４が形成され、また、中央部には電極１１を介してバンプ８によって半導体チップ１ｂが実装されている。そしてランド５にはＢＧＡからなる外部接続端子４が形成されている。また、半導体チップ１ｂは、外部接続端子４の高さより十分低くなるように薄く加工され、バンプ８の接合面は封止樹脂７により封止されている。   As shown in FIG. 1, the semiconductor chip 1a constituting the semiconductor device of the present embodiment includes a connection between the semiconductor chip 1a and the external connection terminal 4, a connection between the semiconductor chip 1a and the semiconductor chip 1b, and a semiconductor chip 1b and the outside. A rewiring 3 is formed to connect to the connection terminal 4 and to interconnect the semiconductor chip 1a, the semiconductor chip 1b, and the external connection terminal 4. The rewiring 3 is insulated by an insulating resin 6 having a predetermined opening. The external connection terminal 4 made of BGA is formed in the opening around the semiconductor chip 1a through the land 5, and the semiconductor chip 1b is mounted in the center portion by the bump 8 through the electrode 11. The land 5 is formed with an external connection terminal 4 made of BGA. Further, the semiconductor chip 1 b is processed to be thin enough to be sufficiently lower than the height of the external connection terminals 4, and the bonding surfaces of the bumps 8 are sealed with a sealing resin 7.

ここで、本実施例では、半導体チップ１ａとして、通常の未研削ウェハとして用いられている厚さ６２５μｍ程度のウェハを使用し、半導体チップ１ｂは１００μｍ程度の厚さとしている。この半導体チップ１ｂの厚さは、温度サイクルによって発生する半導体チップ１ａの反りに対してバンプ接続部や封止樹脂層の応力を緩和するように反りが倣うため、薄ければ薄いほど好ましく、半導体チップ１ａに貼り合わせた状態で外部接続端子４よりも低くなる範囲で５０μｍ、３０μｍ等の任意の厚さに設定することができる。また、研削が可能で半導体チップ１ｂの特性を損なわなければ１０μｍ程度の厚さにしてもよい。また、半導体チップ１ａの厚さについても６２５μｍに限らず、半導体チップ１ａのハンドリング、強度等を勘案して任意の厚さに設定することができ、例えば、研削を施した５００μｍ、４００μｍ等の厚さであっても良い。   Here, in this embodiment, a wafer having a thickness of about 625 μm used as a normal unground wafer is used as the semiconductor chip 1a, and the semiconductor chip 1b has a thickness of about 100 μm. The thickness of the semiconductor chip 1b is preferably as thin as possible because the warp mimics the warp of the bump connection part and the sealing resin layer with respect to the warp of the semiconductor chip 1a generated by the temperature cycle. The thickness can be set to an arbitrary thickness of 50 μm, 30 μm, etc. within a range lower than that of the external connection terminal 4 in a state of being bonded to the chip 1a. The thickness may be about 10 μm as long as grinding is possible and the characteristics of the semiconductor chip 1b are not impaired. Further, the thickness of the semiconductor chip 1a is not limited to 625 μm, and can be set to any thickness in consideration of the handling, strength, etc. of the semiconductor chip 1a. For example, the thickness of 500 μm, 400 μm, etc. after grinding. It may be.

また、半導体チップ１ａ、１ｂを貼り合わせた半導体装置とマザーボードとの接続強度、放熱効果等を更に高めるためには、図２に示すように、薄く加工した半導体チップ１ｂの裏面に突起１２を複数配置する構造とすることもできる。この突起１２は、外部接続端子４と同じ高さとなるように調整されて、マザーボードへの実装時には外部接続端子４と同様にマザーボードに接触する。   Further, in order to further enhance the connection strength between the semiconductor device bonded with the semiconductor chips 1a and 1b and the mother board, the heat radiation effect, etc., as shown in FIG. 2, a plurality of protrusions 12 are formed on the back surface of the thinly processed semiconductor chip 1b. It can also be set as the structure to arrange. The protrusions 12 are adjusted so as to be the same height as the external connection terminals 4 and come into contact with the mother board in the same manner as the external connection terminals 4 when mounted on the mother board.

この突起１２によって、図１の構造の半導体装置よりも、半導体チップ１ｂが発生する熱量を放熱する効果を高め、グランド電位を強化すると共に半導体装置をマザーボードに実装する際の接続補強の効果を発揮することができる。ここでは、突起１２として外部接続端子４と同じ材質であるハンダを使用しているが、ハンダに代えて他の金属材料や導電性の樹脂材料を用いることもできる。また、絶縁性の樹脂を用いることもでき、この場合には、グランド電位の強化という効果は無いが、放熱効果と接続補強の効果は十分に得ることができる。これらは突起である必要はなく、用途に応じた形状、もしくは全面で接続しても効果を得ることができる。   The protrusion 12 enhances the effect of dissipating the amount of heat generated by the semiconductor chip 1b as compared with the semiconductor device having the structure of FIG. 1, strengthens the ground potential, and demonstrates the effect of reinforcing the connection when the semiconductor device is mounted on the motherboard. can do. Here, solder which is the same material as the external connection terminal 4 is used as the protrusion 12, but other metal material or conductive resin material may be used instead of the solder. Insulating resin can also be used. In this case, there is no effect of strengthening the ground potential, but the effect of heat dissipation and connection reinforcement can be sufficiently obtained. These do not need to be protrusions, and an effect can be obtained even if they are connected in a shape corresponding to the application or the entire surface.

上述した図１及び図２に示す半導体装置では、再配線３はアルミニウムもしくは銅を使用したウェハの配線プロセスを利用して形成することにより工程の複雑化を回避している。また、絶縁樹脂６はポリイミドもしくは低弾性率のエポキシ樹脂を使用し、電気的に絶縁し、かつ耐熱性と耐湿性を付与している。また、封止樹脂７としては、半導体チップ１ｂのバンプ８接合部を保護するため、膨張係数がバンプ８や半導体チップと整合するエポキシ樹脂を使用することが好ましいが、接合部の強度が充分に保てる場合には絶縁樹脂６と同じ材料を用いることも可能である。   In the semiconductor device shown in FIG. 1 and FIG. 2 described above, the rewiring 3 is formed using a wafer wiring process using aluminum or copper, thereby avoiding complication of the process. Further, the insulating resin 6 uses polyimide or a low elastic modulus epoxy resin, is electrically insulated, and imparts heat resistance and moisture resistance. In addition, as the sealing resin 7, it is preferable to use an epoxy resin whose expansion coefficient matches the bump 8 or the semiconductor chip in order to protect the bump 8 joint of the semiconductor chip 1b, but the strength of the joint is sufficient. If it can be maintained, the same material as the insulating resin 6 can be used.

本実施例では、再配線３を覆う絶縁樹脂６は基板全面に均一に形成しているが、外部接続端子４の配置されるエリアと、半導体チップ１ｂを搭載するエリアとで材料特性の異なる絶縁樹脂を使用することもできる。例えば、外部接続端子４が配置されるエリアに、半導体チップ１ｂが実装されるエリアより弾性率の低い絶縁樹脂を用いることもでき、この構成によりバンプ８や半導体チップ１ｂに加わる応力をより緩和することができる。   In this embodiment, the insulating resin 6 covering the rewiring 3 is uniformly formed on the entire surface of the substrate. However, the insulating material having different material characteristics is different between the area where the external connection terminals 4 are arranged and the area where the semiconductor chip 1b is mounted. Resin can also be used. For example, an insulating resin having a lower elastic modulus than the area where the semiconductor chip 1b is mounted can be used in the area where the external connection terminals 4 are arranged, and this configuration further reduces the stress applied to the bumps 8 and the semiconductor chip 1b. be able to.

また、本実施例では、半導体チップ１ｂが実装される半導体チップ１ａの所定位置にバンプ８接続のための電極１１が形成されるが、この電極１１は、外部接続端子４のランド５と同時に形成され、共に同じ材料であるニッケルに金メッキが被覆された電極を使用している。しかしながら、よりバンプ８との接合強度を高めたい場合や、この電極１１上にハンダの被覆を施す場合には、電極１１とランド５とは、異なる材料を用いても形成しても良い。   In this embodiment, an electrode 11 for connecting the bump 8 is formed at a predetermined position of the semiconductor chip 1a on which the semiconductor chip 1b is mounted. The electrode 11 is formed simultaneously with the land 5 of the external connection terminal 4. In this case, an electrode in which nickel, which is the same material, is coated with gold plating is used. However, when it is desired to increase the bonding strength with the bump 8 or when the electrode 11 is coated with solder, the electrode 11 and the land 5 may be formed using different materials.

なお、本実施例では、半導体チップ１ａに対して半導体チップ１ｂが中央に実装される場合について記載したが、本発明は上記実施例に限定されるものではなく、半導体チップと同等の機能を持つ２つ以上のチップ、もしくは異なる機能の２つ以上のチップを実装することもでき、実装する位置は任意に設定することができる。   In this embodiment, the case where the semiconductor chip 1b is mounted in the center with respect to the semiconductor chip 1a has been described. However, the present invention is not limited to the above-described embodiment, and has the same function as the semiconductor chip. Two or more chips or two or more chips having different functions can be mounted, and the mounting positions can be arbitrarily set.

次に、本発明の第２の実施例に係る半導体装置について、図３及び図４を参照して説明する。図３及び図４は、第２の実施例に係る半導体装置の一部の構造を模式的に示す拡大断面図である。なお、本実施例は、前記した第１の実施例に係る半導体装置のランド５及び電極１１の構造を改良したものであり、他の部分の構造に関しては第１の実施例と同様である。   Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 3 and 4 are enlarged cross-sectional views schematically showing a partial structure of the semiconductor device according to the second embodiment. In this embodiment, the structure of the land 5 and the electrode 11 of the semiconductor device according to the first embodiment is improved, and the structure of the other parts is the same as that of the first embodiment.

まず、図３に示す構造について説明すると、第２の実施例の半導体装置は、半導体チップ１ａに再配線３を形成し、その上を絶縁樹脂６で覆い、絶縁樹脂６には外部接続端子４を形成する位置と、半導体チップ１ｂを実装するためのバンプ８に対応した位置に開口を設け、再配線３と外部接続端子４であるハンダバンプの双方と密着性が良好な材料によって、ランド５および電極１１を一括して形成している。そして、電極１１上には更に接合層９が形成され、半導体チップ１ｂ上に形成されたバンプ８との密着性を高めて半導体チップ１ｂを実装し、バンプ接合面は封止樹脂７により封止されている。   First, the structure shown in FIG. 3 will be described. In the semiconductor device of the second embodiment, the rewiring 3 is formed on the semiconductor chip 1a, and the insulating resin 6 covers the rewiring 3, and the external connection terminal 4 is provided on the insulating resin 6. Are formed at positions corresponding to the bumps 8 for mounting the semiconductor chip 1b and the bumps 8 for mounting the semiconductor chip 1b, and a material having good adhesion to both the rewiring 3 and the solder bumps which are the external connection terminals 4 is used. The electrodes 11 are formed collectively. A bonding layer 9 is further formed on the electrode 11, and the semiconductor chip 1 b is mounted with improved adhesion to the bumps 8 formed on the semiconductor chip 1 b, and the bump bonding surface is sealed with a sealing resin 7. Has been.

この接合層９とバンプ８の材料の組み合わせとしては、接合層９が金メッキでバンプ８が金メッキバンプ又は金スタッドバンプの組み合わせや、接合層９が錫または錫合金のハンダでバンプ８が金メッキバンプ、金スタッドバンプ、銅メッキバンプ又は銅メッキバンプに錫または錫合金を被覆したバンプなどの組み合わせが可能である。   As a combination of the material of the bonding layer 9 and the bump 8, the bonding layer 9 is gold-plated and the bump 8 is a gold-plated bump or a gold stud bump. The bonding layer 9 is tin or tin alloy solder and the bump 8 is a gold-plated bump. Combinations such as gold stud bumps, copper plated bumps, or bumps obtained by coating copper plated bumps with tin or a tin alloy are possible.

また、電極１１上には接合層９が形成されているが、ランド５を形成する材料がバンプ８との接合性にも優れている材料である場合には、接合層９は形成する必要がなく、その場合はさらにコストを低減することができる。また、接合層９を形成する場合は、半導体チップ１ｂとしては通常のワイヤボンディングによる組立を実施する配線および電極構成のチップを使用することができるため、専用設計とする必要がなく、低コストでパッケージを設計製造することができるという利点もある。   Further, although the bonding layer 9 is formed on the electrode 11, when the material for forming the land 5 is a material having excellent bonding property to the bumps 8, it is necessary to form the bonding layer 9. In this case, the cost can be further reduced. Further, when the bonding layer 9 is formed, a chip having a wiring and electrode configuration for performing assembly by normal wire bonding can be used as the semiconductor chip 1b. There is also an advantage that the package can be designed and manufactured.

また、半導体装置に生じる応力を緩和するために、図４に示すような構造を採用することもできる。この構造について説明すると、図３に示した半導体装置と同様に、半導体チップ１ａ上に再配線３を形成し、再配線３を絶縁樹脂６で覆い、所定の位置に設けた開口部にランド５を形成する。そして、図４に示す構造では、更にランド５領域に絶縁樹脂１３を所定の厚さで形成し、ランド５まで貫通するビアホールを設け、その内部を導体で埋設してビア１０を形成する。このビア１０は、その直径がランド５の直径の２分の１以下に細くすることでできるため、応力を緩和する効果があり、半導体装置の寿命を延ばすことができる。また、半導体チップ１ｂを薄くすることが困難な場合にも、ビア１０により高さを調整することができるという効果もある。   In order to relieve stress generated in the semiconductor device, a structure as shown in FIG. 4 can be employed. Explaining this structure, similarly to the semiconductor device shown in FIG. 3, the rewiring 3 is formed on the semiconductor chip 1a, the rewiring 3 is covered with the insulating resin 6, and the land 5 is formed in the opening provided at a predetermined position. Form. In the structure shown in FIG. 4, the insulating resin 13 is further formed in the land 5 region with a predetermined thickness, a via hole penetrating to the land 5 is provided, and the inside thereof is buried with a conductor to form the via 10. Since the via 10 can be formed by making its diameter thinner than one half of the diameter of the land 5, it has an effect of relieving stress and can extend the life of the semiconductor device. In addition, even when it is difficult to make the semiconductor chip 1b thin, there is an effect that the height can be adjusted by the via 10.

例えば、本願発明者の実験によれば、外部接続端子４のピッチが２００μｍ程度の場合、ランド５の直径は１２０μｍから１００μｍ程度となり、ビア１０の直径を５０μｍ程度とすることによって寿命が２倍以上に延びることをシミュレーションにより確認している。この場合、ビア１０の絶縁を弾性率の低い絶縁樹脂１３で行い保護することにより、その効果を得ることができる。   For example, according to the experiment by the present inventor, when the pitch of the external connection terminals 4 is about 200 μm, the diameter of the land 5 is about 120 μm to 100 μm, and the life of the via 10 is about 50 μm, so that the life is doubled or more. Is confirmed by simulation. In this case, the effect can be obtained by protecting the via 10 with the insulating resin 13 having a low elastic modulus.

上記説明では、ビア１０の直径は５０μｍ程度とし、ランド５の直径より細いものとしたが、ビア１０の直径はランド５の直径に略等しいものを使用しても構わない。この場合には、ビア１０と再配線３の接合強度が高くなければならず、さらに絶縁樹脂１３の弾性率を半導体チップ１ａの弾性率とほぼ同等にすることによって信頼性を維持することができる。   In the above description, the via 10 has a diameter of about 50 μm and is thinner than the land 5, but the via 10 may have a diameter substantially equal to the diameter of the land 5. In this case, the bonding strength between the via 10 and the rewiring 3 must be high, and the reliability can be maintained by making the elastic modulus of the insulating resin 13 substantially equal to the elastic modulus of the semiconductor chip 1a. .

次に、本発明の第３の実施例に係る半導体装置の製造方法について、図５及び図６を参照して説明する。図５及び図６は、第３の実施例に係る半導体装置の製造方法を示すフロー図である。なお、本実施例は、前記した第１及び第２の実施例に係る半導体装置の製造方法について記載するものである。   Next, a method for fabricating a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 5 and 6 are flowcharts showing a method for manufacturing a semiconductor device according to the third embodiment. This embodiment describes a method for manufacturing a semiconductor device according to the first and second embodiments described above.

まず、図５を参照して、本実施例の半導体装置の製造方法について説明すると、ウェハ１、２に各々半導体チップ１ａ、１ｂを作り込んだ後、半導体チップ１ａと半導体チップ１ｂと外部接続端子４との相互接続を行うための再配線３をウェハ１に形成し（Ｓ１０１）、絶縁樹脂６を塗布した後所定の開口を設けてランド５及び電極１１を形成し、必要に応じて第２の実施例で記載した接合層９を形成する（Ｓ１０２）。一方、ウェハ２には、半導体チップ１ａと接続するためのバンプ８形成した後（Ｓ１０３）、ダイシングを実施してウェハ２を分割して半導体チップ１ｂを得る（Ｓ１０４）。   First, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG. 5. After the semiconductor chips 1a and 1b are formed on the wafers 1 and 2, respectively, the semiconductor chip 1a, the semiconductor chip 1b, and the external connection terminals are formed. 4 is formed on the wafer 1 (S101). After applying the insulating resin 6, predetermined openings are provided to form the lands 5 and the electrodes 11, and the second wiring is formed if necessary. The bonding layer 9 described in the embodiment is formed (S102). On the other hand, after forming bumps 8 for connecting to the semiconductor chip 1a on the wafer 2 (S103), dicing is performed to divide the wafer 2 to obtain the semiconductor chip 1b (S104).

次に、バンプ８を形成した半導体チップ１ｂをウェハ１の所定位置に、所要の数量を順次に位置決めしてフリップチップ接合する（Ｓ１０５）。この後、封止樹脂７をバンプ８接合面に注入し、樹脂を硬化させた後（Ｓ１０６）、搭載した半導体チップ１ｂの裏面を所定の厚さとなるように研削加工する（Ｓ１０７）。そして、研削工程終了後にランド５上に外部接続端子４を形成し（Ｓ１０８）、半導体装置の外形となるように個片に切断して半導体装置が形成される（Ｓ１０９）。ここではバンプ形成はウェハ状態で行っているが、ダイシングした後にバンプ形成を行っても良い。ウェハ状態でバンプ形成を行う場合はメッキ法、もしくはスタッドバンプ法により行い、ダイシングした後にバンプを形成する場合はスタッドバンプ法を用いる。   Next, the semiconductor chip 1b on which the bumps 8 are formed is positioned at a predetermined position on the wafer 1 and the required quantity is sequentially positioned and flip-chip bonded (S105). Thereafter, the sealing resin 7 is injected into the bonding surfaces of the bumps 8 to cure the resin (S106), and then the back surface of the mounted semiconductor chip 1b is ground to a predetermined thickness (S107). Then, after the grinding process is finished, the external connection terminals 4 are formed on the lands 5 (S108), and the semiconductor device is formed by cutting into individual pieces so as to form the outer shape of the semiconductor device (S109). Here, bump formation is performed in a wafer state, but bump formation may be performed after dicing. When bump formation is performed in the wafer state, plating is performed by the stud bump method, or when bumps are formed after dicing, the stud bump method is used.

また、半導体装置を製造する他の方法について、図６を参照して説明する。まず、上述した方法と同様に、ウェハ１、２に各々半導体チップ１ａ、１ｂを作り込んだ後、半導体チップ１ａと半導体チップ１ｂと外部接続端子４との相互接続を行うための再配線３をウェハ１に形成し（Ｓ２０１）、絶縁樹脂６を塗布した後所定の開口を設けてランド５及び電極１１を形成し、必要に応じて接合層９を形成する（Ｓ２０２）。一方、ウェハ２は、半導体チップ１ａと接続するためのバンプ８を形成した後（Ｓ２０３）、図６の方法では、ダイシングの前に裏面研磨を行い、ウェハ２を所望の厚さにした後（Ｓ２０４）、ダイシングを実施して所定の大きさに切断する（Ｓ２０５）。   Another method for manufacturing a semiconductor device will be described with reference to FIG. First, in the same manner as described above, after the semiconductor chips 1a and 1b are formed on the wafers 1 and 2, respectively, the rewiring 3 for interconnecting the semiconductor chip 1a, the semiconductor chip 1b, and the external connection terminal 4 is provided. Formed on the wafer 1 (S201), the insulating resin 6 is applied, predetermined openings are provided to form the lands 5 and the electrodes 11, and the bonding layer 9 is formed as necessary (S202). On the other hand, after forming bumps 8 to be connected to the semiconductor chip 1a on the wafer 2 (S203), in the method of FIG. 6, after the back surface is polished before dicing and the wafer 2 is made to a desired thickness ( S204), dicing is performed and cutting into a predetermined size (S205).

次に、バンプ８が形成され、薄く加工された半導体チップ１ｂをウェハ１の所定位置に、所要の数量を順次に位置決めしてフリップチップ接合する（Ｓ２０６）。この後、封止樹脂７をバンプ８接合面に注入し、樹脂を硬化させた後（Ｓ２０７）、ランド５上に外部接続端子４を形成し（Ｓ２０８）、半導体装置の外形となるように個片に切断して半導体装置が形成される（Ｓ２０９）。   Next, the semiconductor chip 1b, on which the bumps 8 are formed and processed thinly, is sequentially positioned at a predetermined position on the wafer 1 and a required number is sequentially flip-chip bonded (S206). Thereafter, the sealing resin 7 is injected into the bonding surface of the bumps 8 and the resin is cured (S207), and then the external connection terminals 4 are formed on the lands 5 (S208), so that the external shape of the semiconductor device is obtained. The semiconductor device is formed by cutting into pieces (S209).

上記図５及び図６に示す２つの方法にはそれぞれ長所と短所がある。例えば、図５に示す方法では、ダイシングによって分割された半導体チップ１ｂを薄く加工する前にハンドリングしてウェハ１に実装するため、作業性が良好となるという長所があるが、半導体チップ１ｂを実装後に一括して研削するために、ウェハ１のそりやバンプ８による接合状態、また研削装置の加工精度等の影響により、半導体チップ１ｂの厚さにばらつきが生じてしまうという短所がある。一方、図６に示す方法では、半導体チップ１ｂをウェハ状態のままで研削するために厚さのばらつきを低減することができるが、薄く研削された状態でハンドリングしなければならず、作業性が低下するという欠点がある。上記どちらの方法を採用するかは、製造条件、製造装置の性能、歩留まり等を勘案して適宜選択すればよい。   Each of the two methods shown in FIGS. 5 and 6 has advantages and disadvantages. For example, the method shown in FIG. 5 has the advantage that the workability is improved because the semiconductor chip 1b divided by dicing is handled and mounted on the wafer 1 before being thinly processed, but the semiconductor chip 1b is mounted. Since the grinding is performed collectively later, there is a disadvantage in that the thickness of the semiconductor chip 1b varies due to the warp of the wafer 1, the bonding state by the bumps 8, the processing accuracy of the grinding apparatus, and the like. On the other hand, in the method shown in FIG. 6, since the semiconductor chip 1b is ground in the wafer state, the thickness variation can be reduced. However, the semiconductor chip 1b must be handled in a thinly ground state, and the workability is improved. There is a drawback of lowering. Which method is to be used may be selected as appropriate in consideration of manufacturing conditions, performance of the manufacturing apparatus, yield, and the like.

なお、上述した方法では、Ｓ１０３でウェハ２にバンプ８を形成した後に、Ｓ１０４でダイシングを実施したが、これらのステップを逆にしてダイシングを実施した後にバンプ８を形成しても良い。また、前記した第２の実施例に記載したように、ランド５形成後に応力緩和効果を高めるためにビア１０を形成する場合は、Ｓ１０７で半導体チップ１ｂを研磨した後、又は、Ｓ２０７では半導体チップ１ｂを樹脂封止した後、Ｓ１０８（Ｓ２０８）で外部接続端子４を形成する前にビア１０の形成を行えばよい。このビア１０は、通常、メッキにより形成されるが、シート状の絶縁樹脂１２に固定されたビア１０集合体を熱圧着などの方法によって貼付けて形成することもできる。   In the above-described method, the bumps 8 are formed on the wafer 2 in S103 and then dicing is performed in S104. However, the bumps 8 may be formed after performing dicing with these steps reversed. Further, as described in the second embodiment, when the via 10 is formed in order to enhance the stress relaxation effect after the land 5 is formed, the semiconductor chip 1b is polished in S107 or in S207. After the resin sealing 1b, the via 10 may be formed before the external connection terminal 4 is formed in S108 (S208). The via 10 is usually formed by plating, but the via 10 assembly fixed to the sheet-like insulating resin 12 may be attached by a method such as thermocompression bonding.

また、本実施例では半導体装置を製造する２つの方法を記載したが、本発明は上記実施例に限定されるものではなく、前記した第１及び第２の実施例に記載した半導体装置の構造を実現できる方法であればよいことは明らかであり、例えば、研削に代えて、ウェットエッチング、ドライエッチング、研磨等の手法を用いることもでき、また、ウェハ２を薄く研削する代わりに、外部接続端子４を高く形成してもよい。   In this embodiment, two methods for manufacturing a semiconductor device have been described. However, the present invention is not limited to the above embodiment, and the structure of the semiconductor device described in the first and second embodiments described above. Obviously, any method can be used as long as the method can be realized. For example, a technique such as wet etching, dry etching, or polishing can be used instead of grinding, and an external connection can be used instead of grinding the wafer 2 thinly. The terminal 4 may be formed high.

本発明は、半導体装置及びその製造方法に利用可能である。   The present invention can be used for a semiconductor device and a manufacturing method thereof.

１ａ 半導体チップ
１ｂ 半導体チップ
２ａ、２ｂ 電極パッド
３ 再配線
４ 外部接続端子
５ ランド
６ 絶縁樹脂
７ 封止樹脂
８ バンプ
９ 接合層
１０ ビア
１１ 電極
１２ 突起
１３ 絶縁樹脂
１４ 実装基板
１５ シリコン基板
１６、１６ａ、１６ｂ 半導体チップ
１７ ハンダバンプ
１８ 外部接続端子
１９ ボンディングワイヤ
２０ 接着剤
２１ 基板
２２ 封止樹脂
２３ 内部配線
２４ モールド樹脂 DESCRIPTION OF SYMBOLS 1a Semiconductor chip 1b Semiconductor chip 2a, 2b Electrode pad 3 Rewiring 4 External connection terminal 5 Land 6 Insulating resin 7 Sealing resin 8 Bump 9 Bonding layer 10 Via 11 Electrode 12 Protrusion 13 Insulating resin 14 Mounting substrate 15 Silicon substrate 16, 16a 16b Semiconductor chip 17 Solder bump 18 External connection terminal 19 Bonding wire 20 Adhesive 21 Substrate 22 Sealing resin 23 Internal wiring 24 Mold resin

Claims (5)

外部と接続するＢＧＡからなる接続端子を有する第１のチップの前記接続端子形成面と同一面に、第２のチップがバンプを介して実装されてなる半導体装置において、
前記第１のチップの実装面に対して、前記第２のチップの高さが前記接続端子よりも低く設定され、
前記第２のチップの実装面と反対側の面に、前記バンプと同じ材質の、所定の高さの複数の突起を備え、前記第１のチップの実装面に対して、前記接続端子と前記第２のチップ上の前記突起とが略等しい高さとなるように前記突起の高さが設定されることを特徴とする半導体装置。 In a semiconductor device in which a second chip is mounted via bumps on the same surface as the connection terminal forming surface of a first chip having a connection terminal made of BGA connected to the outside.
The height of the second chip is set lower than the connection terminal with respect to the mounting surface of the first chip,
A surface opposite to the mounting surface of the second chip is provided with a plurality of protrusions of the same material as the bump and having a predetermined height, and the connection terminal and the A height of the protrusion is set so that the protrusion on the second chip is substantially equal. 外部と接続するＢＧＡからなる接続端子を有する第１のチップに第２のチップが実装されてなる半導体装置において、
前記第１のチップの実装面に、前記第１のチップと前記第２のチップと前記接続端子とを相互に配線する再配線層が配設され、前記再配線層には、前記接続端子と、バンプを介して実装される前記第２のチップとが同一面内に配設され、
前記第１のチップの実装面に対して、前記第２のチップの高さが前記接続端子よりも低くなるように、前記第２のチップが薄く加工され、
前記第２のチップの実装面と反対側の面に、前記バンプと同じ材質の、所定の高さの複数の突起を備え、前記第１のチップの実装面に対して、前記接続端子と前記第２のチップ上の前記突起とが略等しい高さとなるように前記突起の高さが設定されることを特徴とする半導体装置。 In a semiconductor device in which a second chip is mounted on a first chip having a connection terminal made of BGA connected to the outside,
A rewiring layer that interconnects the first chip, the second chip, and the connection terminals is disposed on the mounting surface of the first chip, and the rewiring layer includes the connection terminals and The second chip mounted via the bumps is disposed in the same plane,
The second chip is thinly processed so that the height of the second chip is lower than the connection terminal with respect to the mounting surface of the first chip,
A surface opposite to the mounting surface of the second chip is provided with a plurality of protrusions of the same material as the bump and having a predetermined height, and the connection terminal and the A height of the protrusion is set so that the protrusion on the second chip is substantially equal. 外部と接続する接続端子を有する第１のチップに第２のチップが実装されてなる半導体装置において、
前記第１のチップの実装面に、前記第１のチップと前記第２のチップと前記接続端子とを相互に配線する再配線層と、前記再配線を覆い、前記接続端子形成領域及び前記第２のチップ実装領域に所定の開口を有する絶縁層と、前記開口に設けた下地電極とを有し、前記接続端子形成領域の前記下地電極にはＢＧＡからなる接続端子が形成され、前記第２のチップ実装領域の前記下地電極にはバンプを介して前記第２のチップがフリップチップ接続され、
前記第１のチップの実装面に対して、前記第２のチップの高さが前記接続端子よりも低くなるように、前記第２のチップが薄く加工され、
前記第２のチップの実装面と反対側の面に、前記バンプと同じ材質の、所定の高さの複数の突起を備え、前記第１のチップの実装面に対して、前記接続端子と前記第２のチップ上の前記突起とが略等しい高さとなるように前記突起の高さが設定されることを特徴とする半導体装置。 In a semiconductor device in which a second chip is mounted on a first chip having a connection terminal connected to the outside,
A rewiring layer that interconnects the first chip, the second chip, and the connection terminals to each other on the mounting surface of the first chip, covers the rewiring, and includes the connection terminal formation region and the first chip 2 having an insulating layer having a predetermined opening in the chip mounting region and a base electrode provided in the opening, wherein the base electrode in the connection terminal forming region is formed with a connection terminal made of BGA, The second chip is flip-chip connected to the base electrode in the chip mounting area via a bump,
The second chip is thinly processed so that the height of the second chip is lower than the connection terminal with respect to the mounting surface of the first chip,
A surface opposite to the mounting surface of the second chip is provided with a plurality of protrusions of the same material as the bump and having a predetermined height, and the connection terminal and the A height of the protrusion is set so that the protrusion on the second chip is substantially equal. 外部と接続する接続端子を形成する領域と第２のチップを実装する領域とが設けられた第１のチップが複数形成された第１のウェハ上に、前記第１のチップと前記第２のチップと前記接続端子とを相互に配線する再配線層を形成する工程と、前記再配線上に絶縁層を堆積し、前記接続端子形成領域及び前記第２のチップ実装領域の所定の位置に開口を形成する工程と、前記開口部に下地電極を形成する工程と、第２のウェハに対して、各々の前記第２のチップにバンプを形成する処理と前記第２のウェハをダイシングして前記第２のチップに分割する処理とを任意の順序で行う工程と、前記第２のチップを、前記第１のウェハ上の各々の前記第１のチップに順次に位置決めしてフリップチップ接合する工程と、前記第２のチップのバンプ接合面を樹脂封止する工程と、前記第１のチップの実装面に対して、前記第２のチップの高さが前記接続端子よりも低くなるように、前記第２のチップの裏面を薄く加工する工程と、前記第１のウェハ上の各々の前記第１のチップにＢＧＡからなる接続端子を形成する工程と、前記第１のウェハをダイシングして個片に分割する工程と、を少なくとも有し、
前記第２のチップの裏面を薄く加工する工程後に、前記第２のチップの裏面に前記バンプと同じ材質の、所定の高さの複数の突起を形成する工程を備え、該突起は、前記第１のチップの実装面に対して、前記接続端子と前記突起とが略等しい高さとなるように形成されることを特徴とする半導体装置の製造方法。 The first chip and the second chip are formed on a first wafer on which a plurality of first chips each having a region for forming a connection terminal connected to the outside and a region for mounting a second chip are formed. Forming a redistribution layer for interconnecting the chip and the connection terminal; and depositing an insulating layer on the redistribution and opening the connection terminal formation region and the second chip mounting region at predetermined positions Forming a base electrode in the opening, forming a bump on each second chip, and dicing the second wafer with respect to the second wafer A process of dividing the second chip into a second chip in an arbitrary order; and a process of sequentially positioning the second chip on each of the first chips on the first wafer and performing flip-chip bonding. And bump bonding of the second chip And the back surface of the second chip is processed thinly so that the height of the second chip is lower than the connection terminal with respect to the mounting surface of the first chip. And at least a step of forming connection terminals made of BGA on each of the first chips on the first wafer, and a step of dicing and dividing the first wafer into pieces. ,
After the step of thinly processing the back surface of the second chip, the method includes a step of forming a plurality of protrusions of the same material as the bumps on the back surface of the second chip and having a predetermined height. A method of manufacturing a semiconductor device, wherein the connection terminals and the protrusions are formed so as to have substantially the same height with respect to a mounting surface of one chip. 外部と接続する接続端子を形成する領域と第２のチップを実装する領域とが設けられた第１のチップが複数形成された第１のウェハ上に、前記第１のチップと前記第２のチップと前記接続端子とを相互に配線する再配線層を形成する工程と、前記再配線上に絶縁層を堆積し、前記接続端子形成領域及び前記第２のチップ実装領域の所定の位置に開口を形成する工程と、前記開口部に下地電極を形成する工程と、第２のウェハに対して、各々の前記第２のチップにバンプを形成する処理と、実装後において、前記第１のチップの実装面に対して、前記第２のチップの高さが前記接続端子よりも低くなるように、前記第２のウェハの裏面を薄く加工する処理と、前記第２のウェハをダイシングして前記第２のチップに分割する処理とを任意の順序で行う工程と、前記第２のチップを、前記第１のウェハ上の各々の前記第１のチップに順次に位置決めしてフリップチップ接合する工程と、前記第２のチップのバンプ接合面を樹脂封止する工程と、前記第１のウェハ上の各々の前記第１のチップにＢＧＡからなる接続端子を形成する工程と、前記第１のウェハをダイシングして個片に分割する工程と、を少なくとも有し、
前記第２のチップを樹脂封止する工程後に、前記第２のチップの裏面に前記バンプと同じ材質の、所定の高さの複数の突起を形成する工程を備え、該突起は、前記第１のチップの実装面に対して、前記接続端子と前記突起とが略等しい高さとなるように形成されることを特徴とする半導体装置の製造方法。 The first chip and the second chip are formed on a first wafer on which a plurality of first chips each having a region for forming a connection terminal connected to the outside and a region for mounting a second chip are formed. Forming a redistribution layer for interconnecting the chip and the connection terminal; and depositing an insulating layer on the redistribution and opening the connection terminal formation region and the second chip mounting region at predetermined positions Forming a base electrode in the opening, forming a bump on each second chip for the second wafer, and after mounting, the first chip A process of thinning the back surface of the second wafer so that the height of the second chip is lower than the connection terminal with respect to the mounting surface, and dicing the second wafer Arbitrary order of processing to divide into second chips A step of sequentially positioning the second chip on each of the first chips on the first wafer and performing flip chip bonding; and a bump bonding surface of the second chip is sealed with resin. At least a step of forming a connection terminal made of BGA on each of the first chips on the first wafer, and a step of dicing and dividing the first wafer into pieces. Have
After the step of resin-sealing the second chip, the method includes a step of forming a plurality of protrusions having a predetermined height and made of the same material as the bumps on the back surface of the second chip. A method of manufacturing a semiconductor device, wherein the connection terminals and the protrusions are formed to have substantially the same height with respect to the chip mounting surface.
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