JP3262728B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device comprising a first semiconductor chip having a first LSI and a second semiconductor chip having a second LSI connected in a face-down manner. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in order to reduce the cost and size of LSI semiconductor devices, LSIs having different functions have been developed.
There has been proposed a semiconductor device in which semiconductor chips having LSIs formed by different processes or different processes are joined by a face-down method.

Hereinafter, the conventional LSI semiconductor device will be described with reference to FIG.

First, a first internal electrode 111 and a bonding pad 112 are formed on a first semiconductor chip 110 having a first LSI, and a second LSI
A first internal electrode 121 is formed on a second semiconductor chip 120 having
The first internal electrode 111 and the second internal electrode 121 of the second semiconductor chip 120 are electrically connected to each other via a bump 122 made of solder. An insulating resin 130 is filled between the first semiconductor chip 110 and the second semiconductor chip 120, and the first semiconductor chip 110 and the second semiconductor chip 120 are
2 and an insulating resin 130.

The first semiconductor chip 110 is fixed to the die pad 131 of the lead frame with resin, and the bonding pad 11 of the first semiconductor chip 110 is fixed.
2 and the external leads 132 of the lead frame are electrically connected via bonding wires 133. First
The semiconductor chip 110, the second semiconductor chip 120, the bonding wires 133, the die pad 131, and part of the external leads 132 are packaged with a sealing resin 135.

Hereinafter, a method for manufacturing the semiconductor device will be described with reference to FIGS.

First, as shown in FIGS. 8 and 9, a first internal electrode 111 and a bonding pad 112 are formed on a first semiconductor chip 110 having a first LSI, and a second LSI Semiconductor chip 12 having
After the second internal electrode 121 is formed on the first internal electrode 121, a bump 122 made of solder is formed on the second internal electrode 121. Thereafter, the wafer on which the second semiconductor chip 120 is formed is diced, and the second semiconductor chip 12 is diced.
After separating the second semiconductor chips 120 from each other, the second semiconductor chips 120 are arranged on the wafer-shaped first semiconductor chips 110.

Next, as shown in FIG. 9, the bumps 122 of the second semiconductor chip 120 and the first semiconductor chip 110
Then, the first semiconductor chips 110 in a wafer shape are diced to separate the first semiconductor chips 110 from each other.

Next, as shown in FIG. 8, after an insulating resin 130 is filled between the first semiconductor chip 110 and the second semiconductor chip 120, the first semiconductor chip 110 is connected to a die pad of a lead frame. 131, the bonding pad 112 of the first semiconductor chip 110 and the external lead 132 of the lead frame are connected via a bonding wire 133.
When a part of the semiconductor chip 110, the second semiconductor chip 120, the bonding wires 133, the die pad 131, and the external leads 132 is packaged with the sealing resin 135, a conventional semiconductor device can be obtained.

[0010]

However, according to the conventional method for manufacturing a semiconductor device, pure water used for dicing the wafer-shaped first semiconductor chip 110 is formed by the first semiconductor chip 110 and the second semiconductor chip 110. Semiconductor chip 12
In this case, a step of removing the pure water by using an oven or the like is required. Further, the junction between the first semiconductor chip 110 and the second semiconductor chip 120 receives an in-plane shear force due to the pressure of pure water supplied when dicing the wafer-shaped first semiconductor chip 110. Silicon chips generated in the dicing process of the first semiconductor chip 110
There is a first problem in that the semiconductor device may be intruded between the semiconductor chip 10 and the second semiconductor chip 120, thereby lowering the reliability of the semiconductor device and lowering the yield.

Incidentally, in a semiconductor device in which a first semiconductor chip 110 having a first LSI and a second semiconductor chip 120 having a second LSI are connected by bumps 122, the first semiconductor chip 110 First
It is necessary to match the position of the internal electrode 111 with the position of the second internal electrode 121 of the second semiconductor chip 120. For this reason, the first LS of the first semiconductor chip 110
I and the first internal electrode 11
1 or the second semiconductor chip 120
Since the length of the wiring connecting the functional block formed in the second LSI and the second internal electrode 121 becomes long, a signal time delay occurs in the first LSI or the second LSI. I do.

Therefore, the first semiconductor chip 110
In order to reduce the length of the wiring connecting the functional block formed in the LSI and the first internal electrode 111, the first
10A, the position of the internal electrode 111 is brought closer to the position of the functional block formed in the first LSI, and the first internal electrode 111 formed in the first semiconductor chip 110 is formed as shown in FIG. Is offset from the center of the first semiconductor chip 110.

However, when the position of the first internal electrode 111 is offset with respect to the center of the first semiconductor chip 110, the position of the center of the first semiconductor chip 110 and the center of the second semiconductor chip 120 are shifted. Needs to coincide with the position, the distance from the side surface of the second semiconductor chip 120 to the outer surface of the encapsulating resin 135 differs depending on the region, and exists on the side of the second semiconductor chip 120. The amount of the sealing resin 135 differs depending on the part. Therefore, when the sealing resin 135 cures, the second
The curing shrinkage force applied to the side surface of the semiconductor chip 120 differs depending on the side surface. That is, the curing shrinkage force of the portion where the amount of the sealing resin 135 is large (the portion indicated by A in FIG. 10B) is smaller than the portion where the amount of the sealing resin 135 is small (see FIG.
(The portion indicated by B in (b)). In addition, when the semiconductor device is mounted on a printed circuit board or the like, the temperature of the sealing resin 135 rises, and the heat applied to the side surface of the second semiconductor chip 120 due to the thermal expansion of the sealing resin 135 due to the temperature rise Stress varies from side to side. That is, the portion (A) where the amount of the sealing resin 135 is large.
Is larger than the thermal stress in the portion (B) where the amount of the sealing resin 135 is small. Therefore, the second semiconductor chip 12
The curing shrinkage force and thermal stress applied to the side (a) corresponding to the portion (A) where the amount of the sealing resin 135 is large at 0 are:
The curing shrinkage force and the thermal stress applied to the side (b) corresponding to the portion (B) where the amount of the sealing resin 135 in the second semiconductor chip 120 is small are larger. Therefore, the first
Since a shearing force due to a difference in curing shrinkage force and a difference in thermal stress is applied to the joint between the semiconductor chip 110 and the second semiconductor chip 120 in the in-plane direction, the reliability of the semiconductor device is impaired and the yield is reduced. Is reduced.

In view of the above, the present invention prevents pure water from entering between the first semiconductor chip and the second semiconductor chip at the time of dicing, and eliminates the step of removing pure water using an oven or the like. The pressure of pure water supplied when dicing the first semiconductor chip is equal to that of the second semiconductor chip.
To prevent a situation in which the semiconductor chip is joined to the first semiconductor chip and a situation in which chips of the substrate generated when dicing the first semiconductor chip enter between the first semiconductor chip and the second semiconductor chip. It is a first object of the present invention to improve the reliability and yield of a device, and to reduce the curing shrinkage force and thermal stress of a package applied to a joint between a first semiconductor chip and a second semiconductor chip to reduce the reliability of the semiconductor device. A second object is to improve the performance and yield.

[0015]

In order to achieve the second object, a semiconductor device according to the present invention has a first semiconductor chip having a first LSI, a first semiconductor chip having a second LSI, and a first semiconductor chip having a first LSI. A second semiconductor chip having a chip size smaller than that of the first semiconductor chip and connected face-down to the first semiconductor chip, and a package encapsulating the first semiconductor chip and the second semiconductor chip In the first direction in which the first side having the same length or the shorter length of the two adjacent sides of the second semiconductor chip extends in the first direction. The central portion and the central portion of the second semiconductor chip are offset from each other, and the central portion of the second semiconductor chip and the central portion of the package are substantially coincident.

According to the semiconductor device of the present invention, in the first direction in which the first side having the same length or the shorter length of the two adjacent sides of the second semiconductor chip extends. Since the center of the second semiconductor chip and the center of the package are substantially coincident, the distance from the side surface of the second semiconductor chip to the outer surface of the package is substantially equal. For this reason, in the first direction, the curing shrinkage force applied to each side surface of the second semiconductor chip when the package is cured becomes substantially equal, and the second contraction force is caused by the thermal expansion of the package.
The thermal stress applied to each side surface of the semiconductor chip becomes substantially equal. However, although the curing shrinkage force and the thermal stress of the package applied to each side surface of the first semiconductor chip in the first direction are slightly different, the chip size of the first semiconductor chip is larger than the chip size of the second semiconductor chip. Therefore, in the first direction, the difference between the curing shrinkage force and the thermal stress of the package applied to the side surface of the first semiconductor chip is due to the curing shrinkage force and the thermal stress of the package applied to the side surface of the second semiconductor chip in the conventional semiconductor device. Smaller than the difference in stress.

In the semiconductor device according to the present invention, in the second direction in which the second side different from the first side extends out of the two adjacent sides of the second semiconductor chip.
It is preferable that the center of the semiconductor chip and the center of the second semiconductor chip are offset from each other, and that the center of the second semiconductor chip substantially coincides with the center of the package.

In this case, the curing shrinkage force and the thermal stress of the package applied to each side surface of the second semiconductor chip become substantially equal in the second direction.

In order to achieve the second object, a first method for manufacturing a semiconductor device according to the present invention comprises a first semiconductor chip having a first LSI, a second LSI, and a second semiconductor chip. A chip connecting step of connecting a second semiconductor chip having a chip size smaller than that of the first semiconductor chip by a face-down method;
A chip sealing step of sealing the semiconductor chip and the second semiconductor chip with a package. The chip connecting step includes the step of connecting the second semiconductor chip having the same length or the shorter one of two adjacent sides. In the first direction in which the first side having the length extends, the center of the first semiconductor chip and the center of the second semiconductor chip are offset from each other, and the center of the second semiconductor chip is Connecting the first semiconductor chip and the second semiconductor chip such that the portion substantially coincides with the center of the package.

According to the first method of manufacturing a semiconductor device, the chip connecting step is performed such that the center of the second semiconductor chip substantially coincides with the center of the package in the first direction. And a step of connecting the second semiconductor chip to the second semiconductor chip.
In the first direction, the curing shrinkage force and the thermal stress of the package applied to each side surface of the second semiconductor chip become substantially equal.

In the first method for fabricating a semiconductor device, the chip connecting step is performed in a second direction in which a second side different from the first side extends out of two adjacent sides of the second semiconductor chip. At the center of the first semiconductor chip and the second
The first semiconductor chip and the second semiconductor chip are arranged such that the center of the second semiconductor chip is offset from the center of the second semiconductor chip and the center of the package substantially coincides with the center of the package.
It is preferable to include a step of connecting the semiconductor chip to the semiconductor chip.

In this manner, in the obtained semiconductor device, the curing shrinkage force and the thermal stress of the package applied to each side surface of the second semiconductor chip become substantially equal in the second direction.

In order to achieve the first object, a second method for manufacturing a semiconductor device according to the present invention comprises a first semiconductor chip having a first LSI, a first semiconductor chip having a second LSI, and a first semiconductor chip having a second LSI. Dicing a semiconductor wafer on which a plurality of second semiconductor chips are formed, the method being directed to a method of manufacturing a semiconductor device in which a second semiconductor chip having a chip size smaller than that of the first semiconductor chip is connected in a face-down manner. A first chip separating step of separating the plurality of second semiconductor chips from each other; and a step of separating the plurality of second semiconductor chips separated from each other into a semiconductor wafer on which the plurality of first semiconductor chips are formed. A chip connecting step of connecting each of the plurality of first semiconductor chips in a face-down manner, and a plurality of first semiconductor chips and a plurality of first semiconductor chips connected to each other; A resin filling step of filling an insulating resin between the first semiconductor chips and the second semiconductor chip, and dicing the semiconductor wafer on which the plurality of first semiconductor chips are formed to form a plurality of first semiconductor chips. Second to separate from each other
Chip separation process.

According to the second method for manufacturing a semiconductor device, after the insulating resin is filled between the first semiconductor chip and the second semiconductor chip, the semiconductor wafer on which the first semiconductor chip is formed is removed. Since the first semiconductor chips are separated from each other by dicing, pure water used in the dicing step does not enter between the first semiconductor chip and the second semiconductor chip, and the water pressure at the time of dicing is reduced to the second pressure. When the semiconductor chip is added to the first semiconductor chip from the side, the joint between the first semiconductor chip and the second semiconductor chip is not damaged, and the first semiconductor chip is free from substrate waste generated during dicing. And the second semiconductor chip.

In the second method for manufacturing a semiconductor device, between the resin filling step and the second chip separating step, a surface of the second semiconductor chip opposite to the surface facing the first semiconductor chip is polished. It is preferable to further include a chip polishing step for performing the following.

In the second method for manufacturing a semiconductor device, the second semiconductor chip is provided on the surface of the first semiconductor chip facing the second semiconductor chip between the resin filling step and the second chip separating step. It is preferable that the method further includes a chip polishing step of polishing a surface of the second semiconductor chip opposite to the surface facing the first semiconductor chip after forming the surrounding resin layer.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.
2 (a) to 2 (c).

First, as shown in FIG. 1A, the first semiconductor wafers are formed on a first semiconductor wafer, and each is formed on a first LS.
A first internal electrode 11 and a bonding pad 12 made of aluminum are respectively formed on the plurality of first semiconductor chips 10 having I. In addition, aluminum is formed on a plurality of second semiconductor chips 20 formed on a second semiconductor wafer, each having a second LSI and having a smaller chip size than the first semiconductor chip 10. After forming the second internal electrode 21
A bump 22 made of solder is formed on each second internal electrode 21.

As the material of the bump 22, Au, In,
A metal such as In-Sn, Pb-Sn, Cu, or Ni can be used.
m to 100 m and a height of about 1 m to 50 m can be used. In addition, the second made of aluminum
Ni / A on the internal electrodes 21 by electroless plating or the like.
After forming a barrier metal layer (not shown) such as u, the bumps 22 can be formed on the barrier metal layer by electrolytic plating, electroless plating, dipping, transfer, or the like.

Also, instead of forming the bumps 22 on the second internal electrodes 21 of the second semiconductor chip 20, the first
A bump may be formed on the first internal electrode 11 of the semiconductor chip 10.

Next, the second semiconductor wafer on which the second semiconductor chips 20 are formed is diced to separate the plurality of second semiconductor chips 20 from each other. An insulating resin 30 made of, for example, an ultraviolet curable epoxy resin is applied to the mounting area of the semiconductor chip 20.

As the insulating resin 30, a thermosetting, ultraviolet curable or room temperature curable epoxy resin, acrylic resin, polyimide resin, urethane resin or the like can be used instead of the ultraviolet curable epoxy resin. . Also,
As a method of applying the insulating resin 30, a dispensing method, a printing method, a stamping method, or the like can be used as appropriate.

Although the insulating resin 30 is applied to the mounting area of the second semiconductor chip 20 in the first semiconductor chip 10, the insulating resin 30 may be applied to the second semiconductor chip 20 instead.

Next, the second semiconductor chip 20 is arranged on the first semiconductor chip 10 in the form of a wafer, and
After aligning the bumps 22 of the semiconductor chip 20 with the first internal electrodes 11 of the first semiconductor chip 10, the second
Is brought closer to the first semiconductor chip 10, and the bumps 22 of the second semiconductor chip 20 are brought into contact with the first internal electrodes 11 of the first semiconductor chip 10.

After the insulating resin 30 was applied to the first semiconductor chip 10, the bumps 22 of the second semiconductor chip 20 were brought into contact with the first internal electrodes 11 of the first semiconductor chip 10. However, instead of this, the second semiconductor chip 2
0 bumps 22 and the first internal electrodes 11 of the first semiconductor chip 10 are brought into contact with each other.
An insulating resin 30 may be filled between the semiconductor chip 20 and the second semiconductor chip 20.

Next, as shown in FIG. 1B, the second semiconductor chip 20 is pressed against the first semiconductor chip 10 by the pressing tool 40, and the bumps 22 of the second semiconductor chip 20 are pressed. And the first internal electrode 11 of the first semiconductor chip 10 are joined together, and the insulating resin 30 is spread between the first semiconductor chip 10 and the second semiconductor chip 20. In this way, the first semiconductor chip 10 and the second semiconductor chip 20 are temporarily fixed by the viscosity of the insulating resin 30. The pressing force by the pressing tool 40 is appropriately set to a load of 0.1 g to 20 g per one bump 22. The magnitude of the load is such that the first internal electrode 11 of the first semiconductor chip 10 The setting is made so as not to damage or change the characteristics of the transistor and the wiring formed below the first internal electrode 11.

Next, ultraviolet rays 41 are applied to the insulating resin 30.
Is irradiated from the periphery of the first semiconductor chip 10 to cure the insulating resin 30 so that the first semiconductor chip 1
0 and the second semiconductor chip 20 are integrated. UV 4
The amount of energy of 1 depends on the type of the insulating resin 30, but is usually irradiated with ultraviolet rays 41 having an irradiation amount of 200 mJ to 5000 mJ for several seconds. After that, the pressing tool 40
When the pressure is released and kept at normal temperature or under heating, the insulating resin 30 is cured. Such a process is performed on all the second semiconductor chips 20 to integrate all the second semiconductor chips 20 with the first semiconductor chips 10 in a wafer state.

When the insulating resin 30 is thermosetting, the insulating resin 30 is cured by heating the insulating resin 30 via the pressing tool 40. As a heating condition in this case, usually, after heating at a temperature of about 70 ° C. to 250 ° C. for several seconds to several tens of seconds, the pressurization by the pressurization tool 40 is released.

In the step of pressing the second semiconductor chip 20 by the pressing tool 40 and the step of curing the insulating resin 30, pressing and curing may be performed alternately for each second semiconductor chip 20. Alternatively, after applying pressure to the plurality of second semiconductor chips 20, the plurality of insulating resins 30 may be cured simultaneously.

Next, as shown in FIG. 1C, the probe terminal 42 of the prober is brought into contact with the bonding pad 12 of the first semiconductor chip 10 so that the first semiconductor chip 1
Inspection of the electrical characteristics of the first LSI and the second LSI of the second semiconductor chip 20 is performed simultaneously.

Next, as shown in FIG. 2A, the back surfaces of the plurality of second semiconductor chips 20 are simultaneously polished while rotating the diamond wheel 43. In this case, the second
The semiconductor chip 20 is firmly fixed to the first semiconductor chip 10 in a wafer state by the insulating resin 30 and has an increased mechanical strength, and thus has an initial thickness of 400 to 680 μm. The second semiconductor chip 20 can be polished to a thickness of about 10 μm.

Instead of polishing with the diamond wheel 43, polishing with alumina or chemical polishing with a region other than the polishing region covered with resist or wax may be performed.

Further, in addition to polishing the second semiconductor chip 20, the first semiconductor chip 10 in a wafer state may be polished. In this case, since the second semiconductor chip 20 is fixed to the first semiconductor chip 10 by the insulating resin 30, the rigidity of the first semiconductor chip 10 in a wafer state is increased. 10 can be polished thinner than before. Thus, the first semiconductor chip 10 and the second semiconductor chip 2
When polishing is performed on 0, the thickness of the semiconductor device including the first semiconductor chip 10 and the second semiconductor chip 20 can be further reduced. However, if the first semiconductor chip 10 is polished too thin, the first semiconductor chip 10 may be damaged in a later dicing step for the first semiconductor wafer. The amount is limited. On the other hand, the second semiconductor chip 20 already separated by dicing can be polished to the maximum.

Next, as shown in FIG. 2B, dicing is performed on the first semiconductor wafer on which the first semiconductor chips 10 are formed.

Next, as shown in FIG. 2C, the separated first semiconductor chip 10 is fixed to the die pad 31 of the lead frame with a resin, and the first semiconductor chip 10 is bonded to the bonding pad 12 of the first semiconductor chip 10. The external leads 32 of the lead frame are connected via bonding wires 33. Then, the first semiconductor chip 10, the second semiconductor chip 20, the bonding wires 33, the die pad 31
By packaging a part of the external leads 32 with the sealing resin 35, an LSI semiconductor device in which the first semiconductor chip 10 and the second semiconductor chip 20 are integrated is obtained.

According to the method of manufacturing the semiconductor device according to the first embodiment, the space between the second semiconductor chip 20 and the first semiconductor chip 10 in the wafer state is filled with the insulating resin 30 and then the first semiconductor chip 20 is filled with the first resin. Since dicing is performed on the semiconductor chip 10, the following effects can be obtained.

First, since the pure water used in the dicing step does not enter between the first semiconductor chip 10 and the second semiconductor chip 20, the step of evaporating the pure water entering between the chips with an oven or the like is reduced. can do. However, the first semiconductor chip 10 and the second semiconductor chip 2
A step of blowing off the pure water attached to 0 is necessary, but the time required for the step of blowing off the pure water is substantially the same as the time required for cutting one semiconductor wafer. No.

Further, even if the water pressure at the time of dicing the first semiconductor chip 10 is applied to the second semiconductor chip 20 from the side, the second semiconductor chip 20 is applied to the first semiconductor chip 10 in a wafer state. Since it is fixed by the insulating resin 30, the joint between the first semiconductor chip 10 and the second semiconductor chip 20 is not damaged, so that the reliability and yield of the semiconductor device are improved.

Further, it is possible to avoid a situation in which silicon chips generated by dicing the first semiconductor chip 10 enter between the first semiconductor chip 10 and the second semiconductor chip 20.

In the first embodiment, the inspection of the electrical characteristics has been completed in a state where the second semiconductor chip 20 is joined to the first semiconductor chip 10, so that the inspection results are determined to be non-defective. Only semiconductor chip 30
In other words, since there is no need to package a defective semiconductor chip, the cost in the packaging process can be reduced.

In the first embodiment, the bonding pad 12 of the first semiconductor chip 10 in a wafer state is used.
Since the electrical characteristics are inspected by bringing the probe terminals 42 into contact with each other, a plurality of semiconductor chips can be inspected simultaneously, so that the time required for the inspection process can be reduced. The inspection of the electrical characteristics is performed by the first semiconductor chip 10.
The step may be performed before or after the step of filling the insulating resin 30 between the first semiconductor chip 20 and the second semiconductor chip 20.

(Second Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIGS. 4 (a) and (b).

As in the first embodiment, as shown in FIG. 3A, a first semiconductor chip 10 having a first LSI
After the first internal electrode 11 and the bonding pad 12 are formed on the second internal electrode 21 and the second internal electrode 21 is formed on the second semiconductor chip 20 having the second LSI, A bump 22 is formed on the electrode 21. Thereafter, the second semiconductor wafer on which the second semiconductor chip 20 is formed is diced, and the second semiconductor chip 20 is diced.
Are separated from each other, an insulating resin 30 is applied to the mounting region of the first semiconductor chip 10 on which the second semiconductor chip 20 is mounted. After that, the bump 2 of the second semiconductor chip 20 is formed.
2 is brought into contact with the first internal electrode 11 of the first semiconductor chip 10.

Next, as shown in FIG. 3B, the second semiconductor chip 20 is pressed against the first semiconductor chip 10 by the pressing tool 40, and the bumps 22 of the second semiconductor chip 20 are pressed. And the first internal electrode 11 of the first semiconductor chip 10 are joined together, and the insulating resin 30 is spread between the first semiconductor chip 10 and the second semiconductor chip 20. Then, the first semiconductor chip 10 and the second semiconductor chip 20 are integrated by irradiating the insulating resin 30 with ultraviolet rays 41 to cure the insulating resin 30.

Next, as shown in FIG. 3C, the probe terminal 42 of the prober is brought into contact with the bonding pad 12 of the first semiconductor chip 10 so that the first semiconductor chip 1
Inspection of the electrical characteristics of the first LSI and the second LSI of the second semiconductor chip 20 is performed simultaneously.

Next, as shown in FIG. 4A, the chip holding resin 44 is spread over the entire surface of the first semiconductor chip 10 in the form of a wafer to the same height as the second semiconductor chip 20. After the deposition, the back surfaces of the plurality of second semiconductor chips 20 are simultaneously polished while rotating the diamond wheel 43. In this case, since the second semiconductor chip 20 is fixed to the first semiconductor chip 10 in the wafer state by the insulating resin 30 and the chip holding resin 44, the second semiconductor chip 20 is fixed.
Of the semiconductor chip 20 can be more reliably performed. When the polishing of the second semiconductor chip 20 is completed, the chip holding resin 44 is removed by a solution. In order to prevent the insulating resin 30 from being removed when the chip-holding resin 44 is removed by the solution, the chip-holding resin 4
As 4, a resin different from the insulating resin 30 is used, and a solution that dissolves the chip holding resin 44 but does not dissolve the insulating resin 30 is used as the solution.

Next, as shown in FIG. 4B, after dicing is performed on the first semiconductor wafer on which the first semiconductor chips 10 are formed, the separated first semiconductor chips 10 are formed. Is fixed to the die pad 31 of the lead frame, and the bonding pad 12 of the first semiconductor chip 10 is connected to the external lead 32 of the lead frame via the bonding wire 33. Thereafter, the first semiconductor chip 10 When the semiconductor chip 20, the bonding wire 33, the die pad 31, and a part of the external lead 32 are packaged with the sealing resin 35, FIG.
The semiconductor device as shown in FIG.

(Third Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described.
This will be described with reference to FIGS. 5A to 5C and FIGS. 6A and 6B.

As in the first embodiment, as shown in FIG. 5A, a first internal electrode 11 and a bonding pad 12 are formed on a square first semiconductor chip 10 having a first LSI. After forming the second internal electrode 21 on the square second semiconductor chip 20 having the second LSI and having a smaller chip size than the first semiconductor chip 10, the second internal electrode 21 is formed. The bump 22 is formed on the internal electrode 21. In this case, the distance between the functional block of the first LSI and the first internal electrode 11 is reduced,
In order to reduce the signal delay time in the LSI described above, the first internal electrode 11 is offset, for example, to the left with respect to the center of the first semiconductor chip 10.

Next, the second semiconductor wafer on which the second semiconductor chips 20 are formed is diced to separate the second semiconductor chips 20 from each other. An insulating resin 30 is applied to a mounting area of the chip 20. Since the first internal electrode 11 is offset to the left with respect to the center of the first semiconductor chip 10, the application region of the insulating resin 30 is also offset to the left with respect to the center of the first semiconductor chip 10. are doing.

Next, the second semiconductor chip 20 is arranged on the first semiconductor chip 10 in the form of a wafer, and
After aligning the bumps 22 of the semiconductor chip 20 with the first internal electrodes 11 of the first semiconductor chip 10, the second
The bumps 22 of the semiconductor chip 20 and the first internal electrodes 11 of the first semiconductor chip 10 are brought into contact with each other. Thus, the center of the second semiconductor chip 20 is offset to the left with respect to the center of the first semiconductor chip 10.

Next, as shown in FIG. 5B, the second semiconductor chip 20 is pressed against the first semiconductor chip 10 by the pressing tool 40, and the bumps 22 of the second semiconductor chip 20 are pressed. And the first internal electrode 11 of the first semiconductor chip 10 are joined together, and the insulating resin 30 is spread between the first semiconductor chip 10 and the second semiconductor chip 20. Then, the first semiconductor chip 10 and the second semiconductor chip 20 are integrated by irradiating the insulating resin 30 with ultraviolet rays 41 to cure the insulating resin 30.

Next, as shown in FIG. 5C, the probe terminal 42 of the prober is brought into contact with the bonding pad 12 of the first semiconductor chip 10 so that the first semiconductor chip 1
Inspection of the electrical characteristics of the first LSI and the second LSI of the second semiconductor chip 20 is performed simultaneously. Thereafter, although not shown, the back surfaces of the plurality of second semiconductor chips 20 are polished.

Next, as shown in FIG. 6A, dicing is performed on the first semiconductor wafer on which the first semiconductor chips 10 are formed, so that the first semiconductor chips 10 are formed.
Is separated. Then, the separated first semiconductor chip 1
0 is fixed to the die pad 31 of the lead frame, and the bonding pad 12 of the first semiconductor chip 10 is connected to the external lead 32 of the lead frame via the bonding wire 33. Thereafter, as shown in FIG. 6B, the first semiconductor chip 10 and the second semiconductor chip 2
A part of the bonding wire 33, the die pad 31, and the external lead 32 is packaged with a square sealing resin 35. In this case, the center of the second semiconductor chip 20 and the center of the sealing resin 35 substantially match, while the center of the first semiconductor chip 10 is
Package so that it is offset to the right with respect to the center of

The following two methods are used to fix the first semiconductor chip 10 to the die pad 31 of the lead frame.
One of the two methods can be appropriately selected. In other words, by making the length of the inner lead of the lead frame different on the left and right,
The die pad 31 may be provided so as to be offset to the right with respect to the center of the lead frame, and the first semiconductor chip 10 may be mounted such that the center of the first semiconductor chip 10 and the center of the die pad 31 coincide. Then, as shown in FIG. 6B, the die pad 31 is provided so as to be located at the center of the lead frame, and the center of the first semiconductor chip 10 is located on the right side with respect to the center of the die pad 31. May be placed so as to be offset.

The offset amount between the center of the first semiconductor chip 10 and the center of the sealing resin 35 can be set as follows, for example. That is, when the size of the first semiconductor chip 10 is 10 mm square, the size of the second semiconductor chip 20 is 4 mm square, and the size of the sealing resin 35 is 16 mm square, the center of the second semiconductor chip 20 is The central part of the first semiconductor chip 10 is offset by 1 mm from the central part of the sealing resin 35 while the central part of the first semiconductor chip 10 is aligned with the central part of the sealing resin 35. In this case, the first
The distance from the side surface of the semiconductor chip 10 to the side surface of the sealing resin 35 is 2 mm and 4 mm, respectively.

According to the semiconductor device of the third embodiment, the central portion of the second semiconductor chip 20 and the sealing resin 35
Are substantially the same, the distance from the side surface of the second semiconductor chip 20 to the outer surface of the sealing resin 35 is equal on the left and right. For this reason, the curing shrinkage force applied to the side surface of the second semiconductor chip 20 when the sealing resin 35 is cured becomes equal on both the left and right sides, and the second semiconductor chip 20 is thermally expanded with the sealing resin 35. The thermal stress applied to the side surface of each side 20 is also equal on both the left and right sides.

However, since the center of the first semiconductor chip 10 is offset with respect to the center of the sealing resin 35, the side surface of the first semiconductor chip 10 is hardened when the sealing resin 35 is cured. The curing shrinkage force applied to the left and right sides is different between the left and right sides, and the first is caused by the thermal expansion of the sealing resin 35.
The thermal stress applied to the side surface of the semiconductor chip 10 also differs between the left and right sides.

However, since the chip size of the first semiconductor chip 10 is larger than the chip size of the second semiconductor chip 20, the amount of the sealing resin 30 present on the side of the first semiconductor chip 10 is Second semiconductor chip 20
10 is smaller than the amount of the sealing resin 30 existing on the side of the first semiconductor chip 10, the difference between the curing shrinkage force and the thermal stress of the sealing resin 35 applied to the left and right side surfaces of the first semiconductor chip 10 is shown in FIG. Second semiconductor chip 12 in the shown conventional semiconductor device
0 is smaller than the difference between the curing shrinkage force and the thermal stress of the sealing resin 135 applied to the left and right side surfaces. Therefore, the first semiconductor chip 10 and the second semiconductor chip 20 are connected to each other at the joint between the first semiconductor chip 10 and the second semiconductor chip 20 due to the difference between the curing shrinkage force and the thermal stress of the sealing resin 35. The shearing force applied to the joint with the chip 20 from the in-plane direction is reduced as compared with the conventional case.

In the third embodiment, the first semiconductor chip 10, the second semiconductor chip 20, and the sealing resin 3
The plane shapes of 0 are each square, but may be rectangular as shown in FIG. When the second semiconductor chip 20 has a rectangular shape, the center of the first semiconductor chip 10 and the center of the second semiconductor chip 20 are mutually separated in the direction in which the short side of the second semiconductor chip 20 extends. It is preferable that the center portion of the second semiconductor chip 20 and the center portion of the sealing resin 30 substantially coincide with each other while being offset. That is, it is preferable that X ₁ and X ₂ in FIG. 7 are equal. By doing so, there is no difference between the curing shrinkage force and the thermal stress of the sealing resin 30 applied to the left and right side surfaces in FIG. 7 of the second semiconductor chip 20. In this case, although different from the Y ₁ and Y ₂ in FIG. 7, the amount of the sealing resin 30 present in the lateral direction in FIG. 7, the amount of the sealing resin 30 present in the vertical direction in FIG. 7 As compared with the above, the influence of the difference between the curing shrinkage force and the thermal stress of the package applied to the short side surface of the second semiconductor chip 20 is small. However, when the second semiconductor chip 20 is rectangular, the center of the second semiconductor chip 20 and the center of the encapsulating resin 30 may be in the direction in which the long side of the second semiconductor chip 20 extends. Are almost the same, that is, Y ₁
And Y ₂ are preferably equal.

In the first to third embodiments, the type of the package of the semiconductor device is not particularly limited, and a QFP type, a PGA type, a BGA type, or the like can be appropriately adopted, and the package material can be used. In place of the sealing resin, a sealing ceramic or the like can be used as appropriate.

[0072]

According to the semiconductor device of the present invention, the second
A center portion of the second semiconductor chip and a center portion of the package in a first direction in which a first side having the same length or a shorter length of two adjacent sides of the semiconductor chip extends. Are almost the same, the shearing force applied from the in-plane direction to the junction between the first semiconductor chip and the second semiconductor chip due to the difference between the curing shrinkage force and the thermal stress of the package is smaller than that in the related art. As a result, the reliability and yield of the semiconductor device are improved.

In the semiconductor device according to the present invention, the second side in the second direction in which the second side different from the first side out of the two sides adjacent to each other of the second semiconductor chip extends.
When the center of the semiconductor chip and the center of the package substantially coincide with each other, the difference between the curing shrinkage force and the thermal stress of the package applied to each side surface of the second semiconductor chip in the second direction is different from that of the related art. As a result, the reliability and the yield of the semiconductor device are further improved.

According to the first method of manufacturing a semiconductor device of the present invention, in the chip connecting step, the center of the first semiconductor chip and the center of the second semiconductor chip are offset from each other in the first direction. And the step of connecting the first semiconductor chip and the second semiconductor chip such that the center of the second semiconductor chip and the center of the package substantially coincide with each other. According to the method, the shear force applied from the in-plane direction to the joint between the first semiconductor chip and the second semiconductor chip is reduced as compared with the conventional case, so that the reliability and the yield of the semiconductor device are improved.

In the first method for manufacturing a semiconductor device, the chip connecting step may include the step of connecting the center of the first semiconductor chip and the second semiconductor in a second direction in which the second side of the second semiconductor chip extends. Connecting the first semiconductor chip and the second semiconductor chip so that the center of the chip is offset from each other and the center of the second semiconductor chip is substantially coincident with the center of the package. Including, the first
Since the shearing force applied from the in-plane direction to the joint between the semiconductor chip and the second semiconductor chip is further reduced as compared with the related art, the reliability and yield of the semiconductor device are further improved.

According to the second method for manufacturing a semiconductor device, since the pure water used in the dicing step does not enter between the first semiconductor chip and the second semiconductor chip, the first semiconductor chip and the second Since a step of evaporating the pure water that has entered between the semiconductor chip and the semiconductor chip in an oven or the like becomes unnecessary, the steps and costs can be reduced. In addition, the junction between the first semiconductor chip and the second semiconductor chip is not damaged by the water pressure at the time of dicing, and debris of the substrate generated at the time of dicing is reduced by the first semiconductor chip and the second semiconductor chip. Therefore, the reliability and the yield of the semiconductor device are improved.

In the second method for manufacturing a semiconductor device, if a chip polishing step for polishing the second semiconductor chip is provided between the resin filling step and the second chip separating step, the second semiconductor chip is Since the first semiconductor chip in a wafer state is polished while being firmly fixed with an insulating resin, the mechanical strength is increased and the polishing is stabilized, and the second semiconductor chip is compared with the conventional one. Therefore, an ultra-thin LSI semiconductor device in which the first semiconductor chip and the second semiconductor chip are integrated can be obtained.

In the second method for manufacturing a semiconductor device, a resin layer surrounding the second semiconductor chip is formed between the resin filling step and the second chip separating step, and then the second semiconductor chip is polished. When the chip polishing step is provided, the mechanical strength is further increased, the polishing is more stabilized, and the second semiconductor chip can be polished thinner than before, so that a thinner LSI semiconductor device can be obtained. .

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the second embodiment.

FIGS. 5A to 5C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 6A and 6B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the third embodiment. FIGS.

FIG. 7 is a plan view showing a modification of the semiconductor device obtained by the method for manufacturing a semiconductor device according to the third embodiment.

FIG. 8 is a sectional view of a conventional semiconductor device.

FIG. 9 is a cross-sectional view showing one process of a conventional semiconductor device.

FIG. 10 is a cross-sectional view of a semiconductor device on which the present invention is based.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st semiconductor chip 11 1st internal electrode 12 Bonding pad 20 2nd semiconductor chip 21 2nd internal electrode 22 Bump 30 Insulating resin 31 Die pad 32 External lead 33 Bonding wire 35 Sealing resin 40 Pressure Tool 41 UV 42 Probe terminal 43 Diamond wheel 44 Chip holding resin

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 25/18 (56) References JP-A-5-343609 (JP, A) JP-A-6-209907 (JP, A) Kaihei 6-151701 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 25/00-25/18

Claims (4)

(57) [Claims] A first semiconductor chip having a first LSI, a second LSI having a smaller chip size than the first semiconductor chip, and a face-down method for the first semiconductor chip. And a package sealing the first semiconductor chip and the second semiconductor chip. The second semiconductor chip is connected to two sides of the second semiconductor chip adjacent to each other. In the first direction in which the first side having the same length or the shorter length extends, the center of the first semiconductor chip and the center of the second semiconductor chip are offset from each other. And a center part of the second semiconductor chip and a center part of the package substantially coincide with each other. 2. A center part of the first semiconductor chip in a second direction in which a second side different from the first side extends among two adjacent sides of the second semiconductor chip. 2. The center of the second semiconductor chip is offset from the center of the second semiconductor chip, and the center of the second semiconductor chip substantially coincides with the center of the package. 3. Semiconductor device. A first semiconductor chip having a first LSI and a second semiconductor chip having a second LSI and having a smaller chip size than the first semiconductor chip, the second semiconductor chip having a second LSI and a second semiconductor chip having a chip size smaller than the first semiconductor chip ; Two adjacent semiconductor chips
The first side having the same length or the shorter length of the sides
The first semiconductor chip in a first direction in which
And the center of the second semiconductor chip are mutually
As offset, a chip connection step of connecting by face down method, a package the first semiconductor chip and second semiconductor chip connected to each other, said second semiconductor chip
The center of the package and the center of the package almost coincide
And a chip sealing step for sealing
A method for manufacturing a semiconductor device. 4. The method according to claim 1, wherein, in the second direction, a second side different from the first side extends out of two sides adjacent to each other of the second semiconductor chip. Connecting the first semiconductor chip and the second semiconductor chip so that the center of the semiconductor chip and the center of the second semiconductor chip are offset from each other. Item 4. The method for manufacturing a semiconductor device according to Item 3.