JP2005142452A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005142452A
JP2005142452A JP2003379224A JP2003379224A JP2005142452A JP 2005142452 A JP2005142452 A JP 2005142452A JP 2003379224 A JP2003379224 A JP 2003379224A JP 2003379224 A JP2003379224 A JP 2003379224A JP 2005142452 A JP2005142452 A JP 2005142452A
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substrate
chip
semiconductor
semiconductor device
semiconductor chip
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Yasuhiro Naka
康弘 中
Kenji Ujiie
健二 氏家
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Renesas Technology Corp
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Renesas Technology Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device to be manufactured by a batch mold wherein a substrate warping deformation is reduced before molding due to a difference in coefficients of line expansion between a semiconductor chip and a substrate. <P>SOLUTION: Adhesives are inserted so as to reduce a connection area in a connection part between the semiconductor chip and the substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置及びその製造技術に関し、特に、一括モールドにより製造される半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a technique effective when applied to a semiconductor device manufactured by batch molding.

ＣＳＰ（Ｃhip Ｓcale Ｐackage）型のような半導体装置では、近年、生産コストの削減を目的として、一括モールドによる製造方法を採用するケースが増加している。図２に、一括モールドによる製造方法の概略を示す。   In a semiconductor device such as a CSP (Chip Scale Package) type, in recent years, an increasing number of cases adopt a manufacturing method using a batch molding for the purpose of reducing production costs. In FIG. 2, the outline of the manufacturing method by collective molding is shown.

まず、大きな基板（多数個取り基板）１０上に、多数個の半導体チップ（半導体素子）１が搭載される。半導体チップ１の搭載は、１例としては、チップ裏面を接着材を使用して加熱接着した後、ワイヤボンディングにより基板１０との電気的接続を図ることにより行われる。他の例としては、あらかじめはんだバンプまたはＡｕバンプなどが取付けられた半導体チップ１を、リフロー、加熱圧着、または、ＡＣＦ（Ａnisotropic Ｃonductive Ｆilm）やＮＣＦ（Ｎon−Ｃonductive Ｆilm）のような接着材を用いた加熱接着により、フリップチップ接続する方法がある。リフローまたは加熱圧着による接続の場合は、接続後、半導体チップ１と基板１０の間に、アンダーフィルと呼ばれる樹脂が挿入される場合がある。チップ搭載後、モールドレジンで一括封止され、最後に切断されて、個々の半導体装置に個片化される。なお、ＢＧＡ（Ｂall Ｇrid Ａrray）型半導体装置の場合は、個片化の前に、はんだボールが取付けられる。一括モールドによる製造方法の詳細は、例えば、特開２０００−１２７４５号公報に開示されている。   First, a large number of semiconductor chips (semiconductor elements) 1 are mounted on a large substrate (multiple substrate) 10. For example, the mounting of the semiconductor chip 1 is performed by thermally bonding the back surface of the chip using an adhesive and then electrically connecting to the substrate 10 by wire bonding. As another example, the semiconductor chip 1 to which solder bumps or Au bumps are previously attached is used for reflow, thermocompression bonding, or an adhesive material such as ACF (Anisotropic Conductive Film) or NCF (Non-Conductive Film). There is a method of flip chip connection by heat bonding. In the case of connection by reflow or thermocompression bonding, a resin called underfill may be inserted between the semiconductor chip 1 and the substrate 10 after connection. After mounting the chip, it is collectively sealed with a mold resin, and finally cut and separated into individual semiconductor devices. In the case of a BGA (Ball Grid Array) type semiconductor device, a solder ball is attached before singulation. The details of the manufacturing method using the collective molding are disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-12745.

特開２０００−１２７４５公報JP 2000-12745 A

しかし、一括モールドによる製造方法を採用した場合、１個１個の半導体装置を別個に製造する場合と比較して、半導体装置多数個分の大きなサイズの基板を取り扱うことになるため、製造工程中に生じる反りが問題となる場合がある。チップ搭載工程では、いずれの接続方法でも、加熱しての接続となるため、接続後、半導体チップと基板の線膨張係数差に起因した熱変形が発生する。また、モールド工程においても、熱変形に加え、レジンの硬化収縮によって、反り変形が発生する。これらの反り変形によって、量産現場の搬送工程など、製造工程において不具合を生じる場合がある。モールド工程における反りは、レジンに含まれるシリカ粒子量を調整することにより、その線膨張係数や、硬化収縮量を比較的容易に変化させることが可能なので、これにより、ある程度、低減することが可能である。しかし、半導体チップ搭載時に生じる反りは、チップと基板との線膨張係数差が大きいため、基板の物性変更によって、反りを低減することが困難である。本発明は、特に、この半導体チップ搭載時に生じる反り変形低減を目的とする。   However, when the manufacturing method using the collective molding is adopted, a large-sized substrate corresponding to a large number of semiconductor devices is handled as compared with a case where each semiconductor device is manufactured separately. Warpage that occurs in the case may be a problem. In the chip mounting process, since any connection method is connected by heating, thermal deformation due to the difference in linear expansion coefficient between the semiconductor chip and the substrate occurs after the connection. Also in the molding process, warpage deformation occurs due to hardening shrinkage of the resin in addition to thermal deformation. These warpage deformations may cause problems in the manufacturing process such as a transfer process at a mass production site. The warpage in the molding process can be reduced to some extent by adjusting the amount of silica particles contained in the resin so that the linear expansion coefficient and the amount of cure shrinkage can be changed relatively easily. It is. However, warping that occurs when a semiconductor chip is mounted has a large difference in linear expansion coefficient between the chip and the substrate, and it is difficult to reduce the warping by changing the physical properties of the substrate. The present invention is particularly aimed at reducing the warpage deformation that occurs when the semiconductor chip is mounted.

本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。   The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

反り変形を低減する構造を検討するため、有限要素解析を実施した。図１０に示すような、対称性を考慮した１／４のモデルを使用し、環境温度を約２００℃低下させたときに発生する反り量を、弾性解析により求めた。基板の頂点（角部）を基準としたときの、基板中心部の厚さ方向の変位量を反り量と定義し、基板のチップ搭載面（素子搭載面）側が凸となる反りの場合を正の反り量とする。   Finite element analysis was performed to examine the structure that reduces warpage deformation. Using a 1/4 model considering symmetry as shown in FIG. 10, the amount of warpage generated when the environmental temperature was lowered by about 200 ° C. was obtained by elastic analysis. The amount of displacement in the thickness direction at the center of the board when the apex (corner part) of the board is used as a reference is defined as the amount of warping, and the case where the chip mounting surface (element mounting surface) side of the board is convex is positive. The amount of warpage.

反りは、半導体チップ１と基板１０の線膨張係数差に起因して生じるため、搭載するチップサイズが小さいほど、反りは小さくなるはずである。実際、図１０に示すように、搭載チップ数が同一で、搭載するチップサイズが異なる場合の反り量を比較したところ、チップサイズが大きい図１１（ａ）の構造の場合、反り量６．５ｍｍだったのに対し、基板長手方向のチップの辺の長さが約半分の図１１（ｂ）の構造の場合、反り量は３．２ｍｍと半減した。チップサイズが大きい場合でも、半導体チップ１と基板１０の接着部の面積を小さくする、即ち半導体チップ１と基板１０との間における接着材の面積を半導体チップ１の面積よりも小さくすることにより、反り低減が可能であると考えられる。   Since the warpage is caused by a difference in linear expansion coefficient between the semiconductor chip 1 and the substrate 10, the warpage should be smaller as the mounted chip size is smaller. Actually, as shown in FIG. 10, the amount of warpage when the number of mounted chips is the same and the mounted chip sizes are different is compared. As a result, in the case of the structure of FIG. On the other hand, in the case of the structure of FIG. 11B in which the length of the side of the chip in the longitudinal direction of the substrate is about half, the amount of warpage was halved to 3.2 mm. Even when the chip size is large, by reducing the area of the bonding portion between the semiconductor chip 1 and the substrate 10, that is, by reducing the area of the adhesive between the semiconductor chip 1 and the substrate 10 than the area of the semiconductor chip 1, It is considered that warpage can be reduced.

十分な反り低減のためには、チップ面積より十分小さい接着材の面積となるようにすることが好ましい。図１１等の状況を考慮すると、例えば基板長手方向の接着部長さを８０％（対チップ長手方向長さ）程度以下にすることが考えられる。反り量がある程度低減される。面積で比較する場合、例えば７０％以下程度にすることが考えられる。   In order to sufficiently reduce the warp, it is preferable that the area of the adhesive is sufficiently smaller than the chip area. Considering the situation of FIG. 11 and the like, for example, it is conceivable that the length of the bonded portion in the longitudinal direction of the substrate is about 80% (the length in the longitudinal direction of the chip) or less. The amount of warpage is reduced to some extent. When comparing by area, for example, it can be considered to be about 70% or less.

なお、チップ接着後にワイヤボンディング工程等のその後の工程での不具合を防ぐ観点では、ある程度の接着材面積を有することが好ましい。例えば、チップ面積の１０％以上程度である。   In addition, it is preferable to have a certain adhesive material area from the viewpoint of preventing problems in subsequent processes such as a wire bonding process after chip bonding. For example, it is about 10% or more of the chip area.

半導体チップ１をフリップチップで接続する場合は、半導体チップ１のバンプ配列を、なるべくチップ中央部によせることが有効である。この場合、アンダーフィルは挿入せずに、モールドすることが望ましい。   When the semiconductor chip 1 is connected by flip chip, it is effective to place the bump arrangement of the semiconductor chip 1 at the center of the chip as much as possible. In this case, it is desirable to mold without inserting the underfill.

ＡＣＦやＮＣＦなどを使用してフリップチップ接続する場合は、チップ中央部によせたバンプがある部分のみ、ＡＣＦ、ＮＣＦを挿入する。   In the case of flip chip connection using ACF, NCF or the like, ACF and NCF are inserted only in the portion where there is a bump at the center of the chip.

なお、基板形状が、図１１のような長方形の場合、長手方向の方がチップ数が多く、反り量への影響が大きいため、チップ接着面積の低減、または、バンプ配列のチップ中央部への集中は、基板長手方向の寸法、配列に関して実施する方が、より効果的である。   When the substrate shape is rectangular as shown in FIG. 11, the number of chips in the longitudinal direction is larger and the influence on the warpage amount is larger. Therefore, the chip bonding area is reduced or the bump array is arranged at the center of the chip. It is more effective to perform the concentration with respect to the dimension and arrangement in the longitudinal direction of the substrate.

次に、基板にスリットを入れ、発生したひずみを緩和させることによって、反り量を低減する方法を検討した。図１２のように、搭載チップ数１８個の場合で、スリット１６の入れ方や、半導体チップ１の配置を変えて解析を行い、反り低減のため最も効果的な方法を検討した。スリット１６を入れることによって、基板１０のひずみを緩和する効果が得られると同時に、基板１０の剛性が低下するため、スリット１６の数や大きさが増加した結果、逆に反りが増加する場合もあるので、構造検討には注意が必要である（例えば、図１２（ｂ）から（ｃ），（ｄ）から（ｅ），（ｇ）から（ｆ）の変化）。   Next, a method for reducing the amount of warpage was studied by making slits in the substrate and reducing the generated strain. As shown in FIG. 12, in the case of 18 mounted chips, analysis was performed by changing the way of inserting the slits 16 and the arrangement of the semiconductor chip 1, and the most effective method for reducing warpage was examined. By inserting the slits 16, the effect of alleviating the distortion of the substrate 10 can be obtained, and at the same time, the rigidity of the substrate 10 is reduced, and as a result, the number of slits 16 and the size thereof are increased. Therefore, attention must be paid to the structural examination (for example, changes from FIG. 12B to (c), (d) to (e), and (g) to (f)).

最も反り低減に効果的だったのは、図１２（ｆ）〜（ｈ）のように、半導体チップ１を基板１０の両端に配置し、中央部には半導体チップ１を搭載しない場合であった。図１３に、図１２（ｇ）の線分Ａ−Ｂ断面の変形を示すように、半導体チップ１が搭載されない部分は平坦に近い形状となっており、事実上、基板サイズを小さくしたのと同様の効果が得られたものと考える。特に、図１２（ｈ）のように、中央部のチップが搭載されない部分にはスリットを設けず、それ以外の基板両端の余白部にスリットを入れた構造の場合、最も反り変形が低減された。これは、スリットのない基板中央部の剛性が、スリットのある基板両端部よりも相対的に剛性が高いため、基板中央部によって基板両端部の変形が抑制されるためと考えられる。そのため、搭載チップ数２４個の場合、反りを最小とする最適スリット構造、チップ配置は、図１４のように、できるだけ半導体チップ１を基板両端によせ、半導体チップ１が搭載されない部分以外にスリット１６を設けた構造となる。   The most effective way to reduce the warp was when the semiconductor chips 1 were arranged at both ends of the substrate 10 and the semiconductor chip 1 was not mounted at the center as shown in FIGS. . As shown in FIG. 13 which is a modification of the cross section taken along line AB in FIG. 12 (g), the portion where the semiconductor chip 1 is not mounted has a nearly flat shape, and the substrate size is effectively reduced. I think that the same effect was acquired. In particular, as shown in FIG. 12 (h), in the case where the slit is not provided in the portion where the chip in the central portion is not mounted and the slit is provided in the blank portion at the other end of the substrate, the warp deformation is reduced most. . This is presumably because the rigidity of the central part of the substrate without slits is relatively higher than that of both ends of the substrate with slits, so that deformation of both ends of the substrate is suppressed by the central part of the substrate. Therefore, in the case where the number of mounted chips is 24, the optimum slit structure and the chip arrangement that minimize the warp are as shown in FIG. 14, with the semiconductor chip 1 as far as possible from both ends of the substrate as shown in FIG. It becomes the structure which provided.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。   The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

本発明によれば、半導体装置の製造における基板の反り変形を低減することが可能となる。   According to the present invention, it is possible to reduce warping deformation of a substrate in manufacturing a semiconductor device.

以下、図面を参照して、一括モールドにより製造される半導体装置に本発明を適用した実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。   Hereinafter, an embodiment in which the present invention is applied to a semiconductor device manufactured by batch molding will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

（実施形態１）
本実施形態１では、接着材の大きさを工夫して、樹脂封止前の基板反り変形を低減した例について説明する。 (Embodiment 1)
In the first embodiment, an example in which the size of the adhesive material is devised to reduce the warpage deformation of the substrate before resin sealing will be described.

図１は、本実施形態１の半導体装置の内部構造を示す図（（ａ）は模式的断面図，（ｂ）は模式的平面図）であり、
図２は、一括モールドによる半導体装置の製造概要を示す模式図であり、
図３は、本実施形態１の半導体装置の製造に使用される基板（多数個取り基板）の概略構成を示す模式的平面図であり、
図４は、本実施形態１の半導体装置の製造において、基板のチップ搭載領域に接着材を配置した状態を示す模式的平面図であり、
図５は、本実施形態１の半導体装置の製造において、基板のチップ搭載領域に半導体チップを搭載した状態を示す模式的平面図であり、
図６は、本実施形態１の半導体装置の製造において、基板のチップ搭載領域に半導体チップを搭載した状態を示す模式的断面図であり、
図７は、本実施形態１の半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図であり、
図８は、本実施形態１の半導体装置の製造において形成された樹脂封止体を示す模式的平面図であり、
図９は、本実施形態１の半導体装置の製造において、切断工程を示す模式的平面図である。 1A and 1B are views ((a) is a schematic cross-sectional view, and (b) is a schematic plan view) showing an internal structure of the semiconductor device of Embodiment 1. FIG.
FIG. 2 is a schematic diagram showing an outline of manufacturing a semiconductor device by batch molding.
FIG. 3 is a schematic plan view showing a schematic configuration of a substrate (multiple substrate) used for manufacturing the semiconductor device of Embodiment 1.
FIG. 4 is a schematic plan view showing a state in which an adhesive is arranged in the chip mounting region of the substrate in the manufacture of the semiconductor device of Embodiment 1.
FIG. 5 is a schematic plan view showing a state in which a semiconductor chip is mounted on a chip mounting region of a substrate in the manufacture of the semiconductor device of Embodiment 1.
FIG. 6 is a schematic cross-sectional view showing a state in which a semiconductor chip is mounted on a chip mounting region of a substrate in the manufacture of the semiconductor device of Embodiment 1.
FIG. 7 is a schematic plan view showing a wire bonding step in the manufacture of the semiconductor device of Embodiment 1.
FIG. 8 is a schematic plan view showing a resin sealing body formed in the manufacture of the semiconductor device of Embodiment 1.
FIG. 9 is a schematic plan view showing a cutting process in the manufacture of the semiconductor device of the first embodiment.

図１（ａ），（ｂ）に示すように、本実施形態１の半導体装置は、インターポーザと呼称される配線基板３の主面３ｘに半導体チップ（半導体素子）１を搭載し、配線基板３の主面３ｘと反対側の裏面に突起状電極として例えばボール状の半田バンプ６を複数配置したパッケージ構造になっている。   As shown in FIGS. 1A and 1B, the semiconductor device according to the first embodiment has a semiconductor chip (semiconductor element) 1 mounted on a main surface 3x of a wiring board 3 called an interposer. The package structure has a plurality of, for example, ball-shaped solder bumps 6 arranged as protruding electrodes on the back surface opposite to the main surface 3x.

半導体チップ１は、厚さ方向と交差する平面形状が方形状になっており、本実施形態１では例えば正方形になっている。半導体チップ１は、これに限定されないが、主に、半導体基板、この半導体基板の主面に形成された複数のトランジスタ素子、前記半導体基板の主面上において絶縁層、配線層の夫々を複数段積み重ねた多層配線層、この多層配線層を覆うようにして形成された表面保護膜（最終保護膜）等を有する構成になっている。半導体基板は、例えば単結晶シリコンで形成されている。絶縁層は、例えば酸化シリコン膜で形成されている。配線層は、例えばアルミニウム（Ａｌ）、又はアルミニウム合金、又は銅（Ｃｕ）、又は銅合金等の金属膜で形成されている。表面保護膜は、例えば、酸化シリコン膜又は窒化シリコン膜等の無機絶縁膜及び有機絶縁膜を積み重ねた多層膜で形成されている。   The semiconductor chip 1 has a square planar shape that intersects the thickness direction, and is, for example, a square in the first embodiment. Although not limited to this, the semiconductor chip 1 mainly includes a semiconductor substrate, a plurality of transistor elements formed on the main surface of the semiconductor substrate, and a plurality of stages of insulating layers and wiring layers on the main surface of the semiconductor substrate. The multilayer wiring layers are stacked, and a surface protective film (final protective film) is formed so as to cover the multilayer wiring layers. The semiconductor substrate is made of, for example, single crystal silicon. The insulating layer is made of, for example, a silicon oxide film. The wiring layer is formed of a metal film such as aluminum (Al), an aluminum alloy, copper (Cu), or a copper alloy. The surface protective film is formed of, for example, a multilayer film in which an inorganic insulating film and an organic insulating film such as a silicon oxide film or a silicon nitride film are stacked.

半導体チップ１は、互いに反対側に位置する主面（回路形成面）１ｘ及び裏面を有し、半導体チップ１の主面１ｘ側には集積回路が形成されている。この集積回路は、主に、半導体基板の主面に形成されたトランジスタ素子、及び多層配線層に形成された配線によって構成されている。   The semiconductor chip 1 has a main surface (circuit forming surface) 1x and a back surface located on opposite sides, and an integrated circuit is formed on the main surface 1x side of the semiconductor chip 1. This integrated circuit is mainly composed of transistor elements formed on the main surface of the semiconductor substrate and wirings formed on the multilayer wiring layer.

半導体チップ１の主面１ｘには、接続部として例えば複数の電極パッド１ａが形成されている。この複数の電極パッド１ａは、例えば半導体チップ１の各辺に沿って配置されている。   On the main surface 1x of the semiconductor chip 1, for example, a plurality of electrode pads 1a are formed as connection portions. The plurality of electrode pads 1a are arranged along each side of the semiconductor chip 1, for example.

配線基板３は、その厚さ方向と交差する平面形状が方形状になっており、本実施形態１では例えば正方形になっている。配線基板３は、これに限定されないが、例えば、コア材と、このコア材の主面を覆うようにして形成された第１の保護膜と、このコア材の主面と反対側の裏面を覆うようにして形成された第２の保護膜とを有する構成になっている。コア材は、例えば、その主面、裏面及び内部に配線を有する多層配線構造になっている。コア材の各絶縁層は、例えばガラス繊維にエポキシ系、若しくはポリイミド系の樹脂を含浸させた高弾性樹脂基板で形成されている。コア材の各配線層は、例えば、Ｃｕを主成分とする金属膜で形成されている。第１の保護膜は、主にコア材の主面に形成された最上層の配線を保護する目的で形成され、第２の保護膜は、主にコア材の裏面に形成された最下層の配線を保護する目的で形成されている。第１及び第２の保護膜としては、例えば絶縁性の樹脂膜が用いられている。   The wiring board 3 has a square planar shape that intersects with the thickness direction, and is, for example, a square in the first embodiment. The wiring board 3 is not limited to this, but includes, for example, a core material, a first protective film formed so as to cover the main surface of the core material, and a back surface opposite to the main surface of the core material. The second protective film is formed to cover the second protective film. The core material has, for example, a multilayer wiring structure having wiring on its main surface, back surface, and inside. Each insulating layer of the core material is formed of, for example, a highly elastic resin substrate in which glass fiber is impregnated with epoxy resin or polyimide resin. Each wiring layer of the core material is formed of, for example, a metal film containing Cu as a main component. The first protective film is formed mainly for the purpose of protecting the uppermost layer wiring formed on the main surface of the core material, and the second protective film is formed on the lowermost layer formed mainly on the back surface of the core material. It is formed for the purpose of protecting the wiring. As the first and second protective films, for example, insulating resin films are used.

配線基板３の主面３ｘにはチップ搭載領域（素子搭載領域）が配置され、このチップ搭載領域には接着材２を介在して半導体チップ１の裏面が接着固定されている。また、配線基板３の主面３ｘには、接続部として例えば複数の電極パッド３ａが配置されている。本実施形態１において、複数の電極パッド３ａは半導体チップ１（チップ搭載領域）の周囲に配置されている。また、配線基板３の裏面には、接続部として複数の電極パッド（図示せず）が配置され、この複数の電極パッドには半田バンプ６が夫々固着されている。   A chip mounting area (element mounting area) is disposed on the main surface 3x of the wiring board 3, and the back surface of the semiconductor chip 1 is bonded and fixed to the chip mounting area with an adhesive 2 interposed therebetween. Further, on the main surface 3x of the wiring board 3, for example, a plurality of electrode pads 3a are arranged as connection portions. In the first embodiment, the plurality of electrode pads 3a are arranged around the semiconductor chip 1 (chip mounting region). In addition, a plurality of electrode pads (not shown) are arranged on the back surface of the wiring board 3 as connection portions, and solder bumps 6 are fixed to the plurality of electrode pads, respectively.

半導体チップ１の複数の電極パッド１ａは、配線基板３の複数の電極パッド３ａと夫々電気的に接続されている。本実施形態１において、半導体チップ１の電極パッド１ａと配線基板３の電極パッド３ａとの電気的な接続は、ボンディングワイヤ５で行われている。ボンディングワイヤ５の一端部側は、半導体チップ１の電極パッド１ａに接続され、ボンディングワイヤ５の一端部側と反対側の他端部側は、配線基板３のパッド３ａに接続されている。すなわち、本実施形態１の半導体装置は、ワイヤボンディング構造になっている。   The plurality of electrode pads 1 a of the semiconductor chip 1 are electrically connected to the plurality of electrode pads 3 a of the wiring substrate 3, respectively. In the first embodiment, the electrical connection between the electrode pad 1 a of the semiconductor chip 1 and the electrode pad 3 a of the wiring substrate 3 is performed by the bonding wire 5. One end of the bonding wire 5 is connected to the electrode pad 1 a of the semiconductor chip 1, and the other end of the bonding wire 5 opposite to the one end is connected to the pad 3 a of the wiring substrate 3. That is, the semiconductor device according to the first embodiment has a wire bonding structure.

ボンディングワイヤ５としては、例えば金（Ａｕ）ワイヤを用いている。また、ボンディングワイヤ５の接続方法としては、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング法を用いている。   For example, a gold (Au) wire is used as the bonding wire 5. Further, as a method for connecting the bonding wires 5, for example, a nail head bonding method using ultrasonic vibration in combination with thermocompression bonding is used.

半導体チップ１、複数のボンディングワイヤ５等は、配線基板３の主面３ｘ側に選択的に形成された樹脂封止体４によって樹脂封止されている。樹脂封止体４は、低応力化を図る目的として、例えば、フェノール系硬化剤、シリコーンゴム及びフィラー（例えばシリカ）等が添加されたビフェニール系の熱硬化性樹脂で形成されている。樹脂封止体４の形成方法としては、大量生産に好適なトランスファ・モールド法を用いている。トランスファモールド法は、ポット、ランナー、樹脂注入ゲート、及びキャビティ等を備えた成形金型（モールド金型）を使用し、ポットからランナー及び樹脂注入ゲートを通してキャビティの内部に熱硬化性樹脂を注入して樹脂封止体を形成する方法である。   The semiconductor chip 1, the plurality of bonding wires 5, and the like are sealed with a resin sealing body 4 that is selectively formed on the main surface 3 x side of the wiring board 3. For the purpose of reducing the stress, the resin sealing body 4 is formed of, for example, a biphenyl-based thermosetting resin to which a phenol-based curing agent, silicone rubber, filler (for example, silica) and the like are added. As a method of forming the resin sealing body 4, a transfer mold method suitable for mass production is used. The transfer mold method uses a molding die (molding die) having a pot, a runner, a resin injection gate, and a cavity, and injects a thermosetting resin from the pot into the cavity through the runner and the resin injection gate. This is a method for forming a resin sealing body.

樹脂封止体４及び配線基板３は、ほぼ同一の平面サイズになっており、樹脂封止体４及び配線基板３の側面は面一になっている。本実施形態１の半導体装置は、後で詳細に説明するが、複数の製品形成領域を有する多数個取り基板（マルチ配線基板）を使用し、この多数個取り基板の複数の製品形成領域に実装された複数の半導体チップを一括して樹脂封止する樹脂封止体（一括用樹脂封止体）を形成した後、前記多数個取り基板及び一括用樹脂封止体を複数の個片に分割することによって製造される。   The resin sealing body 4 and the wiring board 3 have substantially the same planar size, and the side surfaces of the resin sealing body 4 and the wiring board 3 are flush with each other. As will be described in detail later, the semiconductor device according to the first embodiment uses a multi-piece substrate (multi-wiring board) having a plurality of product formation regions and is mounted on the plurality of product formation regions of the multi-piece substrate. After forming a resin encapsulant (collective resin encapsulant) that collectively encapsulates a plurality of semiconductor chips, the multi-chip substrate and the encapsulated resin encapsulant are divided into a plurality of pieces. Manufactured by doing.

配線基板３の主面３ｘと半導体チップ１との間における接着材２の面積は、半導体チップ１の面積よりも小さくなっている。本実施形態１において、接着材２は、半導体チップ１の周縁（側面）よりも内側に配置されており、半導体チップ１の裏面（接着面）の全面とは接触せず、半導体チップ１の裏面の中央部付近のみ接触している。   The area of the adhesive 2 between the main surface 3x of the wiring board 3 and the semiconductor chip 1 is smaller than the area of the semiconductor chip 1. In the first embodiment, the adhesive 2 is disposed on the inner side of the periphery (side surface) of the semiconductor chip 1, does not contact the entire back surface (adhesion surface) of the semiconductor chip 1, and is the back surface of the semiconductor chip 1. It is in contact only near the center of.

配線基板３の主面３ｘと半導体チップ１との間は、接着材２が設けられた第１の領域（接着材充填領域）と、樹脂封止体４の樹脂が設けられた第２の領域（封止樹脂充填領域）とを有する構成になっている。本実施形態１において、第１の領域（接着材充填領域）は、第２の領域（封止樹脂充填領域）で周囲を囲まれている。   Between the main surface 3x of the wiring board 3 and the semiconductor chip 1, a first region where the adhesive 2 is provided (adhesive filling region) and a second region where the resin of the resin sealing body 4 is provided. (Sealing resin filling region). In the first embodiment, the first region (adhesive filling region) is surrounded by the second region (sealing resin filling region).

次に、本実施形態１の半導体装置の製造に使用される多数個取り基板（マルチ配線基板）について説明する。   Next, a multi-piece substrate (multi-wiring substrate) used for manufacturing the semiconductor device according to the first embodiment will be described.

図３に示すように、多数個取り基板１０は、その厚さ方向と交差する平面形状が方形状になっており、本実施形態１では長方形になっている。多数個取り基板１０の主面（チップ搭載面）にはモールド領域１１が設けられ、このモールド領域１１の中には複数の製品形成領域（デバイス形成領域）１３が設けられ、この各々の製品形成領域１３の中にはチップ搭載領域１４が設けられている。半導体装置の製造において、各々のチップ搭載領域１４には、半導体チップ（１）が搭載され、モールド領域１１には、各々のチップ搭載領域１４に搭載された複数の半導体チップ（１）を一括して樹脂封止する樹脂封止体（１５）が形成される。ここで、チップ搭載領域１４の外形サイズは、そこに搭載される半導体チップ１の外形サイズを意味する。   As shown in FIG. 3, the multi-chip substrate 10 has a square shape that intersects the thickness direction thereof, and is rectangular in the first embodiment. A mold region 11 is provided on the main surface (chip mounting surface) of the multi-cavity substrate 10, and a plurality of product formation regions (device formation regions) 13 are provided in the mold region 11. A chip mounting area 14 is provided in the area 13. In the manufacture of a semiconductor device, a semiconductor chip (1) is mounted on each chip mounting area 14, and a plurality of semiconductor chips (1) mounted on each chip mounting area 14 are bundled in a mold area 11. Thus, a resin sealing body (15) for resin sealing is formed. Here, the outer size of the chip mounting area 14 means the outer size of the semiconductor chip 1 mounted thereon.

各製品形成領域１３は、分離領域１２によって区画され、基本的に図１に示す配線基板３と同様の構造及び平面形状になっている。配線基板３は、多数個取り基板１０の複数の製品形成領域１３を各々個片化することによって形成される。本実施形態１において、多数個取り基板１０は、これに限定されないが、例えば、Ｘ方向に６個，Ｙ方向に３個の行列配置（６×３）で配置された計１８個の製品形成領域１３を有する構成になっている。   Each product formation region 13 is partitioned by a separation region 12 and has basically the same structure and planar shape as the wiring board 3 shown in FIG. The wiring board 3 is formed by dividing each of the plurality of product forming regions 13 of the multi-piece substrate 10 into individual pieces. In the first embodiment, the multi-cavity substrate 10 is not limited to this. For example, a total of 18 product formations are arranged in a matrix arrangement (6 × 3) of 6 in the X direction and 3 in the Y direction. The area 13 is configured.

本実施形態１の半導体装置は、基本的に図２に示す組立プロセスによって製造される。以下、本実施形態１の半導体装置の製造について、図３乃至図９を用いて詳細に説明する。   The semiconductor device of Embodiment 1 is basically manufactured by the assembly process shown in FIG. Hereinafter, the manufacture of the semiconductor device of Embodiment 1 will be described in detail with reference to FIGS.

まず、図３に示す多数個取り基板１０を準備し、その後、図４に示すように、多数個取り基板１０の主面の複数ある製品形成領域１３の各々のチップ搭載領域１４に接着材２を配置する。   First, the multi-chip substrate 10 shown in FIG. 3 is prepared, and then, as shown in FIG. 4, the adhesive 2 is applied to each chip mounting region 14 of the plurality of product formation regions 13 on the main surface of the multi-chip substrate 10. Place.

本実施形態１では、接着材２として、例えば、エポキシ系の熱硬化性樹脂からなり、フィルム状（シート状）に加工された接着用樹脂フィルム２ａを使用し、この接着用樹脂フィルム２ａをチップ搭載領域１４に貼り付ける。また、接着用樹脂フィルム２ａとしては、図４に示すように、チップ搭載領域１４よりも小さいもの、即ち、チップ搭載領域１４に搭載される半導体チップ１よりも小さいものを使用する。また、接着用樹脂フィルム２ａの配置としては、チップ搭載領域１４の中央部、即ち、チップ搭載領域１４に半導体チップ１を搭載した時、半導体チップ１の周縁（側面）よりも内側に位置し、かつ半導体チップ１の裏面（接着面）の全面とは接触せず、半導体チップ１の裏面の中央部付近のみ接触する位置に配置する。   In the first embodiment, as the adhesive 2, for example, an adhesive resin film 2 a made of an epoxy thermosetting resin and processed into a film shape (sheet shape) is used, and the adhesive resin film 2 a is chipped. Affixed to the mounting area 14. As the adhesive resin film 2a, as shown in FIG. 4, a film smaller than the chip mounting area 14, that is, a film smaller than the semiconductor chip 1 mounted in the chip mounting area 14 is used. Further, as the arrangement of the adhesive resin film 2a, when the semiconductor chip 1 is mounted in the center portion of the chip mounting area 14, that is, in the chip mounting area 14, it is located inside the periphery (side surface) of the semiconductor chip 1, And it arrange | positions in the position which does not contact the whole surface of the back surface (adhesion surface) of the semiconductor chip 1, but contacts only the center part vicinity of the back surface of the semiconductor chip 1. FIG.

次に、図５及び図６に示すように、多数個取り基板１０の主面の複数ある製品形成領域１３の各々のチップ搭載領域１４に、接着用樹脂フィルム２ａを介在して半導体チップ１を接着固定する。半導体チップ１の接着固定は、チップ搭載領域１４上に接着用樹脂フィルム２ａを介在して半導体チップ１を配置し、その後、多数個取り基板１０及び半導体チップ１を加熱した状態で半導体チップ１を若干圧着し、その後、このままの状態を接着用樹脂フィルム２ａが溶融して硬化するまで保持することによって行う。この一連の工程を各チップ搭載領域１４毎に繰り返し実施する。本実施形態１において、半導体チップ１の圧着及び加熱は、例えば、収納トレイからチップ搭載領域１４上に半導体チップ１を搬送して位置決めする搬送コレットによって行われる。また、多数個取り基板１０の加熱は、例えば、ヒートステージによって行われる。また、接着用樹脂フィルム２ａの硬化は、例えば、１８０℃、２０秒という条件下で行われる。この時の加熱は、例えば、多数個取り基板１０を予め６５℃程度にした上で、２３５℃程度に熱せられた搬送コレットで行われる。この工程により、多数個取り基板１０の主面に複数の半導体チップ１が接着固定される。   Next, as shown in FIGS. 5 and 6, the semiconductor chip 1 is mounted on each chip mounting region 14 of the product forming region 13 on the main surface of the multi-chip substrate 10 with an adhesive resin film 2 a interposed therebetween. Adhere and fix. The semiconductor chip 1 is bonded and fixed by placing the semiconductor chip 1 on the chip mounting region 14 with the adhesive resin film 2a interposed therebetween, and then heating the multi-chip substrate 10 and the semiconductor chip 1 in a state where the semiconductor chip 1 is heated. A slight pressure is applied, and then the state as it is is maintained until the adhesive resin film 2a is melted and cured. This series of steps is repeated for each chip mounting area 14. In the first embodiment, the semiconductor chip 1 is pressed and heated by, for example, a transport collet that transports and positions the semiconductor chip 1 from the storage tray onto the chip mounting area 14. Further, the heating of the multi-piece substrate 10 is performed by, for example, a heat stage. Further, the curing of the adhesive resin film 2a is performed, for example, under conditions of 180 ° C. and 20 seconds. The heating at this time is performed by, for example, a transport collet heated to about 235 ° C. after the multi-chip substrate 10 is set to about 65 ° C. in advance. Through this step, the plurality of semiconductor chips 1 are bonded and fixed to the main surface of the multi-chip substrate 10.

この工程において、多数個取り基板１０の主面（チップ搭載領域１４）と半導体チップ１裏面（接着面）との間における接着用樹脂フィルム２ａの面積は、半導体チップ１の面積よりも小さくなっている。本実施形態１において、接着用樹脂フィルム２ａは、半導体チップ１の周縁（側面）よりも内側に配置されており、半導体チップ１の裏面（接着面）の全面とは接触せず、半導体チップ１の裏面の中央部付近のみ接触している。   In this step, the area of the adhesive resin film 2 a between the main surface (chip mounting region 14) of the multi-chip substrate 10 and the back surface (adhesion surface) of the semiconductor chip 1 is smaller than the area of the semiconductor chip 1. Yes. In the first embodiment, the adhesive resin film 2 a is disposed on the inner side of the periphery (side surface) of the semiconductor chip 1, does not contact the entire back surface (adhesion surface) of the semiconductor chip 1, and the semiconductor chip 1. It is in contact only near the center of the back side.

なお、半導体チップ１の圧着及び加熱は、チップ搭載領域１４上に半導体チップ１を搬送コレットによって配置した後、搬送コレットとは別のツールで行ってもよい。また、別のツールで行う場合、各チップ搭載領域１４上に半導体チップ１を搬送コレットによって夫々配置した後、各チップ搭載領域１４上に配置された複数の半導体チップ１を１つのツールで一括して行ってもよい。また、複数の半導体チップ１を複数のブロックに分け、このブロック毎に一括して行ってもよい。   The semiconductor chip 1 may be crimped and heated by using a tool different from the transport collet after the semiconductor chip 1 is arranged on the chip mounting region 14 by the transport collet. When using another tool, the semiconductor chip 1 is arranged on each chip mounting area 14 by the transfer collet, and then a plurality of semiconductor chips 1 arranged on each chip mounting area 14 are collected together with one tool. You may go. Alternatively, the plurality of semiconductor chips 1 may be divided into a plurality of blocks, and the processing may be performed collectively for each block.

次に、多数個取り基板１０の主面の各製品形成領域１３において、図７に示すように、製品形成領域１３の複数の電極パッド（３ａ）と、この製品形成領域１３に搭載された半導体チップ１の複数の電極パッド（１ａ）とを複数のボンディングワイヤ５で夫々電気的に接続する。この工程により、図７に示すように、多数個取り基板１０の主面に複数の半導体チップ１が実装される。   Next, in each product formation region 13 on the main surface of the multi-chip substrate 10, as shown in FIG. 7, a plurality of electrode pads (3 a) in the product formation region 13 and the semiconductor mounted in the product formation region 13. A plurality of electrode pads (1a) of the chip 1 are electrically connected by a plurality of bonding wires 5, respectively. By this step, as shown in FIG. 7, a plurality of semiconductor chips 1 are mounted on the main surface of the multi-chip substrate 10.

ここで、実装とは、基板に半導体チップが接着固定され、基板の電極パッドと半導体チップの電極パッドとが電気的に接続された状態を言う。本実施形態１では、半導体チップ１の接着固定は、接着用樹脂フィルム２ａによって行われており、多数個取り基板１０の製品形成領域１３の電極パッド（３ａ）と半導体チップ１の電極パッド（１ａ）との電気的な接続は、ボンディングワイヤ５によって行われている。   Here, the mounting means a state in which the semiconductor chip is bonded and fixed to the substrate, and the electrode pad of the substrate and the electrode pad of the semiconductor chip are electrically connected. In the first embodiment, the semiconductor chip 1 is bonded and fixed by the adhesive resin film 2a, and the electrode pad (3a) of the product forming region 13 of the multi-chip substrate 10 and the electrode pad (1a of the semiconductor chip 1). Is electrically connected to the bonding wire 5.

次に、多数個取り基板１０の主面に実装された複数の半導体チップ１を一括して樹脂封止し、図８に示すように、多数個取り基板１０の主面上に樹脂封止体１５を形成する。樹脂封止体１５は、多数個取り基板１０の主面のモールド領域（１１）に、複数の製品形成領域１３を覆うようにして形成され、各製品形成領域１３の半導体チップ１及びボンディングワイヤ５等は、１つの樹脂封止体１５によって樹脂封止される。樹脂封止体１５は、多数個取り基板１０の複数ある製品形成領域１３を一括して覆うキャビティを備えた成形金型を使用し、この成形金型のキャビティの内部に熱硬化性樹脂を注入して行う一括方式のトランスファモールド法で形成される。   Next, the plurality of semiconductor chips 1 mounted on the main surface of the multi-chip substrate 10 are collectively sealed with resin, and as shown in FIG. 15 is formed. The resin sealing body 15 is formed in the mold region (11) on the main surface of the multi-cavity substrate 10 so as to cover the plurality of product forming regions 13, and the semiconductor chip 1 and the bonding wires 5 in each product forming region 13 are formed. Are sealed with a single resin sealing body 15. The resin sealing body 15 uses a molding die having a cavity that collectively covers a plurality of product forming regions 13 of the multi-cavity substrate 10 and injects a thermosetting resin into the inside of the cavity of the molding die. It is formed by a batch transfer mold method.

この工程において、接着用樹脂フィルム２ａは半導体チップ１の裏面の中央部に選択的に配置されているため、多数個取り基板１０と半導体チップ１との間に封止樹脂が浸入し、この封止樹脂によって接着用樹脂フィルム２ａは周囲を囲まれる。即ち、多数個取り基板１０の主面と半導体チップ１の裏面との間は、図１を参照すれば、接着材２（接着用樹脂シート２ａ）が設けられた第１の領域（接着材充填領域）と、樹脂封止体４（樹脂封止体１５）の樹脂が設けられた第２の領域（封止樹脂充填領域）とを有し、第１の領域（接着材充填領域）は、第２の領域（封止樹脂充填領域）で周囲を囲まれている。   In this step, since the adhesive resin film 2a is selectively disposed at the center of the back surface of the semiconductor chip 1, the sealing resin enters between the multi-chip substrate 10 and the semiconductor chip 1, and this sealing is performed. The adhesive resin film 2a is surrounded by the stop resin. That is, between the main surface of the multi-chip substrate 10 and the back surface of the semiconductor chip 1, referring to FIG. 1, the first region (adhesive filling) with the adhesive 2 (adhesive resin sheet 2a) is provided. Region) and a second region (sealing resin filling region) provided with resin of the resin sealing body 4 (resin sealing body 15), and the first region (adhesive filling region) is The periphery is surrounded by the second region (sealing resin filling region).

次に、多数個取り基板１０の主面と反対側の裏面に、各製品形成領域に対応して複数の半田バンプ６を形成する。半田バンプ６は、例えば、多数個取り基板１０の裏面の電極パッド上にボール供給法で半田ボールを供給し、その後、半田ボールを溶融して電極パッドとの接合を行うことによって形成される。   Next, a plurality of solder bumps 6 are formed on the back surface opposite to the main surface of the multi-chip substrate 10 corresponding to each product formation region. The solder bumps 6 are formed, for example, by supplying solder balls onto the electrode pads on the back surface of the multi-chip substrate 10 by a ball supply method, and then melting the solder balls and joining them to the electrode pads.

次に、図９に示すように、多数個取り基板１０及び樹脂封止体１５を複数の個片に分割する。この分割は、多数個取り基板１０の分離領域１２に沿って多数個取り基板１０及び樹脂封止体１５を例えばダイシングすることによって行われる。この工程により、図１に示す本実施形態１の半導体装置がほぼ完成する。   Next, as shown in FIG. 9, the multi-cavity substrate 10 and the resin sealing body 15 are divided into a plurality of pieces. This division is performed by, for example, dicing the multi-chip substrate 10 and the resin sealing body 15 along the separation region 12 of the multi-chip substrate 10. Through this step, the semiconductor device of the first embodiment shown in FIG. 1 is almost completed.

本実施形態１の半導体装置の製造では、加熱して熱硬化性の接着用樹脂フィルム２ａを硬化させることにより、多数個取り基板１０の主面に半導体チップ１を接着固定しているため、半導体チップ１を接着固定した後、多数個取り基板１０に、半導体チップ１と多数個取り基板１０との熱膨張係数差に起因する反りが生じる。本実施形態１では、図６に示すように、多数個取り基板１０の主面と半導体チップ１との間における接着用樹脂フィルム２ａの面積が半導体チップ１の面積よりも小さくなっているため、多数個取り基板１０の主面と半導体チップ１との間の全域に接着用樹脂フィルムを配置した場合と比較して、多数個取り基板１０と半導体チップ１との熱膨張係数差に起因する多数個取り基板１０の反り変形を低減することができる。   In the manufacture of the semiconductor device of the first embodiment, the semiconductor chip 1 is bonded and fixed to the main surface of the multi-chip substrate 10 by heating and curing the thermosetting adhesive resin film 2a. After the chip 1 is bonded and fixed, warping due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the multi-chip substrate 10 occurs in the multi-chip substrate 10. In the first embodiment, as shown in FIG. 6, the area of the adhesive resin film 2 a between the main surface of the multi-chip substrate 10 and the semiconductor chip 1 is smaller than the area of the semiconductor chip 1. Compared with the case where the adhesive resin film is disposed in the entire area between the main surface of the multi-chip substrate 10 and the semiconductor chip 1, the large number caused by the difference in thermal expansion coefficient between the multi-chip substrate 10 and the semiconductor chip 1. Warpage deformation of the individual substrate 10 can be reduced.

また、本実施形態１では、図４に示すように、チップ搭載領域１４（半導体チップ１）の外形サイズよりも小さい外形サイズの接着用樹脂フィルム２ａを使用し、この接着用樹脂フィルム２ａをチップ搭載領域１４の中央部に配置している。チップ搭載領域１４よりも外形サイズが小さい接着用樹脂フィルム２ａを使用する場合、チップ搭載領域１４の周辺部に偏って接着用樹脂フィルム２ａを配置しても、チップ搭載領域１４と半導体チップ１との間における接着用樹脂フィルム２ａの面積を半導体チップ１の面積よりも小さくすることができる。しかしながら、チップ搭載領域１４の周辺部に偏って接着用樹脂フィルム２ａを配置した場合、チップ搭載工程において、半導体チップ１が大きく傾き易く、半導体チップ１の接着強度が低下したり、半導体チップ１の位置がずれたりする不具合や、ワイヤボンディング工程においてワイヤ接続不良が発生し易くなる。従って、チップ搭載領域１４よりも外形サイズが小さい接着用樹脂フィルム２ａを使用する場合は、半導体チップ１の搭載を安定して行うことができる配置、即ち、本実施形態１のように、接着用樹脂フィルム２ａをチップ搭載領域１４の中央部に配置することが望ましい。   In the first embodiment, as shown in FIG. 4, an adhesive resin film 2a having an outer size smaller than the outer size of the chip mounting region 14 (semiconductor chip 1) is used, and the adhesive resin film 2a is used as a chip. It is arranged at the center of the mounting area 14. When the adhesive resin film 2a having a smaller outer size than the chip mounting area 14 is used, the chip mounting area 14 and the semiconductor chip 1 can be arranged even if the adhesive resin film 2a is disposed in the peripheral area of the chip mounting area 14 The area of the adhesive resin film 2a in between can be made smaller than the area of the semiconductor chip 1. However, when the adhesive resin film 2a is disposed in the peripheral portion of the chip mounting area 14, the semiconductor chip 1 tends to be greatly inclined in the chip mounting process, and the bonding strength of the semiconductor chip 1 is reduced. Problems such as misalignment and wire connection failures are likely to occur in the wire bonding process. Therefore, when the adhesive resin film 2a having a smaller outer size than the chip mounting area 14 is used, the semiconductor chip 1 can be mounted stably, that is, as in the first embodiment, It is desirable to arrange the resin film 2a at the center of the chip mounting area 14.

多数個取り基板１０の主面と半導体チップ１との間における接着用樹脂フィルム２ａの面積は、例えば、半導体チップ１の裏面の中央部を接着しないで周辺部のみをリング状に接着するようにしても小さくすることができる。しかしながら、このような場合、接着用樹脂フィルム１ａの面積は小さくなっても、熱膨張係数差に起因する応力は半導体チップ１の裏面全体を接着した時とほぼ同等になるため、多数個取り基板１０の反り変形の低減は期待できない。このことは、半導体チップ１の裏面の４つの角部を夫々独立に接着する場合においても同様である。従って、本実施形態１のように、半導体チップ１の裏面の全面を接着せず、半導体チップ１の裏面の中央部付近のみ接着固定することが有効である。   The area of the adhesive resin film 2a between the main surface of the multi-chip substrate 10 and the semiconductor chip 1 is such that, for example, only the peripheral portion is bonded in a ring shape without bonding the central portion of the back surface of the semiconductor chip 1. But it can be made smaller. However, in such a case, even if the area of the adhesive resin film 1a is reduced, the stress caused by the difference in thermal expansion coefficient is almost the same as when the entire back surface of the semiconductor chip 1 is bonded. A reduction of 10 warp deformation cannot be expected. The same applies to the case where the four corners on the back surface of the semiconductor chip 1 are bonded independently. Therefore, as in the first embodiment, it is effective not to bond the entire back surface of the semiconductor chip 1 but to bond and fix only the central portion of the back surface of the semiconductor chip 1.

本実施形態１のように、外形サイズがチップ搭載領域１４（半導体チップ１）よりも小さい接着用樹脂フィルム２ａを使用する場合、樹脂封止工程において、多数個取り基板１０の主面と半導体チップ１との間に封止樹脂の未充填によるボイドが発生し易くなる。従って、外形サイズがチップ搭載領域１４（半導体チップ１）よりも小さい接着用樹脂フィルム２ａを使用する場合は、半導体チップ１を接着固定した後の、多数個取り基板１０と半導体チップ１との離間が、封止樹脂に含まれるフィラー（例えばシリカ）のうち、最も外形サイズの大きいフィラーよりも広くなるように、接着用樹脂フィルム２ａの厚さを選定する。   When the adhesive resin film 2a whose outer size is smaller than the chip mounting region 14 (semiconductor chip 1) is used as in the first embodiment, the main surface of the multi-chip substrate 10 and the semiconductor chip are used in the resin sealing step. Voids due to unfilling of the sealing resin are likely to occur between Therefore, when using the adhesive resin film 2a whose outer size is smaller than the chip mounting region 14 (semiconductor chip 1), the separation between the multi-chip substrate 10 and the semiconductor chip 1 after the semiconductor chip 1 is bonded and fixed. However, the thickness of the adhesive resin film 2a is selected so as to be wider than the filler having the largest outer size among the fillers (for example, silica) contained in the sealing resin.

なお、本実施形態１では、接着材２として接着用樹脂シート２ａを使用した例について説明したが、接着材２としては、ペースト状の接着材を使用してもよい。但し、ペースト状の接着材はチップ搭載領域１４に塗布した時に濡れ広がり易く、また、チップ搭載領域１４に半導体チップ１を配置する時の反動による圧着で濡れ広がり易いため、量産における制御が難しい。従って、接着材２としては本実施形態１のようにフィルム状に加工されたものを用いることが望ましい。   In the first embodiment, the example in which the adhesive resin sheet 2a is used as the adhesive 2 has been described. However, as the adhesive 2, a paste-like adhesive may be used. However, since the paste-like adhesive is easily spread when wet applied to the chip mounting area 14, and is easily spread by pressure bonding when the semiconductor chip 1 is disposed in the chip mounting area 14, control in mass production is difficult. Therefore, it is desirable to use the adhesive 2 processed into a film shape as in the first embodiment.

また、接着材２としては、半田ペースト、半田プリホーム、Ａｇペースト等の導電性接着材を用いてもよい。   Further, as the adhesive 2, a conductive adhesive such as solder paste, solder preform, or Ag paste may be used.

（実施形態２）
本実施形態２では、複数の突起状電極の配置を工夫して、樹脂封止前の基板反り変形を低減した例について説明する。 (Embodiment 2)
In the second embodiment, an example will be described in which the arrangement of a plurality of protruding electrodes is devised to reduce substrate warpage deformation before resin sealing.

図１５は、本実施形態２の半導体装置の内部構造を示す図（（ａ）は模式的断面図，（ｂ）は模式的平面図）であり、
図１６は、本実施形態２の半導体装置の製造において、チップ実装工程を示す模式的断面図である。 FIG. 15 is a diagram ((a) is a schematic cross-sectional view, (b) is a schematic plan view) showing an internal structure of the semiconductor device of Embodiment 2.
FIG. 16 is a schematic cross-sectional view showing a chip mounting process in the manufacture of the semiconductor device of the second embodiment.

本実施形態２の半導体装置は、図１５（ａ），（ｂ）に示すように、基本的に前述の実施形態１と同様の構成になっており、以下の構成が異なっている。   As shown in FIGS. 15A and 15B, the semiconductor device of Embodiment 2 has basically the same configuration as that of Embodiment 1 described above, and the following configuration is different.

即ち、半導体チップ１は、その主面１ｘと配線基板３の主面との間に、突起状電極として例えば複数の半田バンプ７を介在した状態で、配線基板３の主面３ｘに実装されている。複数の半田バンプ７は、半導体チップ１の主面の中央部に偏って配置されている。複数の半田バンプ７の各々は、半導体チップの主面１ｘに配置された電極パッド１ａと配線基板３の主面に配置された電極パッド３ａとの間に介在され、両者の電極パッドと電気的にかつ機械的に接続されている。   That is, the semiconductor chip 1 is mounted on the main surface 3x of the wiring substrate 3 with a plurality of solder bumps 7 interposed as protruding electrodes between the main surface 1x and the main surface of the wiring substrate 3, for example. Yes. The plurality of solder bumps 7 are arranged so as to be biased toward the center of the main surface of the semiconductor chip 1. Each of the plurality of solder bumps 7 is interposed between the electrode pad 1a arranged on the main surface 1x of the semiconductor chip and the electrode pad 3a arranged on the main surface of the wiring board 3, and both the electrode pads and the electric pads are electrically connected. And mechanically connected.

配線基板３の主面３ｘと半導体チップ１の主面１ｘとの間には、複数の半田バンプ７が配置され、更に複数の半田バンプ７を除く領域に樹脂封止体４の樹脂が配置されている。   A plurality of solder bumps 7 are arranged between the main surface 3x of the wiring board 3 and the main surface 1x of the semiconductor chip 1, and a resin of the resin sealing body 4 is arranged in a region excluding the plurality of solder bumps 7. ing.

本実施形態２の半導体装置は、前述の実施形態１と同様に、基本的に図２に示す組立プロセスによって製造される。以下、本実施形態２の半導体装置の製造について、図２及び図１６を用いて説明する。   The semiconductor device according to the second embodiment is basically manufactured by the assembly process shown in FIG. 2 as in the first embodiment. Hereinafter, the manufacture of the semiconductor device of Embodiment 2 will be described with reference to FIGS.

まず、図３に示す多数個取り基板１０を準備すると共に、図１５に示す半導体チップ１を複数準備する。本実施形態２の多数個取り基板１０は、各々のチップ搭載領域１４の中に複数の電極パッド３ａが配置されている。また、本実施形態２の半導体チップ１は、その主面１ｘに、突起状電極として、例えば複数の半田バンプ７が予め形成されている。複数の半田バンプ７は、半導体チップ１の主面１ｘの中央部付近に集中して配置されている。複数の半田バンプ７は、半導体ウエハを複数の個片に分割して複数の半導体チップ１を形成する前、半導体ウエハの主面に例えば半田ペースト材を印刷法によって配置し、その後、リフロー処理を施して半田ペースト材を溶融することによって形成される。   First, the multi-chip substrate 10 shown in FIG. 3 is prepared, and a plurality of semiconductor chips 1 shown in FIG. 15 are prepared. In the multi-chip substrate 10 of the second embodiment, a plurality of electrode pads 3 a are arranged in each chip mounting region 14. Further, in the semiconductor chip 1 of the second embodiment, for example, a plurality of solder bumps 7 are formed in advance on the main surface 1x as protruding electrodes. The plurality of solder bumps 7 are concentrated in the vicinity of the central portion of the main surface 1x of the semiconductor chip 1. The plurality of solder bumps 7 are formed by, for example, placing a solder paste material on the main surface of the semiconductor wafer by a printing method before dividing the semiconductor wafer into a plurality of pieces to form the plurality of semiconductor chips 1, and then performing a reflow process. It is formed by applying and melting the solder paste material.

次に、図１６に示すように、多数個取り基板１０の主面の複数ある製品形成領域１３の各々のチップ搭載領域１４に、半導体チップ１を夫々配置する。半導体チップ１は、その主面１ｘが多数個取り基板１０の主面と向かい合う状態で配置される。   Next, as shown in FIG. 16, the semiconductor chips 1 are respectively arranged in the chip mounting regions 14 of the plurality of product forming regions 13 on the main surface of the multi-chip substrate 10. The semiconductor chip 1 is arranged with its main surface 1x facing the main surface of the multi-chip substrate 10.

次に、多数個取り基板１０を例えば赤外線リフロー炉に搬送し、その後、各々の製品形成領域１３における複数の半田バンプ７を一括して溶融し、その後、硬化させる。この工程により、多数個取り基板１０の主面に、夫々複数の半田バンプ７を介在して複数の半導体チップ１が実装される。   Next, the multi-piece substrate 10 is transferred to, for example, an infrared reflow furnace, and then the plurality of solder bumps 7 in each product formation region 13 are melted together and then cured. By this step, a plurality of semiconductor chips 1 are mounted on the main surface of the multi-chip substrate 10 with a plurality of solder bumps 7 interposed therebetween.

この後、前述の実施形態１と同様の工程を施すことにより、即ち、多数個取り基板１０の主面に実装された複数の半導体チップ１を１つの樹脂封止体１５で一括して樹脂封止し、その後、多数個取り基板１０の裏面に、各製品形成領域１３に対応して複数の半田バンプ６を形成し、その後、多数個取り基板１０及び樹脂封止体１５を複数の個片に分割することより、図１５に示す本実施形態２の半導体装置がほぼ完成する。   Thereafter, the same process as in the first embodiment is performed, that is, a plurality of semiconductor chips 1 mounted on the main surface of the multi-chip substrate 10 are collectively sealed with one resin sealing body 15. After that, a plurality of solder bumps 6 are formed on the back surface of the multi-piece substrate 10 corresponding to each product formation region 13, and then the multi-piece substrate 10 and the resin sealing body 15 are divided into a plurality of pieces. The semiconductor device according to the second embodiment shown in FIG. 15 is almost completed.

本実施形態２の半導体装置の製造工程中のチップ実装工程において、多数個取り基板１０の主面と半導体チップ１の主面との間における複数の半田バンプ７は、図１６に示すように、半導体チップ１の主面１ｘの中央部付近に集中して配置（偏って配置）されている。このようなバンプ配置にすることにより、本実施形態２においても、樹脂封止前の多数個取り基板１０の反り変形を低減することができる。   In the chip mounting process during the manufacturing process of the semiconductor device according to the second embodiment, the plurality of solder bumps 7 between the main surface of the multi-chip substrate 10 and the main surface of the semiconductor chip 1 are as shown in FIG. The semiconductor chip 1 is concentrated (displaced) in the vicinity of the central portion of the main surface 1x of the semiconductor chip 1. By adopting such a bump arrangement, also in the second embodiment, warping deformation of the multi-chip substrate 10 before resin sealing can be reduced.

図１７は、本実施形態２の変形例である半導体チップの模式的平面図である。   FIG. 17 is a schematic plan view of a semiconductor chip which is a modification of the second embodiment.

複数の半田バンプ７が半導体チップ１の主面の全面に配置されても、図１７に示すように、極端に半導体チップ１の主面１ｘの中央部に集中した配置であれば、多数個取り基板１０の反り低減効果が期待できる。   Even if the plurality of solder bumps 7 are arranged on the entire main surface of the semiconductor chip 1, as shown in FIG. 17, if the arrangement is extremely concentrated on the central portion of the main surface 1x of the semiconductor chip 1, a large number of solder bumps 7 are obtained. The effect of reducing the warpage of the substrate 10 can be expected.

なお、実施形態２では、突起状電極として半田バンプ７を使用し、この半田バンプ７を溶融して半導体チップ１を実装する例について説明したが、本発明は、突起状電極として、例えばＡｕ（金）又はＣｕ（銅）を主成分とする金属バンプを用いて半導体チップ１を実装する場合においても適用することができる。この場合、半導体チップ１は、加熱圧着によって実装される。   In the second embodiment, an example in which the solder bump 7 is used as the protruding electrode and the semiconductor chip 1 is mounted by melting the solder bump 7 has been described. The present invention can also be applied to the case where the semiconductor chip 1 is mounted using metal bumps mainly composed of gold or Cu (copper). In this case, the semiconductor chip 1 is mounted by thermocompression bonding.

また、本発明は、基板の電極パッド上に配置された半田ペースト（迎え半田）を溶融して、基板の電極パッドと突起状電極とを接続することにより、基板に半導体チップを実装する場合においても適用することができる。
（実施形態３）
本実施形態３では、接着材の大きさ及び複数の突起状電極の配置を工夫して、樹脂封止前の基板反り変形を低減した例について説明する。 The present invention also relates to a case where a semiconductor chip is mounted on a substrate by melting a solder paste (welding solder) disposed on the electrode pad of the substrate and connecting the electrode pad of the substrate and the protruding electrode. Can also be applied.
(Embodiment 3)
In the third embodiment, an example will be described in which the size of the adhesive and the arrangement of the plurality of protruding electrodes are devised to reduce the warpage deformation of the substrate before resin sealing.

図１８は、本実施形態３の半導体装置の内部構造を示す図（（ａ）は模式的断面図，（ｂ）は模式的平面図）であり、
図１９は、本実施形態３の半導体装置の製造において、チップ実装工程を示す模式的断面図である。 FIG. 18 is a diagram ((a) is a schematic cross-sectional view, (b) is a schematic plan view) showing the internal structure of the semiconductor device of Embodiment 3.
FIG. 19 is a schematic cross-sectional view showing a chip mounting process in the manufacture of the semiconductor device of the third embodiment.

本実施形態３の半導体装置は、図１８（ａ），（ｂ）に示すように、基本的に前述の実施形態１と同様の構成になっており、以下の構成が異なっている。   As shown in FIGS. 18A and 18B, the semiconductor device of Embodiment 3 has basically the same configuration as that of Embodiment 1 described above, and the following configuration is different.

即ち、半導体チップ１は、その主面１ａと配線基板３の主面３ｘとの間に、突起状電極として例えばＡｕ又はＣｕを主成分とする金属材からなる複数のスタッドバンプ８、並びに接着材２として例えばＡＣＦ９を介在した状態で、配線基板３の主面３ｘに実装されている。   That is, the semiconductor chip 1 includes a plurality of stud bumps 8 made of a metal material mainly composed of, for example, Au or Cu as a protruding electrode, and an adhesive between the main surface 1a and the main surface 3x of the wiring board 3. 2 is mounted on the main surface 3x of the wiring board 3 with an ACF 9 interposed therebetween, for example.

複数のスタッドバンプ８は、半導体チップ１の主面１ｘの中央部に偏って配置されている。複数のスタッドバンプ８の各々は、半導体チップの主面１ｘに配置された電極パッド１ａと配線基板３の主面３ｘに配置された電極パッド３ａとの間に介在され、両者の電極パッドと電気的に接続されている。   The plurality of stud bumps 8 are arranged so as to be biased toward the central portion of the main surface 1x of the semiconductor chip 1. Each of the plurality of stud bumps 8 is interposed between the electrode pad 1a arranged on the main surface 1x of the semiconductor chip and the electrode pad 3a arranged on the main surface 3x of the wiring board 3, and both the electrode pads and the electric pads are electrically connected. Connected.

ＡＣＦ９は、半導体チップ１の周縁（側面）よりも内側に配置されており、半導体チップ１の主面１ｘ（接着面）の全面とは接触せず、複数のスタッドバンプ８を含むように、半導体チップ１の主面１ｘの中央部付近のみ接触している。   The ACF 9 is disposed on the inner side of the periphery (side surface) of the semiconductor chip 1, does not contact the entire main surface 1 x (adhesion surface) of the semiconductor chip 1, and includes a plurality of stud bumps 8. Only the central portion of the main surface 1x of the chip 1 is in contact.

半導体チップ１は、ＡＣＦ９によって配線基板３の主面に接着固定されており、半導体チップ１の複数の電極パッド１ａは、スタッドバンプ８、及びＡＣＦ９に含まれる導電粒子を介在して、配線基板３の複数の電極パッド３ａと夫々電気的に接続されている。   The semiconductor chip 1 is bonded and fixed to the main surface of the wiring board 3 by the ACF 9, and the plurality of electrode pads 1 a of the semiconductor chip 1 interpose the stud bumps 8 and the conductive particles contained in the ACF 9 to interpose the wiring board 3. The plurality of electrode pads 3a are electrically connected to each other.

ここで、ＡＣＦ（Ａnisotropic Ｃonductive Ｆilm：異方導電性フィルム）とは、多数の導電粒子が分散して混入された絶縁樹脂をシート状に加工したものであり、本実施形態３では、例えばエポキシ系の熱硬化性樹脂からなるＡＣＦを用いている。   Here, ACF (Anisotropic Conductive Film) is an insulating resin in which a large number of conductive particles are dispersed and mixed, and is processed into a sheet shape. ACF made of a thermosetting resin is used.

本実施形態３の半導体装置は、前述の実施形態１と同様に、基本的に図２に示す組立プロセスによって製造される。以下、本実施形態３の半導体装置の製造について、図２及び図１９を用いて説明する。   The semiconductor device according to the third embodiment is basically manufactured by the assembly process shown in FIG. 2 as in the first embodiment. Hereinafter, the manufacture of the semiconductor device according to the third embodiment will be described with reference to FIGS.

まず、図３に示す多数個取り基板１０を準備すると共に、図１８に示す半導体チップ１を複数準備する。本実施形態３の多数個取り基板１０は、各々のチップ搭載領域１４の中に複数の電極パッド３ａが配置されている。また、本実施形態３の半導体チップ１は、その主面２ｘに、突起状電極として、例えば複数のスタッドバンプ８が予め形成されている。複数のスタッドバンプ８は、半導体チップ１の主面１ｘの中央部付近に集中して配置されている。複数のスタッドバンプ８は、半導体ウエハを複数の個片に分割して複数の半導体チップ１を形成する前、半導体ウエハの主面に例えばＡｕワイヤを用いたネイルヘッドボンディング法によって形成される。   First, the multi-chip substrate 10 shown in FIG. 3 is prepared, and a plurality of semiconductor chips 1 shown in FIG. 18 are prepared. In the multi-chip substrate 10 of the third embodiment, a plurality of electrode pads 3 a are arranged in each chip mounting region 14. Further, in the semiconductor chip 1 of Embodiment 3, for example, a plurality of stud bumps 8 are formed in advance on the main surface 2x as protruding electrodes. The plurality of stud bumps 8 are concentrated in the vicinity of the central portion of the main surface 1x of the semiconductor chip 1. The plurality of stud bumps 8 are formed by a nail head bonding method using, for example, an Au wire on the main surface of the semiconductor wafer before dividing the semiconductor wafer into a plurality of pieces to form the plurality of semiconductor chips 1.

次に、多数個取り基板１０の主面の複数ある製品形成領域１３の各々のチップ搭載領域１４にＡＣＦ９を貼り付ける。ＡＣＦ９としては、チップ搭載領域１４よりも小さいもの、即ち、チップ搭載領域１４に搭載される半導体チップ１よりも小さいものを使用する。また、ＡＣＦ９の配置としては、チップ搭載領域１４の中央部、即ち、チップ搭載領域１４に半導体チップ１を搭載した時、半導体チップ１の周縁（側面）よりも内側に位置し、かつ半導体チップ１の主面（接着面）１ｘの全面とは接触せず、複数のスタッドバンプ８を含んで半導体チップ１の主面１ｘの中央部付近のみ接触するように配置する。   Next, the ACF 9 is affixed to each chip mounting region 14 of the product forming region 13 on the main surface of the multi-chip substrate 10. The ACF 9 is smaller than the chip mounting area 14, that is, smaller than the semiconductor chip 1 mounted in the chip mounting area 14. The ACF 9 is arranged such that when the semiconductor chip 1 is mounted in the center of the chip mounting area 14, that is, in the chip mounting area 14, the ACF 9 is positioned on the inner side of the periphery (side surface) of the semiconductor chip 1. The main surface (adhesive surface) 1x is not in contact with the entire surface of the main surface 1x, but includes a plurality of stud bumps 8 so that only the central portion of the main surface 1x of the semiconductor chip 1 is in contact.

次に、多数個取り基板１０の主面の複数ある製品形成領域１３の各々のチップ搭載領域１４に、ＡＣＦ９を介在して半導体チップ１を接着固定する。半導体チップ１の接着固定は、図１９に示すように、チップ搭載領域１４上にＡＣＦ９を介在して半導体チップ１を配置し、その後、多数個取り基板１０及び半導体チップ１を加熱した状態で半導体チップ１を圧着し、その後、このままの状態をＡＣＦ９が溶融して硬化するまで保持することによって行う。この一連の工程を各チップ搭載領域１４毎に繰り返し実施する。本実施形態１において、半導体チップ１の圧着及び加熱は、例えば、収納トレイからチップ搭載領域１４上に半導体チップ１を搬送して位置決めする搬送コレットによって行われる。また、多数個取り基板１０の加熱は、例えば、ヒートステージによって行われる。また、ＡＣＦ９の硬化は、例えば、１８０℃、２０秒という条件下で行われる。この時の加熱は、例えば、多数個取り基板１０を予め６５℃程度にした上で、２３５℃程度に熱せられた搬送コレットで行われる。この工程により、多数個取り基板１０の主面に複数の半導体チップ１が実装される。半導体チップ１は、ＡＣＦ９によって多数個取り基板１０の主面に接着固定される。半導体チップ１の電極パッド１ａは、スタッドバンプ８、及びＡＣＦ９の導電性粒子を介在して多数個取り基板１０の電極パッド３ａと電気的に接続される。   Next, the semiconductor chip 1 is bonded and fixed to each chip mounting area 14 of each of the plurality of product forming areas 13 on the main surface of the multi-chip substrate 10 with the ACF 9 interposed therebetween. As shown in FIG. 19, the semiconductor chip 1 is bonded and fixed by placing the semiconductor chip 1 on the chip mounting area 14 with the ACF 9 interposed therebetween, and then heating the multi-chip substrate 10 and the semiconductor chip 1 in a state where the semiconductor chip 1 is heated. The chip 1 is pressure-bonded, and then this state is maintained until the ACF 9 is melted and cured. This series of steps is repeated for each chip mounting area 14. In the first embodiment, the semiconductor chip 1 is pressed and heated by, for example, a transport collet that transports and positions the semiconductor chip 1 from the storage tray onto the chip mounting area 14. Further, the heating of the multi-piece substrate 10 is performed by, for example, a heat stage. Further, the ACF 9 is cured under conditions of, for example, 180 ° C. and 20 seconds. The heating at this time is performed by, for example, a transport collet heated to about 235 ° C. after the multi-chip substrate 10 is set to about 65 ° C. in advance. By this step, a plurality of semiconductor chips 1 are mounted on the main surface of the multi-chip substrate 10. The semiconductor chip 1 is bonded and fixed to the main surface of the multi-chip substrate 10 by the ACF 9. The electrode pads 1a of the semiconductor chip 1 are electrically connected to the electrode pads 3a of the multi-chip substrate 10 with the stud bumps 8 and the conductive particles of the ACF 9 interposed therebetween.

なお、半導体チップ１の圧着及び加熱は、チップ搭載領域１４上に半導体チップ１を搬送コレットによって配置した後、搬送コレットとは別のツールで行ってもよい。また、別のツールで行う場合、各チップ搭載領域１４上に半導体チップ１を搬送コレットによって夫々配置した後、各チップ搭載領域１４上に配置された複数の半導体チップ１を１つのツールで一括して行ってもよい。また、複数の半導体チップ１を複数のブロックに分け、このブロック毎に一括して行ってもよい。   The semiconductor chip 1 may be crimped and heated by using a tool different from the transport collet after the semiconductor chip 1 is arranged on the chip mounting region 14 by the transport collet. When using another tool, the semiconductor chip 1 is arranged on each chip mounting area 14 by the transfer collet, and then a plurality of semiconductor chips 1 arranged on each chip mounting area 14 are collected together with one tool. You may go. Alternatively, the plurality of semiconductor chips 1 may be divided into a plurality of blocks, and the processing may be performed collectively for each block.

この後、前述の実施形態１と同様の工程を施すことにより、即ち、多数個取り基板１０の主面に実装された複数の半導体チップ１を１つの樹脂封止体１５で一括して樹脂封止し、その後、多数個取り基板１０の裏面に、各製品形成領域１３に対応して複数の半田バンプ６を形成し、その後、多数個取り基板１０及び樹脂封止体１５を複数の個片に分割することより、図１８に示す本実施形態３の半導体装置がほぼ完成する。   Thereafter, the same process as in the first embodiment is performed, that is, a plurality of semiconductor chips 1 mounted on the main surface of the multi-chip substrate 10 are collectively sealed with one resin sealing body 15. After that, a plurality of solder bumps 6 are formed on the back surface of the multi-piece substrate 10 corresponding to each product formation region 13, and then the multi-piece substrate 10 and the resin sealing body 15 are divided into a plurality of pieces. The semiconductor device of the third embodiment shown in FIG. 18 is almost completed.

本実施形態３の半導体装置の製造工程中のチップ実装工程において、図１９に示すように、多数個取り基板１０の主面と半導体チップ１の主面１ｘとの間における複数のスタッドバンプ８は、半導体チップ１の主面１ｘの全面に均等に配置されず、半導体チップ１の主面１ｘの中央部に偏って配置されている。また、多数個取り基板１０の主面と半導体チップ１の主面１ｘとの間におけるＡＣＦ９は、半導体チップ１の主面１ｘの全面とは接触せず、複数のスタッドバンプ８を含むように、半導体チップ１の主面１ｘの中央部に接触している。このようにすることにより、本実施形態３においても、樹脂封止前の多数個取り基板１０の反り変形を低減することができる。   In the chip mounting process during the manufacturing process of the semiconductor device of the third embodiment, as shown in FIG. 19, the plurality of stud bumps 8 between the main surface of the multi-chip substrate 10 and the main surface 1x of the semiconductor chip 1 are The semiconductor chip 1 is not evenly arranged on the entire main surface 1x, but is arranged in a central portion of the main surface 1x of the semiconductor chip 1. Further, the ACF 9 between the main surface of the multi-chip substrate 10 and the main surface 1x of the semiconductor chip 1 is not in contact with the entire main surface 1x of the semiconductor chip 1 and includes a plurality of stud bumps 8. The semiconductor chip 1 is in contact with the central portion of the main surface 1x. By doing in this way, also in this Embodiment 3, the curvature deformation of the multi-cavity substrate 10 before resin sealing can be reduced.

なお、本実施形態３では、接着材としてＡＣＦを用いた例について説明したが、本発明は、接着材として、例えば、導電粒子が混入されていない熱硬化性絶縁樹脂からなる樹脂フィルム（ＮＣＦ：Ｎon Ｃonductive Ｆilm）や、熱硬化性絶縁樹脂に多数の導電粒子が分散して混入されたペースト状の異方導電性樹脂（ＡＣＰ：Ａnisotropic Ｃonductive Ｐeste）を用いたい場合においても適用することができる。   In the third embodiment, an example in which ACF is used as an adhesive has been described. However, the present invention can be applied as an adhesive, for example, a resin film (NCF: made of a thermosetting insulating resin in which conductive particles are not mixed). The present invention can also be applied to a case where non-conductive film (ACP) or a paste-like anisotropic conductive resin (ACP) in which a large number of conductive particles are dispersed and mixed in a thermosetting insulating resin is used.

また、本発明は、バンプを使用せず、接着用樹脂に混入された導電性粒子によって半導体チップの電極パッドと基板の電極パッドとを電気的に接続するバンプレス実装技術を採用する半導体装置の製造にも適用することができる。   In addition, the present invention provides a semiconductor device that employs bumpless mounting technology that electrically connects an electrode pad of a semiconductor chip and an electrode pad of a substrate by using conductive particles mixed in an adhesive resin without using bumps. It can also be applied to manufacturing.

（実施形態４）
本実施形態４では、基板にスリットを設けて、樹脂封止前の基板反り変形を低減した例について説明する。 (Embodiment 4)
In the fourth embodiment, an example in which a substrate is provided with slits to reduce the warpage deformation of the substrate before resin sealing will be described.

図２０は、本実施形態４の半導体装置の製造において、基板に半導体チップを実装した状態を示す模式的平面図であり、
図２１は、図２０のａ−ａ線に沿う模式的断面図である。 FIG. 20 is a schematic plan view showing a state in which a semiconductor chip is mounted on a substrate in the manufacture of the semiconductor device of Embodiment 4.
FIG. 21 is a schematic cross-sectional view taken along the line aa in FIG.

図２０及び図２１に示すように、多数個取り基板１０の主面には、各製品形成領域１３のチップ搭載領域１４に対応して、複数の半導体チップ１が実装されている。本実施形態４において、半導体チップ１の実装は、詳細に図示していないが、例えば、前述の実施形態１と同様の方法、即ち、多数個取り基板１０の主面に接着材２を介在して半導体チップ１の裏面を接着固定し、その後、半導体チップ１の電極パッドと多数個取り基板１０の主面の電極パッドとをボンディングワイヤで接続することによって行われている。   As shown in FIGS. 20 and 21, a plurality of semiconductor chips 1 are mounted on the main surface of the multi-chip substrate 10 so as to correspond to the chip mounting area 14 of each product forming area 13. In the fourth embodiment, the mounting of the semiconductor chip 1 is not shown in detail, but, for example, the same method as in the first embodiment described above, that is, the adhesive 2 is interposed on the main surface of the multi-chip substrate 10. Then, the back surface of the semiconductor chip 1 is bonded and fixed, and then the electrode pads of the semiconductor chip 1 and the electrode pads on the main surface of the multi-chip substrate 10 are connected by bonding wires.

本実施形態４の多数個取り基板１０は、前述の実施形態１と異なり、複数の製品形成領域１３が２つのブロック（群）に別れて配置されており、この２つのブロックは、ブロックの間隔が製品形成領域１３の間隔よりも広くなるように、多数個取り基板１０の長手方向（Ｘ方向）に離間して配置されている。即ち、複数の製品形成領域１３、複数のチップ搭載領域１４、そして実装後の複数の半導体チップ１は、多数個取り基板１０の長手方向において互いに反対側に位置する両端部に偏って配置されている。   Unlike the first embodiment described above, the multi-chip substrate 10 of the fourth embodiment has a plurality of product forming regions 13 arranged in two blocks (groups), and the two blocks are spaced apart from each other. Are spaced apart from each other in the longitudinal direction (X direction) of the multi-chip substrate 10 so as to be wider than the interval between the product formation regions 13. That is, the plurality of product forming regions 13, the plurality of chip mounting regions 14, and the plurality of semiconductor chips 1 after mounting are arranged in a biased manner at both ends located on opposite sides in the longitudinal direction of the multi-chip substrate 10. Yes.

また、本実施形態４の多数個取り基板１０は、スリット１６を有する構成になっている。スリット１６は、チップ搭載領域１４（半導体チップ１）間に設けられており、本実施形態４では、製品形成領域１３間の分離領域１２に設けられている。   Further, the multi-chip substrate 10 of the fourth embodiment is configured to have a slit 16. The slits 16 are provided between the chip mounting regions 14 (semiconductor chips 1). In the fourth embodiment, the slits 16 are provided in the separation regions 12 between the product formation regions 13.

この後、前述の実施形態１と同様の工程を施すことにより、即ち、多数個取り基板１０の主面に実装された複数の半導体チップ１を１つの樹脂封止体１５で一括して樹脂封止し、その後、多数個取り基板１０の裏面に、各製品形成領域１３に対応して複数の半田バンプ６を形成し、その後、多数個取り基板１０及び樹脂封止体１５を複数の個片に分割することより、本実施形態４の半導体装置がほぼ完成する。   Thereafter, the same process as in the first embodiment is performed, that is, a plurality of semiconductor chips 1 mounted on the main surface of the multi-chip substrate 10 are collectively sealed with one resin sealing body 15. After that, a plurality of solder bumps 6 are formed on the back surface of the multi-piece substrate 10 corresponding to each product formation region 13, and then the multi-piece substrate 10 and the resin sealing body 15 are divided into a plurality of pieces. The semiconductor device according to the fourth embodiment is almost completed.

本実施形態４の多数個取り基板１０は、その長手方向の両端部に複数の製品形成領域１３（チップ搭載領域１４）が偏って配置され、製品形成領域１３間の分離領域１２にスリット１６が設けられている。このような多数個取り基板１０を使用して半導体装置を製造することにより、本実施形態４においても、樹脂封止前の多数個取り基板１０の反り変形を低減することができる。   In the multi-chip substrate 10 according to the fourth embodiment, a plurality of product formation regions 13 (chip mounting regions 14) are arranged at both ends in the longitudinal direction, and slits 16 are formed in the separation regions 12 between the product formation regions 13. Is provided. By manufacturing a semiconductor device using such a multi-cavity substrate 10, also in the fourth embodiment, warping deformation of the multi-cavity substrate 10 before resin sealing can be reduced.

スリット１６は、できるだけ多く入れることが望ましいが、基板の余白部が限られ、部分的にしか入れられないとしても、ある程度の効果は期待できる。   Although it is desirable to insert as many slits 16 as possible, a certain degree of effect can be expected even if the margin of the substrate is limited and can be inserted only partially.

また、スリット１６は、製品形成領域１３の中に設けてもよい。但し、この場合は、製品形成領域１３（配線基板３）における配線の引き回し自由度が低下してしまうため、本実施形態４のように、製品形成領域１３間の分離領域１２にスリット１６を設けることが望ましい。   Further, the slit 16 may be provided in the product forming region 13. However, in this case, since the degree of freedom of wiring routing in the product formation region 13 (wiring substrate 3) is reduced, the slit 16 is provided in the separation region 12 between the product formation regions 13 as in the fourth embodiment. It is desirable.

また、スリット１６は、チップ搭載領域１４間に限らず、多数個取り基板１０の周縁とチップ搭載領域１４との間に設けてもよい。   The slit 16 is not limited to be provided between the chip mounting areas 14, and may be provided between the peripheral edge of the multi-chip substrate 10 and the chip mounting area 14.

なお、本実施形態４では、半導体チップ１の実装方法として、ワイヤボンディングによる方法について説明したが、本発明は、前述の実施形態２のように、半田バンプを溶融して半導体チップを実装する場合や、前述の実施形態２のように、ＡＣＦを用いて半導体チップを実装する場合等にも適用できる。   In the fourth embodiment, the wire bonding method has been described as the semiconductor chip 1 mounting method. However, in the present invention, the solder bump is melted and the semiconductor chip is mounted as in the second embodiment described above. In addition, the present invention can be applied to a case where a semiconductor chip is mounted using an ACF as in the second embodiment.

また、本実施形態４では、スリット１６及び製品形成領域１３（チップ搭載領域１４）の配置を工夫して、樹脂封止前の基板反り変形を低減した例について説明したが、接着材（接着用樹脂フィルム２ａ）の大きさを工夫して基板反り変形を低減する手段（実施形態１）、突起状電極（半田バンプ７）の配置を工夫して基板反り変形を低減する手段（実施形態２）、接着材（ＡＣＦ９）の大きさ及び突起状電極（スタッドバンプ８）の配置を工夫して基板反り変形を低減する手段（実施形態３）のうちの何れかと本実施形態４とを組み合わせてもよい。この場合、更に樹脂封止前の基板反り変形を低減することができる。   In the fourth embodiment, the example in which the slit 16 and the product formation region 13 (chip mounting region 14) are arranged to reduce the warpage of the substrate before resin sealing has been described. A means for reducing the warpage deformation of the substrate by devising the size of the resin film 2a) (Embodiment 1), and a means for reducing the warpage deformation of the substrate by devising the arrangement of the protruding electrodes (solder bumps 7) (Embodiment 2). Even if any one of the means (embodiment 3) for reducing the warpage of the substrate by devising the size of the adhesive (ACF9) and the arrangement of the protruding electrodes (stud bumps 8) is combined with the present embodiment 4. Good. In this case, it is possible to further reduce the warpage deformation of the substrate before resin sealing.

（実施形態５）
本実施形態５では、基板の厚さを部分的に変えて、樹脂封止前の基板反り変形を低減した例について説明する。 (Embodiment 5)
In the fifth embodiment, an example will be described in which the thickness of the substrate is partially changed to reduce the warpage deformation of the substrate before resin sealing.

図２２は、本実施形態５の半導体装置の製造において、基板に半導体チップを実装した状態を示す模式的平面図であり、
図２３は、図２２のａ−ａ線に沿う模式的断面図であり、
図２４は、本実施形態５の半導体装置の内部構造を示す模式的断面図である。 FIG. 22 is a schematic plan view showing a state in which a semiconductor chip is mounted on a substrate in the manufacture of the semiconductor device of Embodiment 5.
FIG. 23 is a schematic cross-sectional view along the line aa in FIG.
FIG. 24 is a schematic cross-sectional view showing the internal structure of the semiconductor device according to the fifth embodiment.

図２２及び図２３に示すように、多数個取り基板１０の主面には、各製品形成領域１３のチップ搭載領域１４に対応して、複数の半導体チップ１が実装されている。本実施形態５において、半導体チップ１の実装は、詳細に図示していないが、例えば、前述の実施形態１と同様の方法、即ち、多数個取り基板１０の主面に接着材２を介在して半導体チップ１の裏面を接着固定し、その後、半導体チップ１の電極パッドと多数個取り基板１０の主面の電極パッドとをボンディングワイヤで接続することによって行われている。   As shown in FIG. 22 and FIG. 23, a plurality of semiconductor chips 1 are mounted on the main surface of the multi-chip substrate 10 so as to correspond to the chip mounting area 14 of each product formation area 13. In the fifth embodiment, the mounting of the semiconductor chip 1 is not shown in detail, but for example, the same method as in the first embodiment described above, that is, the adhesive 2 is interposed on the main surface of the multi-chip substrate 10. Then, the back surface of the semiconductor chip 1 is bonded and fixed, and then the electrode pads of the semiconductor chip 1 and the electrode pads on the main surface of the multi-chip substrate 10 are connected by bonding wires.

本実施形態５において、多数個取り基板１０は、前述の実施形態１と異なり、厚手領域（第１の厚さの領域）１７ａと、この厚手領域１７ａよりも厚さが薄い薄手領域（第２の厚さ領域）１７ｂとを有する構成になっている。また、複数の製品形成領域１３、複数のチップ搭載領域１４、そして実装後の複数の半導体チップ１は、前述の実施形態４と同様に、２つのブロック（群）に別れて配置されており、この２つのブロックは、ブロックの間隔が製品形成領域１３の間隔よりも広くなるように、多数個取り基板１０の長手方向（Ｘ方向）に離間して配置（多数個取り基板１０の長手方向において互いに反対側に位置する両端部に偏って配置）されている。   In the fifth embodiment, the multi-piece substrate 10 is different from the first embodiment in that the thick area (first thickness area) 17a and the thin area (second area) thinner than the thick area 17a. Thickness region) 17b. Further, the plurality of product formation regions 13, the plurality of chip mounting regions 14, and the plurality of semiconductor chips 1 after mounting are arranged separately in two blocks (groups), as in the above-described fourth embodiment. These two blocks are arranged apart from each other in the longitudinal direction (X direction) of the multi-chip substrate 10 (in the longitudinal direction of the multi-chip substrate 10) so that the interval between the blocks is wider than the interval between the product forming regions 13. (Disposed on both ends located opposite to each other).

２つのブロック間の領域、及び各製品形成領域１３は、主に厚手領域１７ａで形成され、製品形成領域１３間の分離領域１２、及び製品形成領域１３と多数個取り基板１０の周縁との間の領域は、主に薄手領域１７ｂで形成されている。本実施形態５においては、製品形成領域１３の周縁部も薄手領域１７ｂで形成されている。   The region between the two blocks and each product formation region 13 are mainly formed by the thick region 17a, and the separation region 12 between the product formation regions 13 and between the product formation region 13 and the periphery of the multi-chip substrate 10 are formed. This region is mainly formed by the thin region 17b. In the fifth embodiment, the peripheral portion of the product formation region 13 is also formed by the thin region 17b.

本実施形態５において、厚手領域１７ａ、及び薄手領域１７ｂは、多数個取り基板１０の主面側（チップ搭載面側）に段差を付けることによって形成され、多数個取り基板１０の裏面は、その主面よりも平坦になっている。薄手領域１７ｂの厚さは、例えば厚手領域１７ａの約半分になっている。   In the fifth embodiment, the thick region 17a and the thin region 17b are formed by providing a step on the main surface side (chip mounting surface side) of the multi-cavity substrate 10, and the back surface of the multi-cavity substrate 10 is It is flatter than the main surface. The thickness of the thin area 17b is, for example, about half that of the thick area 17a.

この後、前述の実施形態１と同様の工程を施すことにより、即ち、多数個取り基板１０の主面に実装された複数の半導体チップ１を１つの樹脂封止体１５で一括して樹脂封止し、その後、多数個取り基板１０の裏面に、各製品形成領域１３に対応して複数の半田バンプ６を形成し、その後、多数個取り基板１０及び樹脂封止体１５を複数の個片に分割することより、図２４に示す本実施形態５の半導体装置がほぼ完成する。   Thereafter, the same process as in the first embodiment is performed, that is, a plurality of semiconductor chips 1 mounted on the main surface of the multi-chip substrate 10 are collectively sealed with one resin sealing body 15. After that, a plurality of solder bumps 6 are formed on the back surface of the multi-piece substrate 10 corresponding to each product formation region 13, and then the multi-piece substrate 10 and the resin sealing body 15 are divided into a plurality of pieces. The semiconductor device of the fifth embodiment shown in FIG. 24 is almost completed.

本実施形態５の多数個取り基板１０は、その長手方向の両端部に複数の製品形成領域１３（チップ搭載領域１４）が偏って配置されており、更に厚手領域１７ａ及び薄手領域１７ｂを有する構成になっている。このような多数個取り基板１０を使用して半導体装置を製造することにより、本実施形態５においても、樹脂封止前の多数個取り基板１０の反り変形を低減することができる。   The multi-chip substrate 10 according to the fifth embodiment has a configuration in which a plurality of product formation regions 13 (chip mounting regions 14) are arranged at both ends in the longitudinal direction and further have a thick region 17a and a thin region 17b. It has become. By manufacturing a semiconductor device using such a multi-chip substrate 10, warping deformation of the multi-chip substrate 10 before resin sealing can be reduced also in the fifth embodiment.

薄手領域１７ｂは、できるだけ多く設けることが望ましいが、基板の余白部が限られ、部分的にしか入れられないとしても、ある程度の効果は期待できる。   Although it is desirable to provide as many thin regions 17b as possible, a certain degree of effect can be expected even if the margin of the substrate is limited and only part of the thin regions 17b can be inserted.

また、図２４に示すように、個片化後、配線基板３に薄手領域１７ｂがのこっても問題ない。   Further, as shown in FIG. 24, there is no problem even if the thin area 17b is left on the wiring board 3 after the separation.

また、薄手領域１７ｂは、製品形成領域１３の中に部分的に設けてもよく、また、製品形成領域１３を薄手領域１７ｂで形成してもよい。但し、この場合は、製品形成領域１３（配線基板３）における配線の引き回し自由度が低下してしまうため、本実施形態５のように、基板の余白分部に薄手領域１７ｂを設けることが望ましい。   The thin area 17b may be partially provided in the product forming area 13, or the product forming area 13 may be formed by the thin area 17b. However, in this case, since the degree of freedom of wiring routing in the product formation region 13 (wiring substrate 3) decreases, it is desirable to provide the thin region 17b in the margin portion of the substrate as in the fifth embodiment. .

なお、本実施形態５では、半導体チップ１の実装方法として、ワイヤボンディングによる方法について説明したが、本発明は、前述の実施形態２のように、半田バンプを溶融して半導体チップを実装する場合や、前述の実施形態３のように、ＡＣＦを用いて半導体チップを実装する場合等にも適用できる。   In the fifth embodiment, the wire bonding method has been described as the semiconductor chip 1 mounting method. However, in the present invention, the solder bump is melted and the semiconductor chip is mounted as in the second embodiment described above. In addition, the present invention can also be applied to a case where a semiconductor chip is mounted using ACF as in the third embodiment.

また、本実施形態５では、基板の厚さ及び製品形成領域１３（チップ搭載領域１４）の配置を工夫して、樹脂封止前の基板反り変形を低減した例について説明したが、接着材（接着用樹脂フィルム２ａ）の大きさを工夫して基板反り変形を低減する手段（実施形態１）、突起状電極（半田バンプ７）の配置を工夫して基板反り変形を低減する手段（実施形態２）、接着材（ＡＣＦ９）の大きさ及び突起状電極（スタッドバンプ８）の配置を工夫して基板反り変形を低減する手段（実施形態３）のうちの何れかと本実施形態４とを組み合わせてもよい。この場合、更に樹脂封止前の基板反り変形を低減することができる。   In the fifth embodiment, the example in which the thickness of the substrate and the arrangement of the product formation region 13 (chip mounting region 14) are devised to reduce the warpage of the substrate before resin sealing has been described. Means for reducing the warpage deformation of the substrate by devising the size of the adhesive resin film 2a) (Embodiment 1), Means for reducing the warpage deformation of the substrate by devising the arrangement of the protruding electrodes (solder bumps 7) (Embodiment 1) 2) A combination of the fourth embodiment with any one of the means (third embodiment) for reducing the warpage of the substrate by devising the size of the adhesive (ACF9) and the arrangement of the protruding electrodes (stud bumps 8) May be. In this case, it is possible to further reduce the warpage deformation of the substrate before resin sealing.

図２５は、本実施形態５の変形例である半導体装置の製造において、基板に半導体チップを実装した状態を示す模式的平面図であり、
図２６は、図２５のａ−ａ線に沿う模式的断面図であり、
図２７は、本実施形態５の変形例である半導体装置の内部構造を示す模式的断面図である。 FIG. 25 is a schematic plan view showing a state in which a semiconductor chip is mounted on a substrate in the manufacture of a semiconductor device which is a modification of the fifth embodiment.
FIG. 26 is a schematic cross-sectional view along the line aa in FIG.
FIG. 27 is a schematic cross-sectional view showing the internal structure of a semiconductor device which is a modification of the fifth embodiment.

前述の実施形態５では、多数個取り基板１０の主面側（チップ搭載面側）に段差を付けることによって厚手領域１７ａ及び薄手領域１７ｂを形成している。これに対し、本変形例では、図２５及び図２６に示すように、多数個取り基板１０の裏面（チップ搭載面と反対側の面）側に段差を付けることによって厚手領域１７ａ及び薄手領域１７ｂを形成している。本変形例においても、できるだけ多く入れることが望ましいが、基板の余白部が限られ、部分的にしか入れられないとしても、ある程度の効果は期待できる。   In the above-described fifth embodiment, the thick region 17a and the thin region 17b are formed by providing a step on the main surface side (chip mounting surface side) of the multi-cavity substrate 10. On the other hand, in this modification, as shown in FIGS. 25 and 26, a thick region 17a and a thin region 17b are formed by providing a step on the back surface (surface opposite to the chip mounting surface) side of the multi-chip substrate 10. Is forming. Even in this modification, it is desirable to put in as much as possible, but even if the margin of the substrate is limited and only a part can be put in, a certain degree of effect can be expected.

また、図２７に示すように、個片化後、配線基板３に薄手領域１７ｂが残っても問題ない。   In addition, as shown in FIG. 27, there is no problem even if the thin area 17b remains on the wiring board 3 after separation.

（実施形態６）
本実施形態６では、ＭＣＰ（Ｍulti Ｃhip Ｐackage）型半導体装置に本発明を適用した例について説明する。図２８は、本実施形態６の半導体装置の内部構造を示す模式的断面図である。 (Embodiment 6)
In the sixth embodiment, an example in which the present invention is applied to an MCP (Multi Chip Package) type semiconductor device will be described. FIG. 28 is a schematic cross-sectional view showing the internal structure of the semiconductor device according to the sixth embodiment.

図２８に示すように、本実施形態６の半導体装置は、配線基板３の主面３ｘに複数の半導体チップ１が実装されており、複数の半導体チップ１は、配線基板３の主面３ｘ上に形成された樹脂封止体４によって封止されている。各半導体チップ１は、例えば前述の実施形態１と同様の方法で配線基板３の主面に実装されている。   As shown in FIG. 28, in the semiconductor device of the sixth embodiment, a plurality of semiconductor chips 1 are mounted on the main surface 3x of the wiring board 3, and the plurality of semiconductor chips 1 are on the main surface 3x of the wiring board 3. It is sealed by the resin sealing body 4 formed in the above. Each semiconductor chip 1 is mounted on the main surface of the wiring board 3 by, for example, the same method as in the first embodiment.

ＭＣＰの場合、１つの半導体チップを内蔵するパッケージと比較して配線基板３の外形サイズが大きくなるため、製造工程中に生じる基板の反りが問題となる。従って、本発明は、本実施形態６のＭＣＰ型半導体装置においても有効である。   In the case of MCP, since the outer size of the wiring board 3 is larger than that of a package containing one semiconductor chip, warping of the board that occurs during the manufacturing process becomes a problem. Therefore, the present invention is also effective in the MCP type semiconductor device of the sixth embodiment.

以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

例えば、樹脂封止型半導体装置の製造においては、複数の製品形成領域を有する多数取り基板を使用し、各製品形成領域に実装された半導体チップを各製品形成領域毎に樹脂封止する個別方式のトランスファモールディング法や、複数の製品形成領域を有する多数個取り基板を使用し、各製品形成領域に実装された半導体チップを一括して樹脂封止する一括方式のトランスファモールディング法が採用されている。前述の実施形態では、一括方式のトランスファモールディング法により製造される半導体装置について説明したが、本発明は、個別方式のトランスファ・モールディング法により製造される半導体装置にも適用できる。   For example, in the manufacture of resin-encapsulated semiconductor devices, an individual method is used in which a multi-chip substrate having a plurality of product formation regions is used, and a semiconductor chip mounted in each product formation region is resin-sealed for each product formation region The transfer molding method and the batch transfer molding method that uses a multi-piece substrate having a plurality of product formation regions and collectively seals the semiconductor chips mounted in each product formation region are employed. . In the above-described embodiment, the semiconductor device manufactured by the batch transfer molding method has been described. However, the present invention can also be applied to a semiconductor device manufactured by the individual transfer molding method.

また、前述の実施形態では、主にＢＧＡ型半導体装置について説明したが、基板の裏面の半田バンプを省略し、基板の裏面の電極パッドを外部接続用端子とするＬＧＡ（Ｌahd Ｇrid Ａrray）型半導体装置にも適用できる。   In the above-described embodiments, the BGA type semiconductor device has been mainly described. However, a solder bump on the back surface of the substrate is omitted, and an LGA (Lahd Grid Array) type semiconductor in which the electrode pad on the back surface of the substrate is an external connection terminal. It can also be applied to devices.

本発明の実施形態１である半導体装置の内部構造を示す図（（ａ）は模式的断面図，（ｂ）は模式的平面図）である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure ((a) is typical sectional drawing, (b) is typical plan view) which shows the internal structure of the semiconductor device which is Embodiment 1 of this invention. 一括モールドによる半導体装置の製造概要を示す模式図である。It is a schematic diagram which shows the manufacture outline | summary of the semiconductor device by collective molding. 本発明の実施形態１である半導体装置の製造に使用される基板（多数個取り基板）の概略構成を示す模式的平面図である。It is a typical top view which shows schematic structure of the board | substrate (multi-piece substrate) used for manufacture of the semiconductor device which is Embodiment 1 of this invention. 本発明の実施形態１である半導体装置の製造において、基板のチップ搭載領域に接着材を配置した状態を示す模式的平面図である。FIG. 5 is a schematic plan view showing a state in which an adhesive material is arranged in a chip mounting region of a substrate in the manufacture of the semiconductor device according to the first embodiment of the present invention. 本発明の実施形態１である半導体装置の製造において、基板のチップ搭載領域に半導体チップを搭載した状態を示す模式的平面図である。FIG. 5 is a schematic plan view showing a state in which a semiconductor chip is mounted on a chip mounting region of a substrate in the manufacture of the semiconductor device according to the first embodiment of the present invention. 本発明の実施形態１である半導体装置の製造において、基板のチップ搭載領域に半導体チップを搭載した状態を示す模式的平面図である。FIG. 5 is a schematic plan view showing a state in which a semiconductor chip is mounted on a chip mounting region of a substrate in the manufacture of the semiconductor device according to the first embodiment of the present invention. 本発明の実施形態１である半導体装置の製造において、ワイヤボンディング工程を示す模式的平面図である。FIG. 5 is a schematic plan view showing a wire bonding process in the manufacture of the semiconductor device according to the first embodiment of the present invention. 本発明の実施形態１である半導体装置の製造において形成された樹脂封止体を示す模式的平面図である。It is a typical top view which shows the resin sealing body formed in manufacture of the semiconductor device which is Embodiment 1 of this invention. 本発明の実施形態１である半導体装置の製造において、切断工程を示す模式的平面図である。It is a schematic plan view which shows a cutting process in manufacture of the semiconductor device which is Embodiment 1 of this invention. 解析に用いたモデルの１例を示す図である。It is a figure which shows an example of the model used for the analysis. 基板に複数の半導体チップを搭載した状態を示す模式的平面図（（ａ）は第１の半導体チップの場合，（ｂ）は（ａ）の第１の半導体チップよりも小さい第２の半導体チップの場合）である。Schematic plan view showing a state where a plurality of semiconductor chips are mounted on a substrate ((a) is a first semiconductor chip, (b) is a second semiconductor chip smaller than the first semiconductor chip of (a)) In the case of スリットの入れ方、半導体チップ配置の違いによる、基板反り量の違いを解析によって検討した結果を示す図（（ａ）乃至（ｈ））である。It is the figure ((a) thru | or (h)) which shows the result of having examined by analysis the difference in the amount of substrate curvature by the difference in how to insert a slit, and a semiconductor chip arrangement. 半導体チップを基板の両端に配置した場合の反り変形を示す図である。It is a figure which shows the curvature deformation | transformation at the time of arrange | positioning a semiconductor chip to the both ends of a board | substrate. 基板の両端に半導体チップを配置し、スリットを入れた場合の１例を示す図である。It is a figure which shows an example at the time of arrange | positioning a semiconductor chip to the both ends of a board | substrate, and putting the slit. 本発明の実施形態２である半導体装置の内部構造を示す図（（ａ）は模式的断面図，（ｂ）は模式的平面図）である。It is a figure ((a) is a typical sectional view and (b) is a typical top view) showing an internal structure of a semiconductor device which is Embodiment 2 of the present invention. 本発明の実施形態２である半導体装置の製造工程中のチップ実装工程を示す模式的断面図である。It is typical sectional drawing which shows the chip | tip mounting process in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. 本発明の実施形態２の変形例である半導体チップの模式的平面図である。It is a typical top view of the semiconductor chip which is a modification of Embodiment 2 of the present invention. 本発明の実施形態３である半導体装置の内部構造を示す図（（ａ）は模式的断面図，（ｂ）は模式的平面図）である。It is a figure ((a) is a typical sectional view and (b) is a typical top view) showing an internal structure of a semiconductor device which is Embodiment 3 of the present invention. 本発明の実施形態３である半導体装置の製造工程中のチップ実装工程を示す模式的断面図である。It is typical sectional drawing which shows the chip | tip mounting process in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. 本発明の実施形態４である半導体装置の製造において、基板に半導体チップを実装した状態を示す模式的平面図である。FIG. 9 is a schematic plan view showing a state in which a semiconductor chip is mounted on a substrate in the manufacture of a semiconductor device that is Embodiment 4 of the present invention. 図２０のａ−ａ線に沿う模式的断面図である。It is typical sectional drawing in alignment with the aa line of FIG. 本発明の実施形態５である半導体装置の製造において、基板に半導体チップを実装した状態を示す模式的平面図である。In manufacture of the semiconductor device which is Embodiment 5 of this invention, it is a schematic plan view which shows the state which mounted the semiconductor chip in the board | substrate. 図２２のａ−ａ線に沿う模式的断面図である。It is typical sectional drawing which follows the aa line of FIG. 本発明の実施形態５である半導体装置の内部構造を示す模式的断面図である。It is typical sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 5 of this invention. 本発明の実施形態５の変形例である半導体装置の製造において、基板に半導体チップを実装した状態を示す模式的平面図である。FIG. 10 is a schematic plan view showing a state in which a semiconductor chip is mounted on a substrate in the manufacture of a semiconductor device which is a modified example of Embodiment 5 of the present invention. 図２５のａ−ａ線に沿う模式的断面図である。It is typical sectional drawing which follows the aa line of FIG. 本発明の実施形態５の変形例である半導体装置の内部構造を示す模式的断面図である。It is a typical sectional view showing an internal structure of a semiconductor device which is a modification of Embodiment 5 of the present invention. 本発明の実施形態６である半導体装置の内部構造を示す模式的断面図である。It is typical sectional drawing which shows the internal structure of the semiconductor device which is Embodiment 6 of this invention.

符号の説明Explanation of symbols

１…半導体チップ（半導体素子）、２…接着材、３…配線基板、４…樹脂封止体、５…ボンディングワイヤ、６…半田バンプ、７…半田バンプ、８…スタッドバンプ、９…ＡＣＦ、
１０…基板（多数個取り基板）、１１…モールド領域、１２…分離領域、１３…製品形成領域（デバイス形成領域）、１４…チップ搭載領域、１５…樹脂封止体、１６…スリット、１７ａ…厚手領域、１７ｂ…薄手領域。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip (semiconductor element), 2 ... Adhesive material, 3 ... Wiring board, 4 ... Resin sealing body, 5 ... Bonding wire, 6 ... Solder bump, 7 ... Solder bump, 8 ... Stud bump, 9 ... ACF,
DESCRIPTION OF SYMBOLS 10 ... Substrate (multiple substrate), 11 ... Mold area, 12 ... Separation area, 13 ... Product formation area (device formation area), 14 ... Chip mounting area, 15 ... Resin sealing body, 16 ... Slit, 17a ... Thick area, 17b ... thin area.

Claims (16)

基板の主面に、夫々接着材を介在して複数の半導体チップを接着固定する（ａ）工程を有し、
前記（ａ）工程において、前記基板と前記半導体チップとの間における前記接着材の面積は、前記半導体チップの面積よりも小さくなっていることを特徴とする半導体装置の製造方法。 (A) a step of adhering and fixing a plurality of semiconductor chips to the main surface of the substrate, respectively, with an adhesive interposed;
In the step (a), the area of the adhesive between the substrate and the semiconductor chip is smaller than the area of the semiconductor chip. 請求項１に記載の半導体装置の製造方法において、
前記接着材は、前記半導体チップの接着面の全面とは接触せず、前記半導体チップの接着面の中央部付近のみ接触していることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the adhesive is not in contact with the entire bonding surface of the semiconductor chip and is in contact with only the vicinity of the center of the bonding surface of the semiconductor chip. 請求項１に記載の半導体装置の製造方法において、
前記（ａ）工程の後、前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する（ｂ）工程を更に有することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
After the step (a), the method further includes a step (b) of forming a resin sealing body that collectively seals the plurality of semiconductor chips. 請求項１に記載の半導体装置の製造方法において、
前記（ａ）工程の後、前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する（ｂ）工程と、前記基板及び前記樹脂封止体を複数の個片に分割する（ｃ）工程とを更に有することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
After the step (a), a step (b) of forming a resin sealing body that collectively resin seals the plurality of semiconductor chips, and dividing the substrate and the resin sealing body into a plurality of pieces. (C) The manufacturing method of the semiconductor device characterized by further including a process. 配線基板と、
前記配線基板の主面に接着材を介在して接着固定された半導体チップと、
前記配線基板の接続部と前記半導体素子の接続部とを電気的に接続する接続手段と、
前記配線基板の主面上に形成され、前記半導体チップ及び前記接続手段を封止する樹脂封止体とを有し、
前記配線基板と前記半導体チップとの間における前記接着材の面積は、前記半導体チップの面積よりも小さくなっていることを特徴とする半導体装置。 A wiring board;
A semiconductor chip bonded and fixed to the main surface of the wiring board with an adhesive interposed therebetween;
Connection means for electrically connecting the connection portion of the wiring board and the connection portion of the semiconductor element;
A resin sealing body that is formed on the main surface of the wiring board and seals the semiconductor chip and the connection means;
The semiconductor device according to claim 1, wherein an area of the adhesive between the wiring board and the semiconductor chip is smaller than an area of the semiconductor chip. 請求項５に記載の半導体装置において、
前記配線基板と前記半導体チップとの間は、前記接着材が設けられた第１の領域と、前記樹脂封止体の樹脂が設けられた第２の領域とを有し、
前記第１の領域は、前記第２の領域で周囲を囲まれていることを特徴とする半導体装置。 The semiconductor device according to claim 5,
Between the wiring board and the semiconductor chip, it has a first region where the adhesive is provided and a second region where the resin of the resin sealing body is provided,
The semiconductor device according to claim 1, wherein the first region is surrounded by the second region. 基板の主面に、夫々複数の突起状電極を介在して複数の半導体チップを実装する（ａ）工程と、
前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する（ｂ）工程と、
前記基板及び前記樹脂封止体を複数の個片に分割する（ｃ）工程とを有し、
前記（ａ）工程において、前記基板と前記半導体チップとの間における前記複数の突起状電極は、前記半導体チップの主面の全面に均等に配置されず、前記半導体チップの主面の中央部に偏って配置されていることを特徴とする半導体装置の製造方法。 (A) a step of mounting a plurality of semiconductor chips on the main surface of the substrate via a plurality of protruding electrodes, respectively;
A step (b) of forming a resin sealing body that collectively seals the plurality of semiconductor chips;
(C) dividing the substrate and the resin sealing body into a plurality of pieces,
In the step (a), the plurality of protruding electrodes between the substrate and the semiconductor chip are not evenly arranged on the entire main surface of the semiconductor chip, and are formed in the central portion of the main surface of the semiconductor chip. A method of manufacturing a semiconductor device, characterized in that the semiconductor devices are arranged in a biased manner. 基板の主面に、夫々接着材及び複数の突起状電極を介在して複数の半導体チップを実装する（ａ）工程と、
前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する（ｂ）工程と、
前記基板及び前記樹脂封止体を複数の個片に分割する（ｃ）工程とを有し、
前記（ａ）工程において、前記基板と前記半導体チップとの間における前記複数の突起状電極は、前記半導体チップの主面の全面に均等に配置されず、前記半導体チップの主面の中央部に偏って配置され、前記基板と前記半導体チップとの間における前記接着材は、前記半導体チップの主面の全面とは接触せず、前記複数の突起状電極を含むように、前記半導体チップの主面の中央部に接触していることを特徴とする半導体装置の製造方法。 (A) a step of mounting a plurality of semiconductor chips on the main surface of the substrate via an adhesive and a plurality of protruding electrodes, respectively.
A step (b) of forming a resin sealing body that collectively seals the plurality of semiconductor chips;
(C) dividing the substrate and the resin sealing body into a plurality of pieces,
In the step (a), the plurality of protruding electrodes between the substrate and the semiconductor chip are not evenly arranged on the entire main surface of the semiconductor chip, and are formed in the central portion of the main surface of the semiconductor chip. The main part of the semiconductor chip is arranged in a biased manner so that the adhesive between the substrate and the semiconductor chip does not contact the entire main surface of the semiconductor chip and includes the plurality of protruding electrodes. A method of manufacturing a semiconductor device, wherein the semiconductor device is in contact with a central portion of the surface. 請求項８に記載の半導体装置の製造方法において、
前記接着材は、熱硬化性樹脂であることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 8,
The method for manufacturing a semiconductor device, wherein the adhesive is a thermosetting resin. 複数のチップ搭載領域と、前記チップ搭載領域間に配置されたスリットとを有する基板を準備する工程と、
前記複数のチップ搭載領域の夫々に、半導体チップを実装する工程と、
前記複数のチップ搭載領域に実装された前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する工程と、
前記基板及び前記樹脂封止体を複数の個片に分割する工程とを有することを特徴とする半導体装置の製造方法。 Preparing a substrate having a plurality of chip mounting areas and a slit disposed between the chip mounting areas;
Mounting a semiconductor chip in each of the plurality of chip mounting regions;
Forming a resin encapsulant that collectively encapsulates the plurality of semiconductor chips mounted on the plurality of chip mounting regions;
And a step of dividing the substrate and the resin sealing body into a plurality of pieces. 請求項１０に記載の半導体装置の製造方法において、
前記複数のチップ搭載領域は、前記基板の両端に偏って配置されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 10,
The method of manufacturing a semiconductor device, wherein the plurality of chip mounting regions are arranged at both ends of the substrate. 第１の厚さ領域と、前記第１の厚さ領域よりも薄い第２の厚さ領域と、複数のチップ搭載領域とを有する基板を準備する工程と、
前記複数のチップ搭載領域の夫々に、半導体チップを実装する工程と、
前記複数のチップ搭載領域に実装された前記複数の半導体チップを一括して樹脂封止する樹脂封止体を形成する工程と、
前記基板及び前記樹脂封止体を複数の個片に分割する工程とを有することを特徴とする半導体装置の製造方法。 Preparing a substrate having a first thickness region, a second thickness region thinner than the first thickness region, and a plurality of chip mounting regions;
Mounting a semiconductor chip in each of the plurality of chip mounting regions;
Forming a resin encapsulant that collectively encapsulates the plurality of semiconductor chips mounted on the plurality of chip mounting regions;
And a step of dividing the substrate and the resin sealing body into a plurality of pieces. 請求項１２に記載の半導体装置の製造方法において、
前記複数のチップ搭載領域は、前記第１の厚さ領域に形成され、
前記第２の厚さ領域は、前記チップ搭載領域間に形成されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 12,
The plurality of chip mounting regions are formed in the first thickness region,
The method for manufacturing a semiconductor device, wherein the second thickness region is formed between the chip mounting regions. 請求項１２に記載の半導体装置の製造方法において、
前記複数のチップ搭載領域は、前記基板の両端に偏って配置されていることを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the plurality of chip mounting regions are arranged at both ends of the substrate. 請求項１、請求項７、請求項８のうちの何れか１項に記載の半導体装置の製造方法において、
前記基板は、スリットを有し、
前記複数の半導体チップは、前記基板の両端に偏って配置されていることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device of any one of Claim 1, Claim 7, Claim 8,
The substrate has a slit;
The method of manufacturing a semiconductor device, wherein the plurality of semiconductor chips are arranged at both ends of the substrate.
請求項１、請求項７、請求項８のうちの何れか１項に記載の半導体装置の製造方法において、
前記基板は、第１の厚さ領域と、前記第１の厚さ領域よりも薄い第２の厚さ領域とを有し、
前記複数の半導体チップは、前記基板の両端に偏って配置されていることを特徴とする半導体装置の製造方法。
In the manufacturing method of the semiconductor device of any one of Claim 1, Claim 7, Claim 8,
The substrate has a first thickness region and a second thickness region thinner than the first thickness region;
The method of manufacturing a semiconductor device, wherein the plurality of semiconductor chips are arranged at both ends of the substrate.
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JP2014063902A (en) * 2012-09-21 2014-04-10 Tdk Corp Semiconductor ic built-in substrate and manufacturing method of the same
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JP2014063902A (en) * 2012-09-21 2014-04-10 Tdk Corp Semiconductor ic built-in substrate and manufacturing method of the same
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