JP2014063902A - Semiconductor ic built-in substrate and manufacturing method of the same - Google Patents

Semiconductor ic built-in substrate and manufacturing method of the same Download PDF

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JP2014063902A
JP2014063902A JP2012208566A JP2012208566A JP2014063902A JP 2014063902 A JP2014063902 A JP 2014063902A JP 2012208566 A JP2012208566 A JP 2012208566A JP 2012208566 A JP2012208566 A JP 2012208566A JP 2014063902 A JP2014063902 A JP 2014063902A
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semiconductor
resin
substrate
built
hole
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JP5998792B2 (en
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Kazutoshi Tsuyutani
和俊 露谷
Hiroshige Okawa
博茂 大川
Yoshihiro Suzuki
義弘 鈴木
Tsutomu Mochizuki
強 望月
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TDK Corp
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TDK Corp
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Priority to JP2012208566A priority Critical patent/JP5998792B2/en
Priority to US14/032,093 priority patent/US9635756B2/en
Priority to CN201310432296.XA priority patent/CN103681526B/en
Priority to CN201610346620.XA priority patent/CN106024725B/en
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    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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Abstract

PROBLEM TO BE SOLVED: To provide an ultrathin semiconductor IC built-in substrate.SOLUTION: A semiconductor IC built-in substrate manufacturing method comprises: preparing a pregreg 111a which has a core material impregnated with uncured resin and a through hole 112a provided to pierce the core material and the resin so as to be surrounded by the core material and the resin in plan view; and subsequently housing a semiconductor IC120 in the through hole 112a and performing thermal press on the pregreg 111a in this condition to cause a part of the resin to flow into the through hole 112a, and thereby to embed the semiconductor IC120 housed in the through hole 112a, by the inflowing resin. In the present embodiment, since the semiconductor IC120 is embedded by the inflowing resin with no core material above and under the semiconductor IC120, an ultrathin structure without core parts above and under the semiconductor IC120 can be achieved.

Description

本発明は半導体ＩＣ内蔵基板及びその製造方法に関し、特に、超薄型の半導体ＩＣ内蔵基板及びその製造方法に関する。   The present invention relates to a semiconductor IC-embedded substrate and a manufacturing method thereof, and more particularly to an ultra-thin semiconductor IC-embedded substrate and a manufacturing method thereof.

一般的なプリント基板においては、基板の表面に半導体ＩＣなどの電子デバイスが複数実装され、基板内部の配線層を介してこれら電子デバイス間の接続が行われる。しかしながら、このようなタイプのプリント基板は全体の厚みを薄くすることが困難であるため、スマートフォンなど薄型化が要求される機器向けのプリント基板としては、半導体ＩＣを樹脂層に埋め込んだタイプの半導体ＩＣ内蔵基板が用いられることがある（特許文献１参照）。   In a general printed board, a plurality of electronic devices such as semiconductor ICs are mounted on the surface of the board, and these electronic devices are connected via a wiring layer inside the board. However, since it is difficult to reduce the overall thickness of such a type of printed circuit board, as a printed circuit board for devices that require a reduction in thickness, such as a smartphone, a semiconductor in which a semiconductor IC is embedded in a resin layer An IC-embedded substrate may be used (see Patent Document 1).

特開２００２−２４６７６１号公報JP 2002-246761 A

しかしながら、特許文献１に記載された半導体ＩＣ内蔵基板は、コア層に設けられた凹部に半導体ＩＣを収容していることから、半導体ＩＣの下部にもコア層が存在する。このため、全体の厚みをより薄くすることは困難であった。全体の厚みをより薄くするためには、半導体ＩＣの下部に位置するコア層を削除することが考えられるが、この場合、半導体ＩＣを正しく保持することができなくなってしまう。   However, since the semiconductor IC built-in substrate described in Patent Document 1 accommodates the semiconductor IC in the recess provided in the core layer, the core layer also exists below the semiconductor IC. For this reason, it was difficult to make the whole thickness thinner. In order to make the entire thickness thinner, it is conceivable to delete the core layer located under the semiconductor IC. However, in this case, the semiconductor IC cannot be held correctly.

したがって、本発明は、より薄型な半導体ＩＣ内蔵基板及びその製造方法を提供することを目的とする。   Accordingly, it is an object of the present invention to provide a thinner semiconductor IC-embedded substrate and a method for manufacturing the same.

本発明による半導体ＩＣ内蔵基板は、樹脂基板と、前記樹脂基板に埋め込まれた半導体ＩＣとを備え、前記樹脂基板は、芯材に所定の樹脂が含浸されてなるコア部と、平面的に見て前記コア部に囲まれるよう前記コア部を貫通して設けられた収容部とを含み、前記半導体ＩＣは、前記収容部に充填された前記所定の樹脂に埋め込まれていることを特徴とする。   A semiconductor IC-embedded substrate according to the present invention includes a resin substrate and a semiconductor IC embedded in the resin substrate, and the resin substrate includes a core portion in which a core material is impregnated with a predetermined resin and a planar view. And a housing portion provided through the core portion so as to be surrounded by the core portion, wherein the semiconductor IC is embedded in the predetermined resin filled in the housing portion. .

本発明によれば、コア部を貫通して設けられた収容部に半導体ＩＣが埋め込まれていることから、半導体ＩＣの上下にコア部が存在しない。このため、全体の厚みを非常に薄くすることが可能である。しかも、コア部に含浸された樹脂と収容部に充填された樹脂が同じであることから、熱膨張係数の差などに起因する変形などが生じることもない。   According to the present invention, since the semiconductor IC is embedded in the accommodating portion provided through the core portion, the core portion does not exist above and below the semiconductor IC. For this reason, it is possible to make the whole thickness very thin. In addition, since the resin impregnated in the core part and the resin filled in the housing part are the same, deformation due to a difference in thermal expansion coefficient or the like does not occur.

本発明においては、前記樹脂基板の一方の表面に形成され、前記半導体ＩＣの外部端子に接続された配線層と、前記配線層を覆うレジスト膜とをさらに備えることが好ましい。これによれば、単純な構造で半導体ＩＣの外部端子を外部に接続することが可能となる。   In the present invention, it is preferable to further include a wiring layer formed on one surface of the resin substrate and connected to an external terminal of the semiconductor IC, and a resist film covering the wiring layer. According to this, it becomes possible to connect the external terminal of the semiconductor IC to the outside with a simple structure.

本発明においては、前記樹脂基板の他方の表面には配線層が設けられていないことが好ましい。これによれば、配線層が１層のみとなることから、全体の厚みをより薄くすることが可能となる。   In the present invention, it is preferable that a wiring layer is not provided on the other surface of the resin substrate. According to this, since there is only one wiring layer, the overall thickness can be further reduced.

本発明においては、前記樹脂基板の厚みは前記コア部よりも前記収容部の方が薄く、これにより前記樹脂基板の前記一方又は他方の表面は、前記収容部において窪んだ形状を有していることが好ましい。これによれば、半導体ＩＣが内蔵された部分において樹脂基板の厚みをより薄くすることが可能となる。   In the present invention, the thickness of the resin substrate is smaller in the housing portion than in the core portion, whereby the one or the other surface of the resin substrate has a recessed shape in the housing portion. It is preferable. According to this, the thickness of the resin substrate can be further reduced in the portion where the semiconductor IC is incorporated.

本発明において、前記半導体ＩＣは、外部端子が設けられた主面と、前記主面とは反対側に位置する裏面とを有し、前記半導体ＩＣの前記主面及び前記裏面の一方の一部分は接着剤で覆われており、残りの部分は前記所定の樹脂で覆われていることが好ましい。或いは、前記半導体ＩＣの前記主面及び前記裏面の一方は、一部分のみが前記所定の樹脂で覆われており、前記半導体ＩＣの前記主面及び前記裏面の他方は、全面が前記所定の樹脂で覆われていることが好ましい。これによれば、半導体ＩＣの上下における熱膨張係数の差が小さくなることから、半導体ＩＣに反りや割れが生じにくくなる。   In the present invention, the semiconductor IC has a main surface provided with an external terminal and a back surface located on the opposite side of the main surface, and one part of the main surface and the back surface of the semiconductor IC is It is preferable that it is covered with an adhesive and the remaining part is covered with the predetermined resin. Alternatively, only one part of the main surface and the back surface of the semiconductor IC is covered with the predetermined resin, and the other of the main surface and the back surface of the semiconductor IC is entirely formed of the predetermined resin. Preferably it is covered. According to this, since the difference in thermal expansion coefficient between the upper and lower sides of the semiconductor IC is reduced, the semiconductor IC is hardly warped or cracked.

この場合、前記半導体ＩＣの前記主面及び前記裏面の他方は、全面が前記所定の樹脂で覆われていることが好ましく、特に、前記半導体ＩＣの側面は、前記接着剤で覆われている部分が存在しないことがより好ましい。これによれば、半導体ＩＣを確実に保護しつつ、半導体ＩＣの反りや割れを防止することが可能となる。また、製造過程において、半導体ＩＣをハンドリングするための実装機のヘッド部分に接着剤が付着することを防止することも可能となる。   In this case, it is preferable that the other of the main surface and the back surface of the semiconductor IC is entirely covered with the predetermined resin, and in particular, the side surface of the semiconductor IC is a portion covered with the adhesive. More preferably, is not present. According to this, it is possible to prevent warping and cracking of the semiconductor IC while reliably protecting the semiconductor IC. It is also possible to prevent the adhesive from adhering to the head portion of the mounting machine for handling the semiconductor IC during the manufacturing process.

本発明による半導体ＩＣ内蔵基板の製造方法は、芯材に未硬化状態の樹脂が含浸されてなり、平面的に見て前記芯材及び前記樹脂に囲まれるようこれらを貫通して設けられた貫通孔を有するプリグレグを用意する第１の工程と、前記貫通孔に半導体ＩＣを収容する第２の工程と、前記プリグレグをプレスすることにより前記樹脂の一部を前記貫通孔に流入させ、これにより前記貫通孔に収容された前記半導体ＩＣを前記流入した樹脂によって埋め込む第３の工程と、を備えることを特徴とする。   In the method for manufacturing a substrate with a built-in semiconductor IC according to the present invention, a core material is impregnated with an uncured resin, and a through-hole provided through the core material and the resin so as to be surrounded in plan view A first step of preparing a prepreg having a hole; a second step of accommodating a semiconductor IC in the through hole; and pressing a part of the prepreg to cause a part of the resin to flow into the through hole, thereby And a third step of embedding the semiconductor IC accommodated in the through hole with the inflowing resin.

本発明によれば、半導体ＩＣの上下に芯材が無い状態で、半導体ＩＣを樹脂によって埋め込んでいることから、半導体ＩＣの上下にコア部が存在しない構造が得られる。しかも、芯材に含浸された樹脂と半導体ＩＣを埋め込む樹脂が同じであることから、熱膨張係数の差などに起因する変形などが生じることもない。   According to the present invention, since the semiconductor IC is embedded with the resin without the core material above and below the semiconductor IC, a structure in which the core portion does not exist above and below the semiconductor IC is obtained. In addition, since the resin impregnated in the core material and the resin that embeds the semiconductor IC are the same, deformation due to a difference in thermal expansion coefficient or the like does not occur.

本発明において前記第２の工程は、キャリア上に前記半導体ＩＣを搭載する工程と、前記貫通孔に前記半導体ＩＣが位置するよう、前記キャリアに前記プリグレグを貼り付ける工程とを含むことが好ましい。これによれば、非常に薄いプリプレグを正しくハンドリングしつつ、プレスを行うことが可能となる。   In the present invention, it is preferable that the second step includes a step of mounting the semiconductor IC on a carrier and a step of attaching the prepreg to the carrier so that the semiconductor IC is positioned in the through hole. According to this, it is possible to perform pressing while correctly handling a very thin prepreg.

前記半導体ＩＣを搭載する工程は、前記キャリアに第１の金属箔を貼り付ける工程と、前記第１の金属箔上に接着剤を塗布する工程と、前記接着剤上に前記半導体ＩＣを搭載することによって前記第１の金属箔に前記半導体ＩＣを接着する工程とを含むことが好ましい。これによれば、キャリアと半導体ＩＣとの間に第１の金属箔が介在することから、キャリアの取り扱いが容易となる。   The step of mounting the semiconductor IC includes a step of attaching a first metal foil to the carrier, a step of applying an adhesive on the first metal foil, and mounting the semiconductor IC on the adhesive. It is preferable to include a step of adhering the semiconductor IC to the first metal foil. According to this, since the first metal foil is interposed between the carrier and the semiconductor IC, the carrier can be easily handled.

前記第３の工程は、前記プリグレグの表面に第２の金属箔を貼り付け、これによって前記貫通孔の上下が前記第１及び第２の金属箔によって覆われた状態でプレスすることにより行うことが好ましい。これによれば、貫通孔に流入する樹脂の表面位置を第１及び第２の金属箔によって正しく規定することが可能となる。   The third step is performed by attaching a second metal foil to the surface of the prepreg, and pressing in a state where the upper and lower sides of the through hole are covered with the first and second metal foils. Is preferred. According to this, it becomes possible to correctly define the surface position of the resin flowing into the through hole by the first and second metal foils.

本発明においては、前記第１の金属箔をパターニングする第４の工程と、前記パターニングされた前記第１の金属箔をマスクとして前記貫通孔に存在する前記樹脂又は前記接着剤にビアを形成することにより、前記半導体ＩＣの外部端子を露出させる第５の工程と、前記露出した外部端子に接続された配線層を形成する第６の工程と、をさらに備えることが好ましい。これによれば、半導体ＩＣをフェースダウンで搭載するとともに、第１の金属箔をマスクとして利用することが可能となる。   In the present invention, a fourth step of patterning the first metal foil, and vias are formed in the resin or the adhesive existing in the through-hole using the patterned first metal foil as a mask. Accordingly, it is preferable to further include a fifth step of exposing the external terminals of the semiconductor IC and a sixth step of forming a wiring layer connected to the exposed external terminals. This makes it possible to mount the semiconductor IC face down and use the first metal foil as a mask.

本発明においては、前記第２の金属箔をパターニングする第４の工程と、前記パターニングされた前記第２の金属箔をマスクとして前記貫通孔に存在する前記樹脂にビアを形成することにより、前記半導体ＩＣの外部端子を露出させる第５の工程と、前記露出した外部端子に接続された配線層を形成する第６の工程と、をさらに備えることもまた好ましい。これによれば、半導体ＩＣをフェースアップで搭載するとともに、第２の金属箔をマスクとして利用することが可能となる。   In the present invention, a fourth step of patterning the second metal foil, and forming a via in the resin existing in the through-hole using the patterned second metal foil as a mask, It is also preferable to further include a fifth step of exposing the external terminals of the semiconductor IC and a sixth step of forming a wiring layer connected to the exposed external terminals. According to this, it is possible to mount the semiconductor IC face up and use the second metal foil as a mask.

前記半導体ＩＣを接着する工程は、前記半導体ＩＣの主面及び裏面の一方の一部分が前記接着剤に接し、残りの部分が接着剤に接しないよう、前記半導体ＩＣを接着することが好ましく、特に、前記半導体ＩＣの側面が前記接着剤に接しないよう、前記半導体ＩＣを接着することがより好ましい。これによれば、半導体ＩＣをハンドリングするための実装機のヘッド部分に接着剤が付着することを防止することが可能となる。   The step of adhering the semiconductor IC preferably includes adhering the semiconductor IC such that one part of the main surface and the back surface of the semiconductor IC is in contact with the adhesive and the remaining part is not in contact with the adhesive. More preferably, the semiconductor IC is bonded so that the side surface of the semiconductor IC does not contact the adhesive. According to this, it becomes possible to prevent the adhesive from adhering to the head portion of the mounting machine for handling the semiconductor IC.

このように、本発明によれば、超薄型の半導体ＩＣ内蔵基板及びその製造方法を提供することが可能となる。   Thus, according to the present invention, it is possible to provide an ultra-thin semiconductor IC-embedded substrate and a method for manufacturing the same.

本発明の好ましい第１の実施形態による半導体ＩＣ内蔵基板１００の外観を示す略斜視図である。1 is a schematic perspective view showing an appearance of a semiconductor IC-embedded substrate 100 according to a preferred first embodiment of the present invention. 図１に示すＡ−Ａ線に沿った断面図である。It is sectional drawing along the AA line shown in FIG. 半導体ＩＣ内蔵基板１００の製造方法を説明するための工程図である。5 is a process diagram for explaining a method of manufacturing the semiconductor IC-embedded substrate 100. FIG. 半導体ＩＣ内蔵基板１００の製造方法を説明するための工程図である。5 is a process diagram for explaining a method of manufacturing the semiconductor IC-embedded substrate 100. FIG. 半導体ＩＣ内蔵基板１００の製造方法を説明するための工程図である。5 is a process diagram for explaining a method of manufacturing the semiconductor IC-embedded substrate 100. FIG. プリプレグ１１１ａの形状を説明するための略斜視図である。It is a schematic perspective view for demonstrating the shape of the prepreg 111a. 本発明の好ましい第２の実施形態による半導体ＩＣ内蔵基板２００の断面図である。It is sectional drawing of the board | substrate 200 with a built-in semiconductor IC by the preferable 2nd Embodiment of this invention. 半導体ＩＣ内蔵基板２００の製造方法を説明するための工程図である。6 is a process diagram for explaining a method of manufacturing the semiconductor IC-embedded substrate 200. FIG. 半導体ＩＣ内蔵基板２００の製造方法を説明するための工程図である。6 is a process diagram for explaining a method of manufacturing the semiconductor IC-embedded substrate 200. FIG. 半導体ＩＣ内蔵基板２００の製造方法を説明するための工程図である。6 is a process diagram for explaining a method of manufacturing the semiconductor IC-embedded substrate 200. FIG. 本発明の好ましい第３の実施形態による半導体ＩＣ内蔵基板３００の断面図である。It is sectional drawing of the board | substrate 300 with a built-in semiconductor IC by the preferable 3rd Embodiment of this invention. 本発明の好ましい第４の実施形態による半導体ＩＣ内蔵基板４００の断面図である。It is sectional drawing of the board | substrate 400 with a built-in semiconductor IC by the preferable 4th Embodiment of this invention.

以下、添付図面を参照しながら、本発明の好ましい実施の形態について詳細に説明する。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明の好ましい第１の実施形態による半導体ＩＣ内蔵基板１００の外観を示す略斜視図である。また、図２は図１に示すＡ−Ａ線に沿った断面図である。   FIG. 1 is a schematic perspective view showing the appearance of a semiconductor IC-embedded substrate 100 according to a preferred first embodiment of the present invention. 2 is a cross-sectional view taken along the line AA shown in FIG.

図１及び図２に示すように、本実施形態による半導体ＩＣ内蔵基板１００は、樹脂基板１１０と、樹脂基板１１０に埋め込まれた半導体ＩＣ１２０とを備えている。樹脂基板１１０の厚さは、９０〜１００μｍ程度と超薄型である。したがって、樹脂基板１１０に埋め込む半導体ＩＣ１２０についても超薄型とする必要があり、例えば４０μｍ程度に薄型化されている。   As shown in FIGS. 1 and 2, the semiconductor IC built-in substrate 100 according to the present embodiment includes a resin substrate 110 and a semiconductor IC 120 embedded in the resin substrate 110. The thickness of the resin substrate 110 is as thin as about 90 to 100 μm. Therefore, the semiconductor IC 120 embedded in the resin substrate 110 also needs to be ultra-thin, and is thinned to about 40 μm, for example.

樹脂基板１１０は、芯材を含むコア部１１１と芯材を含まない収容部１１２とを有している。収容部１１２は、平面的に見てコア部１１１に取り囲まれるよう、コア部１１１を上下に貫通して設けられている。収容部１１２には、コア部１１１に含浸された樹脂と同じ樹脂が充填されており、収容部１１２に充填された樹脂内に半導体ＩＣ１２０が埋め込まれている。換言すれば、同一の樹脂からなる樹脂基板１１０に、平面的に見て芯材が存在する領域と存在しない領域があり、芯材の存在しない領域に半導体ＩＣ１２０が埋め込まれた構造を有している。樹脂基板１１０の厚さは、コア部１１１よりも収容部１１２の方が若干薄く、これにより樹脂基板１１０の表面１１０ａは、収容部１１２においてやや窪んだ形状を有している。このような形状が得られるのは、後述する製造方法に起因する。かかる窪みにより、部分的ではあるものの樹脂基板１１０の厚みはより薄くなる。   The resin substrate 110 includes a core portion 111 including a core material and a housing portion 112 not including the core material. The accommodating part 112 is provided through the core part 111 vertically so as to be surrounded by the core part 111 when seen in a plan view. The housing portion 112 is filled with the same resin as the resin impregnated in the core portion 111, and the semiconductor IC 120 is embedded in the resin filled in the housing portion 112. In other words, the resin substrate 110 made of the same resin has a structure in which the core material is present and a region in which the core material is not present in a plan view, and the semiconductor IC 120 is embedded in a region where the core material does not exist. Yes. The thickness of the resin substrate 110 is slightly smaller in the housing portion 112 than in the core portion 111, whereby the surface 110 a of the resin substrate 110 has a slightly depressed shape in the housing portion 112. Such a shape is obtained due to the manufacturing method described later. Due to such depressions, the thickness of the resin substrate 110 is partially reduced.

コア部１１１及び収容部１１２に用いる樹脂の材料としては、ガラスエポキシ樹脂などの熱硬化性樹脂が用いられる。また、コア部１１１に用いる芯材としては、ガラス繊維、アラミド繊維等の樹脂繊維等を用いることができる。   A thermosetting resin such as a glass epoxy resin is used as a resin material used for the core portion 111 and the housing portion 112. Moreover, as a core material used for the core part 111, resin fibers, such as glass fiber and an aramid fiber, etc. can be used.

半導体ＩＣ１２０は、シリコン（Ｓｉ）やガリウムヒ素化合物（ＧａＡｓ）などからなる半導体基板上に、トランジスタなどの能動素子やキャパシタなどの受動素子が集積された電子デバイスである。製造段階における半導体ＩＣ１２０の厚みは例えば７００μｍ程度であるが、製造工程の最終段階において半導体基板の裏面を研削することによって、４０μｍ程度まで薄型化される。本実施形態による半導体ＩＣ内蔵基板１００は、このように薄型化された半導体ＩＣ１２０を使用する。   The semiconductor IC 120 is an electronic device in which active elements such as transistors and passive elements such as capacitors are integrated on a semiconductor substrate made of silicon (Si), gallium arsenide compound (GaAs), or the like. The thickness of the semiconductor IC 120 in the manufacturing stage is, for example, about 700 μm, but is thinned to about 40 μm by grinding the back surface of the semiconductor substrate in the final stage of the manufacturing process. The semiconductor IC-embedded substrate 100 according to the present embodiment uses the semiconductor IC 120 thus thinned.

半導体ＩＣ１２０の主面には、パッド電極と呼ばれる複数の外部端子１２１が設けられている。外部端子１２１は、樹脂基板１１０の表面１１０ｂに形成された配線層１３０に接続されている。配線層１３０は、外部との電気的な接続部（後述する符号１３１で示す部分）を除いてレジスト膜１４０で覆われている。また、半導体ＩＣ１２０の主面は、接着剤であるダイアタッチペースト１２２によって配線層１３０に接着されている。   A plurality of external terminals 121 called pad electrodes are provided on the main surface of the semiconductor IC 120. The external terminal 121 is connected to the wiring layer 130 formed on the surface 110 b of the resin substrate 110. The wiring layer 130 is covered with a resist film 140 except for an electrical connection portion (a portion denoted by reference numeral 131 described later) with the outside. The main surface of the semiconductor IC 120 is bonded to the wiring layer 130 with a die attach paste 122 that is an adhesive.

本実施形態による半導体ＩＣ内蔵基板１００は、樹脂基板１１０の表面１１０ｂに設けられた１層の配線層１３０のみを有しており、樹脂基板１１０の表面１１０ａには配線層が設けられていない。このため、樹脂基板１１０の表面１１０ａは、全面が外部に露出した状態とされている。   The semiconductor IC-embedded substrate 100 according to the present embodiment has only one wiring layer 130 provided on the surface 110b of the resin substrate 110, and no wiring layer is provided on the surface 110a of the resin substrate 110. For this reason, the entire surface 110a of the resin substrate 110 is exposed to the outside.

以上が本実施形態による半導体ＩＣ内蔵基板１００の構造である。このように、本実施形態による半導体ＩＣ内蔵基板１００は、コア部１１１を貫通して設けられた収容部１１２に半導体ＩＣ１２０が埋め込まれていることから、半導体ＩＣ１２０の上下に芯材が配置されない構造となる。しかも、樹脂基板１１０には、片方の表面１１０ｂにのみ配線層１３０が形成され、もう片方の表面１１０ａには配線層が形成されていないことから、配線層による厚みも最小限に抑えられる。さらに、半導体ＩＣ１２０は、配線層１３０に接着された状態で保持されていることから、半導体ＩＣ１２０を保持するための部材を半導体ＩＣ１２０の上下に配置する必要もない。これらの特徴により、本実施形態による半導体ＩＣ内蔵基板１００は、厚さ９０〜１００μｍ程度の超薄型化を実現している。   The above is the structure of the semiconductor IC-embedded substrate 100 according to the present embodiment. As described above, the semiconductor IC-embedded substrate 100 according to the present embodiment has the structure in which the core material is not disposed above and below the semiconductor IC 120 because the semiconductor IC 120 is embedded in the accommodating portion 112 provided through the core portion 111. It becomes. In addition, since the wiring layer 130 is formed only on one surface 110b and no wiring layer is formed on the other surface 110a, the thickness of the wiring layer can be minimized. Furthermore, since the semiconductor IC 120 is held in a state of being bonded to the wiring layer 130, it is not necessary to arrange members for holding the semiconductor IC 120 above and below the semiconductor IC 120. With these features, the semiconductor IC-embedded substrate 100 according to the present embodiment realizes an ultra-thin thickness of about 90 to 100 μm.

次に、本実施形態による半導体ＩＣ内蔵基板１００の製造方法について説明する。   Next, the method for manufacturing the semiconductor IC-embedded substrate 100 according to the present embodiment will be described.

図３〜図５は、本実施形態による半導体ＩＣ内蔵基板１００の製造方法を説明するための工程図である。   3 to 5 are process diagrams for explaining the method of manufacturing the semiconductor IC-embedded substrate 100 according to the present embodiment.

まず、図３（ａ）に示すように、ステンレスなどの金属材料からなるキャリア１５０を用意し、その表面に接着シート１６０を介して金属箔１７０を貼り付ける。特に限定されるものではないが、金属箔１７０の材料としては銅（Ｃｕ）を用いることが好ましい。次に、図３（ｂ）に示すように、金属箔１７０の表面に未硬化状態のダイアタッチペースト１２２ａを供給し、図３（ｃ）に示すように、位置決めしながらダイアタッチペースト１２２ａ上に半導体ＩＣ１２０を搭載する。特に限定されるものではないが、ダイアタッチペースト１２２ａはフィラーを含まないことが好ましい。これは、ダイアタッチペースト１２２ａに比較的径の大きなフィラーが含まれると、フィラーが半導体ＩＣ１２０と金属箔１７０との間に挟まり、搭載時の圧力によって半導体ＩＣ１２０を破損させてしまうおそれがあるからである。   First, as shown in FIG. 3A, a carrier 150 made of a metal material such as stainless steel is prepared, and a metal foil 170 is attached to the surface of the carrier 150 via an adhesive sheet 160. Although not particularly limited, it is preferable to use copper (Cu) as the material of the metal foil 170. Next, as shown in FIG. 3B, an uncured die attach paste 122a is supplied to the surface of the metal foil 170, and as shown in FIG. 3C, the die attach paste 122a is positioned while being positioned. A semiconductor IC 120 is mounted. Although not particularly limited, the die attach paste 122a preferably contains no filler. This is because if the die attach paste 122a contains a filler having a relatively large diameter, the filler may be sandwiched between the semiconductor IC 120 and the metal foil 170, and the semiconductor IC 120 may be damaged by the pressure during mounting. is there.

半導体ＩＣ１２０の搭載は、外部端子１２１の形成された主面が下側（ダイアタッチペースト１２２ａ側）を向くよう、いわゆるフェースダウン方式で行われる。そして、ダイアタッチペースト１２２ａを熱硬化又は紫外線硬化させることにより、図３（ｄ）に示すように半導体ＩＣ１２０をキャリア１５０に固定する。   The semiconductor IC 120 is mounted by a so-called face-down method so that the main surface on which the external terminals 121 are formed faces downward (the die attach paste 122a side). Then, the die attach paste 122a is heat-cured or ultraviolet-cured to fix the semiconductor IC 120 to the carrier 150 as shown in FIG.

この状態で、図６に示す形状を有するプリプレグ１１１ａをキャリア１５０上に貼り付ける。使用するプリプレグ１１１ａは、芯材に未硬化状態の樹脂が含浸されてなるコア部１１１の前駆体であり、のちに収容部１１２となるべき貫通孔１１２ａが設けられている。貫通孔１１２ａの平面サイズは、半導体ＩＣ１２０の平面サイズよりもやや大きく設定される。そして、図３（ｅ）に示すように、この貫通孔１１２ａに半導体ＩＣ１２０が収容されるよう、プリプレグ１１１ａをキャリア１５０上に貼り付ける。これにより、半導体ＩＣ１２０はその四方がプリプレグ１１１ａに取り囲まれた状態となる。   In this state, the prepreg 111a having the shape shown in FIG. The prepreg 111a to be used is a precursor of the core part 111 in which a core material is impregnated with an uncured resin, and is provided with a through hole 112a to be the accommodating part 112 later. The planar size of the through hole 112a is set slightly larger than the planar size of the semiconductor IC 120. Then, as shown in FIG. 3E, the prepreg 111a is stuck on the carrier 150 so that the semiconductor IC 120 is accommodated in the through hole 112a. As a result, the semiconductor IC 120 is in a state in which its four sides are surrounded by the prepreg 111a.

次に、図４（ａ）に示すように、プリプレグ１１１ａを覆うように金属箔１８０を貼り付ける。特に限定されるものではないが、金属箔１８０の材料としては銅（Ｃｕ）を用いることが好ましい。これにより、半導体ＩＣ１２０が収容された貫通孔１１２ａは、上下が金属箔１７０，１８０で覆われた状態となる。この状態で、プリプレグ１１１ａを上下から熱プレスする。かかる熱プレスの圧力により、図４（ｂ）に示すように、プリプレグ１１１ａに含浸されていた樹脂の一部が貫通孔１１２ａに流入し、流入した樹脂によって貫通孔１１２ａに収容されている半導体ＩＣ１２０が埋め込まれる。そして、熱プレス時の高温により、プリプレグ１１１ａに含浸されていた樹脂及び貫通孔１１２ａに流入した樹脂が熱硬化し、硬化状態のコア部１１１及び収容部１１２が得られる。   Next, as shown to Fig.4 (a), the metal foil 180 is affixed so that the prepreg 111a may be covered. Although not particularly limited, it is preferable to use copper (Cu) as the material of the metal foil 180. Accordingly, the through hole 112a in which the semiconductor IC 120 is accommodated is in a state where the upper and lower sides are covered with the metal foils 170 and 180. In this state, the prepreg 111a is hot pressed from above and below. 4B, a part of the resin impregnated in the prepreg 111a flows into the through hole 112a, and the semiconductor IC 120 accommodated in the through hole 112a by the inflowed resin. Is embedded. The resin impregnated in the prepreg 111a and the resin flowing into the through hole 112a are thermally cured by the high temperature during hot pressing, and the cured core portion 111 and the accommodating portion 112 are obtained.

このような熱プレスを行うと、樹脂の一部が貫通孔１１２ａに流入するため、コア部１１１に存在する樹脂の量はその分減少する。したがって、使用するプリプレグ１１１ａの厚さは、この点を考慮して設定することが好ましい。また、収容部１１２は、プリプレグ１１１ａから流出した樹脂によって構成されるため、その厚さはコア部１１１の厚さよりも若干薄くなる。したがって、プリプレグ１１１ａを構成する芯材及び未硬化状態の樹脂の体積と、貫通孔１１２ａの体積を最適化すれば、コア部１１１より収容部１１２が薄くなり、製品として極限まで薄型化することが可能となる。   When such hot pressing is performed, a part of the resin flows into the through-hole 112a, so that the amount of the resin existing in the core portion 111 is reduced accordingly. Therefore, it is preferable to set the thickness of the prepreg 111a to be used in consideration of this point. Moreover, since the accommodating part 112 is comprised with resin which flowed out from the prepreg 111a, the thickness becomes a little thinner than the thickness of the core part 111. Therefore, by optimizing the volume of the core material and the uncured resin constituting the prepreg 111a and the volume of the through hole 112a, the accommodating portion 112 becomes thinner than the core portion 111, and the product can be made as thin as possible. It becomes possible.

尚、熱プレスにおいては、圧力の印加と高温の印加を同時に行うことは必須でなく、圧力の印加によって樹脂の一部を貫通孔１１２ａに流入させた後、高温の印加によって樹脂を熱硬化させても構わない。或いは、熱硬化性ではない樹脂を用い、プレスによって樹脂の一部を貫通孔１１２ａに流入させた後、紫外線の照射などを行うことによって樹脂を熱硬化させても構わない。また、熱プレス又はプレスは減圧下で行うことが好ましい。これによれば、収容部１１２への気泡の混入を防止することが可能となる。   In the heat press, it is not essential to apply a pressure and a high temperature at the same time. After a part of the resin flows into the through-hole 112a by applying a pressure, the resin is thermally cured by applying a high temperature. It doesn't matter. Alternatively, a non-thermosetting resin may be used, and after a part of the resin is caused to flow into the through hole 112a by pressing, the resin may be thermoset by irradiation with ultraviolet rays or the like. Moreover, it is preferable to perform a hot press or a press under reduced pressure. According to this, it becomes possible to prevent air bubbles from being mixed into the accommodating portion 112.

上記の工程によって樹脂を硬化させた後、図４（ｃ）に示すようにキャリア１５０を剥離する。次に、図４（ｄ）に示すように、金属箔１７０をパターニングすることにより、外部端子１２１の直下に位置する部分の金属箔１７０を除去する。そして、図４（ｅ）に示すように、パターニングされた金属箔１７０をマスクとして、ダイアタッチペースト１２２にビア１９０を形成することにより、外部端子１２１を露出させる。尚、熱プレスによって流入した樹脂が外部端子１２１の直下に位置している場合には、当該樹脂にビア１９０が形成されることになる。   After the resin is cured by the above process, the carrier 150 is peeled off as shown in FIG. Next, as shown in FIG. 4D, by patterning the metal foil 170, the portion of the metal foil 170 located immediately below the external terminal 121 is removed. Then, as shown in FIG. 4E, the external terminals 121 are exposed by forming vias 190 in the die attach paste 122 using the patterned metal foil 170 as a mask. When the resin that has flowed in by the hot press is located directly below the external terminal 121, the via 190 is formed in the resin.

次に、ビア１９０の内部に金属膜を被覆させる無電解メッキと、電解メッキをこの順に行うことにより、図５（ａ）に示すように樹脂基板１１０の表面１１０ｂにメッキ層１３０ａを形成する。そして、図５（ｂ）に示すようにメッキ層１３０ａをパターニングすることにより配線層１３０を形成し、さらに図５（ｃ）に示すように必要に応じて配線層１３０の表面を金（Ａｕ）などの被膜１３０ｂによって表面処理した後、図５（ｄ）に示すようにレジスト膜１４０を形成すれば、本実施形態による半導体ＩＣ内蔵基板１００が完成する。   Next, by performing electroless plating for covering the inside of the via 190 with a metal film and electrolytic plating in this order, a plating layer 130a is formed on the surface 110b of the resin substrate 110 as shown in FIG. Then, the wiring layer 130 is formed by patterning the plating layer 130a as shown in FIG. 5B, and the surface of the wiring layer 130 is made of gold (Au) as required as shown in FIG. 5C. After the surface treatment with the coating 130b, etc., if the resist film 140 is formed as shown in FIG. 5D, the semiconductor IC-embedded substrate 100 according to the present embodiment is completed.

このように、本実施形態による半導体ＩＣ内蔵基板１００の製造方法では、プリプレグ１１１ａに含まれる未硬化状態の樹脂を熱プレスによって貫通孔１１２ａ内に流入させ、これによって半導体ＩＣ１２０を埋め込んでいることから、プリプレグ１１１ａの厚さが非常に薄い場合であっても半導体ＩＣ１２０を正しく樹脂に埋め込むことが可能となる。   As described above, in the method for manufacturing the semiconductor IC-embedded substrate 100 according to the present embodiment, the uncured resin contained in the prepreg 111a is caused to flow into the through-hole 112a by hot pressing, thereby embedding the semiconductor IC 120. Even if the thickness of the prepreg 111a is very thin, the semiconductor IC 120 can be correctly embedded in the resin.

以上、半導体ＩＣ１２０をフェースダウン方式で搭載した場合における構造及び製造方法について説明したが、半導体ＩＣ１２０の搭載方法としてはフェースダウン方式に限らず、フェースアップ方式であっても構わない。以下、半導体ＩＣ１２０をフェースアップ方式で搭載した場合における構造及び製造方法について説明する。   Although the structure and the manufacturing method when the semiconductor IC 120 is mounted by the face-down method have been described above, the mounting method of the semiconductor IC 120 is not limited to the face-down method, and the face-up method may be used. Hereinafter, a structure and a manufacturing method when the semiconductor IC 120 is mounted by the face-up method will be described.

図７は、本発明の好ましい第２の実施形態による半導体ＩＣ内蔵基板２００の断面図である。   FIG. 7 is a cross-sectional view of a semiconductor IC-embedded substrate 200 according to a preferred second embodiment of the present invention.

図７に示すように、本実施形態による半導体ＩＣ内蔵基板２００は、半導体ＩＣ１２０の裏面にダイアタッチペースト１２２が接着されている点において、上述した第１の実施形態による半導体ＩＣ内蔵基板１００と相違している。その他の点については第１の実施形態による半導体ＩＣ内蔵基板１００と基本的に同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。   As shown in FIG. 7, the semiconductor IC-embedded substrate 200 according to the present embodiment is different from the semiconductor IC-embedded substrate 100 according to the first embodiment described above in that the die attach paste 122 is bonded to the back surface of the semiconductor IC 120. doing. Since the other points are basically the same as those of the semiconductor IC-embedded substrate 100 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted.

図８〜図１０は、本実施形態による半導体ＩＣ内蔵基板２００の製造方法を説明するための工程図である。   8 to 10 are process diagrams for explaining the method of manufacturing the semiconductor IC-embedded substrate 200 according to the present embodiment.

まず、図８（ａ）に示すように、キャリア１５０を用意し、その表面に接着シート１６０を介して金属箔１７０を貼り付ける。次に、図８（ｂ）に示すように、金属箔１７０の表面に未硬化状態のダイアタッチペースト１２２ａを供給する。ここまでは、図３（ａ），（ｂ）に示した工程と同じである。その後、本実施形態では、図８（ｃ）に示すように半導体ＩＣ１２０をフェースアップ方式でダイアタッチペースト１２２ａ上に搭載する。フェースアップ方式とは、外部端子１２１の形成された主面が上側（ダイアタッチペースト１２２ａとは反対側）を向くよう搭載する方式である。そして、ダイアタッチペースト１２２ａを硬化させることにより、図８（ｄ）に示すように半導体ＩＣ１２０をキャリア１５０に固定する。   First, as shown in FIG. 8A, a carrier 150 is prepared, and a metal foil 170 is attached to the surface of the carrier 150 via an adhesive sheet 160. Next, as shown in FIG. 8B, an uncured die attach paste 122 a is supplied to the surface of the metal foil 170. Up to this point, the process is the same as that shown in FIGS. Thereafter, in the present embodiment, as shown in FIG. 8C, the semiconductor IC 120 is mounted on the die attach paste 122a by the face-up method. The face-up method is a method of mounting so that the main surface on which the external terminals 121 are formed faces upward (the side opposite to the die attach paste 122a). Then, the die attach paste 122a is cured to fix the semiconductor IC 120 to the carrier 150 as shown in FIG.

その後の工程は第１の実施形態とほぼ同様であり、貫通孔１１２ａに半導体ＩＣ１２０が収容されるよう、プリプレグ１１１ａをキャリア１５０上に貼り付けた後（図８（ｅ））、プリプレグ１１１ａを覆う金属箔１８０を貼り付け（図９（ａ））、この状態でプリプレグ１１１ａを上下から熱プレスする（図９（ｂ））。これにより、プリプレグ１１１ａに含浸されていた樹脂の一部が貫通孔１１２ａに流入し、流入した樹脂によって貫通孔１１２ａに収容されている半導体ＩＣ１２０が埋め込まれる。   Subsequent processes are almost the same as those in the first embodiment, and after the prepreg 111a is pasted on the carrier 150 so that the semiconductor IC 120 is accommodated in the through hole 112a (FIG. 8E), the prepreg 111a is covered. A metal foil 180 is attached (FIG. 9A), and the prepreg 111a is hot-pressed from above and below in this state (FIG. 9B). Thereby, a part of the resin impregnated in the prepreg 111a flows into the through hole 112a, and the semiconductor IC 120 accommodated in the through hole 112a is embedded by the inflowed resin.

以上の工程が完了した後は、どの段階でキャリア１５０を剥離しても構わないが、本実施形態ではキャリア１５０が設けられた側の表面１１０ｂに配線層１３０が設けられないため、以上の工程が完了した後、任意の段階でキャリア１５０を剥離することが可能である。以下、最終工程の直前までキャリア１５０を剥離しないまま工程を進めた場合を例に説明する。   After the above steps are completed, the carrier 150 may be peeled off at any stage. However, in this embodiment, the wiring layer 130 is not provided on the surface 110b on the side where the carrier 150 is provided. After the process is completed, the carrier 150 can be peeled at an arbitrary stage. Hereinafter, a case where the process is performed without peeling off the carrier 150 until just before the final process will be described as an example.

上記の工程によって樹脂を硬化させた後、金属箔１８０をパターニングし（図９（ｃ））、パターニングされた金属箔１８０をマスクとして、収容部１１２を構成する樹脂にビア１９０を形成する（図９（ｄ））。次に、樹脂基板１１０の表面１１０ａにメッキ層１３０ａを形成した後（図９（ｅ））、メッキ層１３０ａをパターニングすることにより配線層１３０を形成し（図１０（ａ））、さらに必要に応じて配線層１３０の表面を被膜１３０ｂによって表面処理した後（図１０（ｂ））、レジスト膜１４０を形成する（図１０（ｃ））。   After the resin is cured by the above process, the metal foil 180 is patterned (FIG. 9C), and the via 190 is formed in the resin constituting the housing portion 112 using the patterned metal foil 180 as a mask (FIG. 9). 9 (d)). Next, after forming the plating layer 130a on the surface 110a of the resin substrate 110 (FIG. 9E), the wiring layer 130 is formed by patterning the plating layer 130a (FIG. 10A), and further necessary. Accordingly, after the surface of the wiring layer 130 is surface-treated with the coating 130b (FIG. 10B), a resist film 140 is formed (FIG. 10C).

そして、キャリア１５０から樹脂基板１１０を剥離し（図１０（ｄ））、エッチングによって金属箔１７０を除去すれば（図１０（ｅ））、本実施形態による半導体ＩＣ内蔵基板２００が完成する。尚、図１０（ａ）〜（ｅ）の工程をこの順に行うことは必須でなく、例えば、樹脂基板１１０の剥離（図１０（ｄ））、メッキ層１３０ａのパターニング（図１０（ａ））、金属箔１７０の除去（図１０（ｅ））、レジスト膜１４０の形成（図１０（ｃ））、配線層１３０の表面処理（図１０（ｂ））の順で工程を行うことも可能である。   Then, if the resin substrate 110 is peeled from the carrier 150 (FIG. 10D) and the metal foil 170 is removed by etching (FIG. 10E), the semiconductor IC built-in substrate 200 according to the present embodiment is completed. Note that it is not essential to perform the steps of FIGS. 10A to 10E in this order. For example, the resin substrate 110 is peeled (FIG. 10D), and the plating layer 130a is patterned (FIG. 10A). It is also possible to perform the steps in the order of removal of the metal foil 170 (FIG. 10E), formation of the resist film 140 (FIG. 10C), and surface treatment of the wiring layer 130 (FIG. 10B). is there.

以上により、半導体ＩＣ１２０がフェースアップ方式で搭載された半導体ＩＣ内蔵基板２００が作製される。本実施形態による半導体ＩＣ内蔵基板２００は、第１の実施形態による半導体ＩＣ内蔵基板１００とほぼ同様の効果を得ることが可能である。   Thus, the semiconductor IC built-in substrate 200 on which the semiconductor IC 120 is mounted in a face-up manner is manufactured. The semiconductor IC-embedded substrate 200 according to the present embodiment can obtain substantially the same effect as the semiconductor IC-embedded substrate 100 according to the first embodiment.

図１１は、本発明の好ましい第３の実施形態による半導体ＩＣ内蔵基板３００の断面図である。   FIG. 11 is a cross-sectional view of a semiconductor IC-embedded substrate 300 according to a preferred third embodiment of the present invention.

図１１に示すように、本実施形態による半導体ＩＣ内蔵基板３００は、半導体ＩＣ１２０の主面１２０ａの一部分にのみダイアタッチペースト１２２が接着され、残りの部分は収容部１１２に充填された樹脂によって覆われている点において、上述した第１の実施形態による半導体ＩＣ内蔵基板１００と相違している。その他の点については第１の実施形態による半導体ＩＣ内蔵基板１００と基本的に同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。尚、半導体ＩＣ１２０の裏面１２０ｂについては、収容部１１２に充填された樹脂によってその全面が覆われている。半導体ＩＣ１２０の側面１２０ｃについても、収容部１１２に充填された樹脂によってその全面が覆われていることが好ましい。かかる構成により、半導体ＩＣ１２０の上下における熱膨張係数の差が小さくなることから、半導体ＩＣ１２０に反りや割れが生じにくくなる。   As shown in FIG. 11, in the semiconductor IC-embedded substrate 300 according to the present embodiment, the die attach paste 122 is adhered only to a part of the main surface 120a of the semiconductor IC 120, and the remaining part is covered with a resin filled in the housing portion 112. This is different from the semiconductor IC-embedded substrate 100 according to the first embodiment described above. Since the other points are basically the same as those of the semiconductor IC-embedded substrate 100 according to the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. The entire back surface 120b of the semiconductor IC 120 is covered with the resin filled in the housing portion 112. The entire side surface 120c of the semiconductor IC 120 is preferably covered with the resin filled in the housing portion 112. With such a configuration, the difference in thermal expansion coefficient between the upper and lower sides of the semiconductor IC 120 is reduced, so that the semiconductor IC 120 is less likely to be warped or cracked.

このような構成を得るためには、図３（ｂ）に示した工程において未硬化状態のダイアタッチペースト１２２ａの塗布面積を小さくし、これにより、図３（ｃ）に示した工程において半導体ＩＣ１２０の主面１２０ａの一部のみがダイアタッチペースト１２２ａに接し、残りの部分が接しないよう、半導体ＩＣ１２０を接着すればよい。半導体ＩＣ１２０の側面１２０ｃについてもダイアタッチペースト１２２ａが接しないよう、半導体ＩＣ１２０を接着することが好ましい。これによれば、ダイアタッチペースト１２２ａが半導体ＩＣ１２０の裏面１２０ｂに回り込むことがないことから、半導体ＩＣ１２０をハンドリングするための実装機のヘッド部分にダイアタッチペースト１２２ａが付着することがない。   In order to obtain such a configuration, the application area of the uncured die attach paste 122a is reduced in the process shown in FIG. 3B, and thus the semiconductor IC 120 is obtained in the process shown in FIG. The semiconductor IC 120 may be bonded so that only a part of the main surface 120a is in contact with the die attach paste 122a and the remaining part is not in contact. It is preferable to adhere the semiconductor IC 120 so that the die attach paste 122a does not contact the side surface 120c of the semiconductor IC 120 as well. According to this, since the die attach paste 122a does not wrap around the back surface 120b of the semiconductor IC 120, the die attach paste 122a does not adhere to the head portion of the mounting machine for handling the semiconductor IC 120.

図１２は、本発明の好ましい第４の実施形態による半導体ＩＣ内蔵基板４００の断面図である。   FIG. 12 is a cross-sectional view of a semiconductor IC-embedded substrate 400 according to a preferred fourth embodiment of the present invention.

図１２に示すように、本実施形態による半導体ＩＣ内蔵基板４００は、半導体ＩＣ１２０の裏面１２０ｂの一部分にのみダイアタッチペースト１２２が接着され、残りの部分は収容部１１２に充填された樹脂によって覆われている点において、上述した第２の実施形態による半導体ＩＣ内蔵基板２００と相違している。その他の点については第２の実施形態による半導体ＩＣ内蔵基板２００と基本的に同一であることから、同一の要素には同一の符号を付し、重複する説明は省略する。尚、半導体ＩＣ１２０の主面１２０ａについては、外部端子１２１が設けられている部分を除き、収容部１１２に充填された樹脂によってその全面が覆われている。半導体ＩＣ１２０の側面１２０ｃについても、収容部１１２に充填された樹脂によってその全面が覆われていることが好ましい。かかる構成により、上述した第３の実施形態と同じ効果を得ることが可能となる。   As shown in FIG. 12, in the semiconductor IC-embedded substrate 400 according to the present embodiment, the die attach paste 122 is bonded only to a part of the back surface 120b of the semiconductor IC 120, and the remaining part is covered with the resin filled in the housing part 112. In this respect, the semiconductor IC-embedded substrate 200 according to the second embodiment described above is different. Since the other points are basically the same as those of the semiconductor IC-embedded substrate 200 according to the second embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. The main surface 120a of the semiconductor IC 120 is entirely covered with the resin filled in the housing portion 112 except for the portion where the external terminals 121 are provided. The entire side surface 120c of the semiconductor IC 120 is preferably covered with the resin filled in the housing portion 112. With this configuration, the same effects as those of the third embodiment described above can be obtained.

このような構成を得るためには、図８（ｂ）に示した工程において未硬化状態のダイアタッチペースト１２２ａの塗布面積を小さくし、これにより、図８（ｃ）に示した工程において半導体ＩＣ１２０の裏面１２０ｂの一部のみがダイアタッチペースト１２２ａに接し、残りの部分が接しないよう、半導体ＩＣ１２０を接着すればよい。半導体ＩＣ１２０の側面１２０ｃについてもダイアタッチペースト１２２ａが接しないよう、半導体ＩＣ１２０を接着することが好ましい。その効果については、上述した第３の実施形態と同様である。   In order to obtain such a configuration, the application area of the uncured die attach paste 122a is reduced in the step shown in FIG. 8B, and thus the semiconductor IC 120 in the step shown in FIG. 8C. The semiconductor IC 120 may be bonded so that only a part of the back surface 120b of the substrate is in contact with the die attach paste 122a and the remaining part is not in contact. It is preferable to adhere the semiconductor IC 120 so that the die attach paste 122a does not contact the side surface 120c of the semiconductor IC 120 as well. About the effect, it is the same as that of 3rd Embodiment mentioned above.

以上、本発明の好ましい実施形態について説明したが、本発明は、上記の実施形態に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。   The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

例えば、上記実施形態では、樹脂基板１１０に１個の半導体ＩＣ１２０を内蔵しているが、内蔵する半導体ＩＣの数についてはこれに限定されず、２個以上であっても構わない。２個以上の半導体ＩＣを内蔵する場合、これら２個以上の半導体ＩＣを同一の樹脂層内に埋め込んでも構わないし、異なる樹脂層内にそれぞれ埋め込んでも構わない。異なる樹脂層内に半導体ＩＣをそれぞれ埋め込む場合、図３（ｂ）〜図５（ｂ）の工程を繰り返せばよい。   For example, in the above embodiment, one semiconductor IC 120 is built in the resin substrate 110, but the number of built-in semiconductor ICs is not limited to this and may be two or more. When two or more semiconductor ICs are built in, these two or more semiconductor ICs may be embedded in the same resin layer or in different resin layers. When embedding semiconductor ICs in different resin layers, the steps of FIGS. 3B to 5B may be repeated.

１００，２００，３００，４００ 半導体ＩＣ内蔵基板
１１０ 樹脂基板
１１０ａ，１１０ｂ 表面
１１１ コア部
１１１ａ プリプレグ
１１２ 収容部
１１２ａ 貫通孔
１２０ 半導体ＩＣ
１２０ａ 半導体ＩＣの主面
１２０ｂ 半導体ＩＣの裏面
１２０ｃ 半導体ＩＣの側面
１２１ 外部端子
１２２，１２２ａ ダイアタッチペースト
１３０ 配線層
１３０ａ メッキ層
１３０ｂ 被膜
１３１ 接続部
１４０ レジスト膜
１５０ キャリア
１６０ 接着シート
１７０，１８０ 金属箔
１９０ ビア 100, 200, 300, 400 Semiconductor IC built-in substrate 110 Resin substrates 110a, 110b Surface 111 Core portion 111a Pre-preg 112 Housing portion 112a Through hole 120 Semiconductor IC
120a Main surface 120b of semiconductor IC 120b Back surface 120c of semiconductor IC Side surface 121 of semiconductor IC External terminal 122, 122a Die attach paste 130 Wiring layer 130a Plating layer 130b Film 131 Connection part 140 Resist film 150 Carrier 160 Adhesive sheet 170, 180 Metal foil 190 Beer

Claims (16)

樹脂基板と、前記樹脂基板に埋め込まれた半導体ＩＣとを備え、
前記樹脂基板は、芯材に所定の樹脂が含浸されてなるコア部と、平面的に見て前記コア部に囲まれるよう前記コア部を貫通して設けられた収容部とを含み、
前記半導体ＩＣは、前記収容部に充填された前記所定の樹脂に埋め込まれていることを特徴とする半導体ＩＣ内蔵基板。 A resin substrate; and a semiconductor IC embedded in the resin substrate,
The resin substrate includes a core part in which a core material is impregnated with a predetermined resin, and an accommodating part provided through the core part so as to be surrounded by the core part when seen in a plan view,
The semiconductor IC-embedded substrate, wherein the semiconductor IC is embedded in the predetermined resin filled in the housing portion. 前記樹脂基板の一方の表面に形成され、前記半導体ＩＣの外部端子に接続された配線層と、前記配線層を覆うレジスト膜とをさらに備えることを特徴とする請求項１に記載の半導体ＩＣ内蔵基板。   The semiconductor IC built-in according to claim 1, further comprising: a wiring layer formed on one surface of the resin substrate and connected to an external terminal of the semiconductor IC; and a resist film covering the wiring layer. substrate. 前記樹脂基板の他方の表面には配線層が設けられていないことを特徴とする請求項２に記載の半導体ＩＣ内蔵基板。   3. The semiconductor IC-embedded substrate according to claim 2, wherein a wiring layer is not provided on the other surface of the resin substrate. 前記樹脂基板の厚みは前記コア部よりも前記収容部の方が薄く、これにより前記樹脂基板の前記一方又は他方の表面は、前記収容部において窪んだ形状を有していることを特徴とする請求項３に記載の半導体ＩＣ内蔵基板。   The thickness of the resin substrate is smaller in the housing portion than in the core portion, whereby the one or the other surface of the resin substrate has a recessed shape in the housing portion. The semiconductor IC built-in substrate according to claim 3. 前記半導体ＩＣは、外部端子が設けられた主面と、前記主面とは反対側に位置する裏面とを有し、
前記半導体ＩＣの前記主面及び前記裏面の一方の一部分は接着剤で覆われており、残りの部分は前記所定の樹脂で覆われていることを特徴とする請求項１乃至４のいずれか一項に記載の半導体ＩＣ内蔵基板。 The semiconductor IC has a main surface provided with external terminals and a back surface located on the opposite side of the main surface,
5. A part of one of the main surface and the back surface of the semiconductor IC is covered with an adhesive, and the remaining part is covered with the predetermined resin. The semiconductor IC built-in substrate according to the item. 前記半導体ＩＣの前記主面及び前記裏面の他方は、全面が前記所定の樹脂で覆われていることを特徴とする請求項５に記載の半導体ＩＣ内蔵基板。   6. The semiconductor IC-embedded substrate according to claim 5, wherein the other of the main surface and the back surface of the semiconductor IC is entirely covered with the predetermined resin. 前記半導体ＩＣの側面は、前記接着剤で覆われている部分が存在しないことを特徴とする請求項５又は６に記載の半導体ＩＣ内蔵基板。   7. The semiconductor IC-embedded substrate according to claim 5, wherein a side surface of the semiconductor IC does not have a portion covered with the adhesive. 前記半導体ＩＣは、外部端子が設けられた主面と、前記主面とは反対側に位置する裏面とを有し、
前記半導体ＩＣの前記主面及び前記裏面の一方は、一部分のみが前記所定の樹脂で覆われており、
前記半導体ＩＣの前記主面及び前記裏面の他方は、全面が前記所定の樹脂で覆われていることを特徴とする請求項１乃至４のいずれか一項に記載の半導体ＩＣ内蔵基板。 The semiconductor IC has a main surface provided with external terminals and a back surface located on the opposite side of the main surface,
Only one part of the main surface and the back surface of the semiconductor IC is covered with the predetermined resin,
5. The semiconductor IC-embedded substrate according to claim 1, wherein the other of the main surface and the back surface of the semiconductor IC is entirely covered with the predetermined resin. 6. 芯材に未硬化状態の樹脂が含浸されてなり、平面的に見て前記芯材及び前記樹脂に囲まれるようこれらを貫通して設けられた貫通孔を有するプリグレグを用意する第１の工程と、
前記貫通孔に半導体ＩＣを収容する第２の工程と、
前記プリグレグをプレスすることにより前記樹脂の一部を前記貫通孔に流入させ、これにより前記貫通孔に収容された前記半導体ＩＣを前記流入した樹脂によって埋め込む第３の工程と、を備えることを特徴とする半導体ＩＣ内蔵基板の製造方法。 A first step of preparing a prepreg having a through hole provided through a core material impregnated with an uncured resin and being surrounded by the core material and the resin in plan view; ,
A second step of accommodating a semiconductor IC in the through hole;
And pressing the prepreg to cause a part of the resin to flow into the through hole, thereby filling the semiconductor IC accommodated in the through hole with the flowed resin. A method for manufacturing a substrate with a built-in semiconductor IC. 前記第２の工程は、キャリア上に前記半導体ＩＣを搭載する工程と、前記貫通孔に前記半導体ＩＣが位置するよう、前記キャリアに前記プリグレグを貼り付ける工程とを含むことを特徴とする請求項９に記載の半導体ＩＣ内蔵基板の製造方法。   The second step includes a step of mounting the semiconductor IC on a carrier, and a step of attaching the prepreg to the carrier so that the semiconductor IC is positioned in the through hole. 10. A method for producing a semiconductor IC-embedded substrate according to 9. 前記半導体ＩＣを搭載する工程は、前記キャリアに第１の金属箔を貼り付ける工程と、前記第１の金属箔上に接着剤を塗布する工程と、前記接着剤上に前記半導体ＩＣを搭載することによって前記第１の金属箔に前記半導体ＩＣを接着する工程とを含むことを特徴とする請求項１０に記載の半導体ＩＣ内蔵基板の製造方法。   The step of mounting the semiconductor IC includes a step of attaching a first metal foil to the carrier, a step of applying an adhesive on the first metal foil, and mounting the semiconductor IC on the adhesive. The method for manufacturing a substrate with a built-in semiconductor IC according to claim 10, further comprising: adhering the semiconductor IC to the first metal foil. 前記第３の工程は、前記プリグレグの表面に第２の金属箔を貼り付け、これによって前記貫通孔の上下が前記第１及び第２の金属箔によって覆われた状態でプレスすることにより行うことを特徴とする請求項１１に記載の半導体ＩＣ内蔵基板の製造方法。   The third step is performed by attaching a second metal foil to the surface of the prepreg, and pressing in a state where the upper and lower sides of the through hole are covered with the first and second metal foils. The method for manufacturing a substrate with a built-in semiconductor IC according to claim 11. 前記第１の金属箔をパターニングする第４の工程と、
前記パターニングされた前記第１の金属箔をマスクとして前記貫通孔に存在する前記樹脂又は前記接着剤にビアを形成することにより、前記半導体ＩＣの外部端子を露出させる第５の工程と、
前記露出した外部端子に接続された配線層を形成する第６の工程と、をさらに備えることを特徴とする請求項１１又は１２に記載の半導体ＩＣ内蔵基板の製造方法。 A fourth step of patterning the first metal foil;
A fifth step of exposing an external terminal of the semiconductor IC by forming a via in the resin or the adhesive existing in the through hole using the patterned first metal foil as a mask;
The method for manufacturing a substrate with a built-in semiconductor IC according to claim 11, further comprising a sixth step of forming a wiring layer connected to the exposed external terminal. 前記第２の金属箔をパターニングする第４の工程と、
前記パターニングされた前記第２の金属箔をマスクとして前記貫通孔に存在する前記樹脂にビアを形成することにより、前記半導体ＩＣの外部端子を露出させる第５の工程と、
前記露出した外部端子に接続された配線層を形成する第６の工程と、をさらに備えることを特徴とする請求項１２に記載の半導体ＩＣ内蔵基板の製造方法。 A fourth step of patterning the second metal foil;
A fifth step of exposing an external terminal of the semiconductor IC by forming a via in the resin existing in the through-hole using the patterned second metal foil as a mask;
The method of manufacturing a substrate with a built-in semiconductor IC according to claim 12, further comprising a sixth step of forming a wiring layer connected to the exposed external terminal. 前記半導体ＩＣを接着する工程は、前記半導体ＩＣの主面及び裏面の一方の一部分が前記接着剤に接し、残りの部分が接着剤に接しないよう、前記半導体ＩＣを接着することを特徴とする請求項１１乃至１４のいずれか一項に記載の半導体ＩＣ内蔵基板の製造方法。   The step of bonding the semiconductor IC is characterized in that the semiconductor IC is bonded so that one part of the main surface and the back surface of the semiconductor IC is in contact with the adhesive and the remaining part is not in contact with the adhesive. The method for manufacturing a substrate with a built-in semiconductor IC according to claim 11. 前記半導体ＩＣを接着する工程は、前記半導体ＩＣの側面が前記接着剤に接しないよう、前記半導体ＩＣを接着することを特徴とする請求項１５に記載の半導体ＩＣ内蔵基板の製造方法。   The method of manufacturing a substrate with a built-in semiconductor IC according to claim 15, wherein in the step of bonding the semiconductor IC, the semiconductor IC is bonded so that a side surface of the semiconductor IC does not contact the adhesive.
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