JP5609617B2 - Electronic component, method for manufacturing the electronic component, electronic device, and method for manufacturing the electronic device - Google Patents
Electronic component, method for manufacturing the electronic component, electronic device, and method for manufacturing the electronic device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 238000000034 method Methods 0.000 title description 32
- 229920005989 resin Polymers 0.000 claims description 112
- 239000011347 resin Substances 0.000 claims description 112
- 239000000463 material Substances 0.000 claims description 103
- 230000015572 biosynthetic process Effects 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 description 80
- 239000000758 substrate Substances 0.000 description 45
- 238000000465 moulding Methods 0.000 description 17
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000002950 deficient Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本発明は、電子部品、その電子部品の製造方法、電子機器およびその電子機器の製造方法に関する。 The present invention relates to an electronic component, a method for manufacturing the electronic component, an electronic device, and a method for manufacturing the electronic device.
携帯用電子機器などの小型・軽量化、高機能化の要求に対し、搭載するＩＣの高集積化、微細化を図り、さらに、複数のＩＣ機能をワンチップ（システムＬＳＩ）化する方法が用いられている。しかし、この方法は、大規模ＬＳＩ化に伴う歩留低下などから、低コストで製造することは容易ではない。 In response to demands for miniaturization, weight reduction, and high functionality of portable electronic devices, etc., a method of increasing the integration and miniaturization of the mounted IC and further making a plurality of IC functions into one chip (system LSI) is used. It has been. However, this method is not easy to manufacture at a low cost due to a decrease in yield due to the large-scale LSI.
他のアプローチとして、複数の半導体チップを同一基板上に搭載してワンパッケージとする、ＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌｅ）化の方法も行われている。ＭＣＭは、多層配線基板に複数の半導体チップを配置するが、搭載半導体チップの接続端子ピッチが狭くなるに従って配線基板の製造歩留が低下し、基板製造コストが全体のコストアップの重要なファクターとなる。また、半導体チップと配線基板との接続を、バンプやワイヤーボンディング、タブなどで行うが、確保できる接続領域の制限や端子の微細化への製造限界などから、接続端子数に制限がある。当然ながら、平面視面積は搭載半導体チップの平面視面積より大きくなってしまい、ＭＣＭ化によっての面積縮小の効果は必ずしも高くない。更に、信号伝達速度の低下などの全体性能の低下を伴うといった課題がある。 As another approach, an MCM (Multi Chip Module) method in which a plurality of semiconductor chips are mounted on the same substrate to form a single package is also performed. MCM arranges a plurality of semiconductor chips on a multilayer wiring board. However, as the connection terminal pitch of the mounted semiconductor chip becomes narrower, the manufacturing yield of the wiring board decreases, and the board manufacturing cost is an important factor for increasing the overall cost. Become. In addition, the connection between the semiconductor chip and the wiring board is performed by bumps, wire bonding, tabs, and the like, but the number of connection terminals is limited due to the limitation of the connection area that can be secured and the manufacturing limit for the miniaturization of the terminals. Naturally, the area in plan view becomes larger than the area in plan view of the mounted semiconductor chip, and the effect of area reduction by the MCM is not necessarily high. In addition, there is a problem that it is accompanied by a decrease in overall performance such as a decrease in signal transmission speed.
これらの短所を補う観点から幾つかの提案がなされている。例えば、予め複数の良品の半導体チップを選択し、これを先ず、半導体チップの回路形成面（＝電極形成面）側を中間板上の所定の位置にそれぞれ貼付し、この中間板を用いて貼付半導体チップ全体を、一度に、支持基板（Ｓｉ基板など）上に形成した絶縁膜（ポリイミド膜など）上に貼付し、中間板を取り除いた後、さらに半導体チップ上からポリイミド液を滴下して半導体チップ間を埋めて貼付状態を強化するといった方法が提案されている。この、いわば、支持基板上チップ貼付形成方法では、その後、支持基板上に貼付された、回路形成面が表面に出ている半導体チップ上の余分な貼付用絶縁膜を除去後、半導体プロセスを用いて半導体チップ間接続用の配線を形成する。 Several proposals have been made to compensate for these disadvantages. For example, a plurality of non-defective semiconductor chips are selected in advance, and first, the circuit forming surface (= electrode forming surface) side of the semiconductor chip is pasted at a predetermined position on the intermediate plate, and then pasted using this intermediate plate. The entire semiconductor chip is affixed onto an insulating film (polyimide film, etc.) formed on a support substrate (Si substrate, etc.) at once, and after removing the intermediate plate, a polyimide solution is further dropped from above the semiconductor chip. A method has been proposed in which the space between chips is filled to enhance the state of attachment. In other words, in this method for forming a chip on a support substrate, a semiconductor process is used after removing an excessive insulating film for affixing on a semiconductor chip that is affixed on a support substrate and has a circuit forming surface on the surface. Then, wiring for connecting the semiconductor chips is formed.
一方、「擬似ウエハ」を形成する方法も提案されている。複数の良品半導体チップなどの組み合わせた電子部品セットを、半導体チップの回路形成面（＝電極形成面）側を、透明基板（石英基板など）上の粘着シート上の所定の位置にそれぞれ貼付する。そのとき、多数の同一の電子部品セットを、所定の間隔を空けて、半導体ウエハにチップが整列形成されるように、粘着シート上に整列貼付する。 On the other hand, a method of forming a “pseudo wafer” has also been proposed. A set of electronic components such as a plurality of non-defective semiconductor chips is attached to a predetermined position on an adhesive sheet on a transparent substrate (such as a quartz substrate) on the circuit forming surface (= electrode forming surface) side of the semiconductor chip. At that time, a large number of identical electronic component sets are aligned and pasted on the adhesive sheet so that the chips are aligned and formed on the semiconductor wafer at a predetermined interval.
そして、それら整列貼付された電子部品セット群の全体上に絶縁性の樹脂を流し込んで、回路形成面以外の半導体チップの周辺部と裏面部と樹脂で固化し一体化させることで、複数の良品半導体チップからなる電子部品セット群が固化樹脂上に固定され、複数のチップがＳｉウエハ中に形成されたものと類似した、複数の電子部品セットからなるチップが樹脂からなるウエハ中に作製された「擬似ウエハ」が形成される。 A plurality of non-defective products can be obtained by pouring an insulating resin over the entire set of electronic components that have been aligned and pasted, and solidifying and integrating the peripheral and back surfaces of the semiconductor chip other than the circuit forming surface with the resin. An electronic component set group consisting of semiconductor chips was fixed on a solidified resin, and a chip consisting of a plurality of electronic component sets was made in a resin wafer, similar to the case where a plurality of chips were formed in a Si wafer. A “pseudo wafer” is formed.
この「擬似ウエハ」形成方法では、その後、粘着シートの粘着力を弱めて透明基板から「擬似ウエハ」を剥離し、これの、回路面上に配線形成などを行って複数の良品半導体チップなどを組み合わせた電子部品セットとし、さらに電子部品セット毎にダイシングし、個別のチップ状電子部品として完成する。 In this “pseudo-wafer” formation method, the adhesive force of the adhesive sheet is then weakened and the “pseudo-wafer” is peeled off from the transparent substrate, and wiring is formed on the circuit surface to obtain a plurality of non-defective semiconductor chips. A combined electronic component set is further diced for each electronic component set to complete individual chip-shaped electronic components.
上記の二方法は、いずれも不良チップの排除を事前の行うことができ、この面での歩留は向上される上に、形成された半導体チップ組み合わせモジュール上で、各半導体チップの回路形成面が同一平面内に保持されているため、その面上で上部多層配線の形成とチップ間接続がスムーズに行うことができる。従って、これらの方法では、通常のＭＣＭで行われるチップ搭載の多層配線基板経由での半導体チップ間の接続を避けることができ、配線基板自体の高精細化などによる製造歩留低下などを考慮する必要が無い、といったメリットも有している。 Both of the above two methods can eliminate defective chips in advance, and the yield on this surface is improved, and the circuit formation surface of each semiconductor chip is formed on the formed semiconductor chip combination module. Are held in the same plane, it is possible to smoothly form the upper multilayer wiring and connect the chips on the surface. Therefore, in these methods, it is possible to avoid the connection between semiconductor chips via a chip-mounted multilayer wiring board, which is performed in a normal MCM, and to take into account the manufacturing yield reduction due to high definition of the wiring board itself, etc. It also has the advantage that it is not necessary.
しかし、前述二方法に関し、前者の支持基板上チップ貼付形成方法では、支持基板上の絶縁膜（ポリイミド膜など）にチップを一括貼付する方法であるため、形成された半導体チップ組み合わせモジュールの支持基板厚みが厚くなること、貼付用絶縁膜がチップ表面に付着するため、この付着物の除去によるチップ表面の劣化が避け得ないこと、といった課題がある。 However, with respect to the above-mentioned two methods, the former method of chip pasting on a support substrate is a method of pasting chips onto an insulating film (polyimide film, etc.) on a support substrate, so that the support substrate of the formed semiconductor chip combination module There are problems that the thickness is increased, and that the insulating film for sticking adheres to the chip surface, so that the deterioration of the chip surface due to the removal of the adhering matter cannot be avoided.
他方、「擬似ウエハ」形成方法は、半導体チップなどの電子部品の回路形成（＝電極形成）面以外を樹脂で覆って「擬似ウエハ」を作製するため、回路形成面は基本的に大きな汚染を受けないこと、ダイシングされて個別化したチップ状電子部品は軽量で薄い樹脂基板上形成されていること、またチップ状電子部品に搭載された複数の半導体チップの電極形成面は同一面上にあるため、これら電極上へのバンプ形成などが一括形成可能であること、といった利点も有している。 On the other hand, in the “pseudo wafer” formation method, the “pseudo wafer” is manufactured by covering the surface other than the circuit formation (= electrode formation) surface of an electronic component such as a semiconductor chip with resin. The chip-shaped electronic component that is diced and individualized is formed on a lightweight and thin resin substrate, and the electrode forming surfaces of a plurality of semiconductor chips mounted on the chip-shaped electronic component are on the same surface. Therefore, there is an advantage that bumps can be formed on these electrodes at once.
しかし、この「擬似ウエハ」形成方法によって形成されたチップ状電子部品の構造は、片方の面側に半導体チップなどが配列され、他方の面を含む基板側が樹脂で形成される。このため、半導体チップなどと樹脂の線膨張係数に大きな差がある場合、樹脂による「擬似ウエハ」の形成に伴う蓄積熱、および「擬似ウエハ」形成後や個別のチップ状電子部品の配線加工などの加熱に対する内部応力などが生じる結果、でき上がった擬似ウエハ、および個別のチップ状電子部品において、半導体チップなどの搭載側が凹に反りが発生しやすい。このため、配線形成時などでの微細加工プロセスで、大幅な歩留低下を招くといった問題が生じる。 However, in the structure of the chip-like electronic component formed by this “pseudo-wafer” forming method, semiconductor chips and the like are arranged on one surface side, and the substrate side including the other surface is formed of resin. For this reason, when there is a large difference in the linear expansion coefficient between the semiconductor chip and the resin, the accumulated heat associated with the formation of the “pseudo wafer” with the resin, and the wiring processing of individual chip-like electronic components after the formation of the “pseudo wafer” As a result of the occurrence of internal stress or the like due to the heating, the mounting side of the semiconductor chip or the like is likely to warp in the concave in the completed pseudo wafer and individual chip-like electronic components. For this reason, there arises a problem that the yield is drastically reduced in a fine processing process at the time of wiring formation.
そこで本発明の課題は、このような反りの発生を大幅に抑制した、基板側が絶縁性の樹脂（＝半導体チップなどの保護材）で、その材料で半導体チップなどの側面及び裏面が覆われた、チップ状などの電子部品を提供することにある。 Therefore, the object of the present invention is to significantly suppress the occurrence of such warpage, and the substrate side is an insulating resin (= protective material such as a semiconductor chip), and the side and back surfaces of the semiconductor chip and the like are covered with the material. It is to provide electronic parts such as chips.
本発明の電子部品は、
電極が形成された電極形成面を有する複数の電子部品と、
前記電極形成面を露出するように前記複数の電子部品が埋め込まれ、一体形成された絶縁樹脂材と、
前記複数の電子部品の裏面側に配置され、前記絶縁樹脂材中に形成された複数の溝とを有することを特徴とする。
また、本発明の電子部品の製造方法は、
載置台上に、電極が形成された電極形成面を有する複数の電子部品を、前記電極形成面に絶縁樹脂材が接しないように、互いに離間して配置し固定する工程と、
前記載置台上において、前記絶縁樹脂材によって、前記複数の電子部品の側面及び裏面を覆って一体化し、かつ前記裏面に複数の溝を有するように絶縁樹脂材成型体を形成する工程と、
前記絶縁樹脂材成型体を前記載置台から分離する工程と
を含むことを特徴とする。
また、本発明の電子機器は、
電極が形成された電極形成面を有する複数の電子部品と、
前記電極形成面を露出するように前記複数の電子部品が埋め込まれ、一体形成された絶縁樹脂材と、
前記複数の電子部品の裏面側に配置され、前記絶縁樹脂材中に形成された複数の溝とを有することを特徴とする。
また、本発明の電子機器の製造方法は、
載置台上に、電極が形成された電極形成面を有する複数の電子部品を、前記電極形成面に絶縁樹脂材が接しないように、互いに離間して配置し固定する工程と、
前記載置台上において、前記絶縁樹脂材によって、前記複数の電子部品の側面及び裏面を覆って一体化し、かつ前記裏面に複数の溝を有するように絶縁樹脂材成型体を形成する工程と、
前記絶縁樹脂材成型体を前記載置台から分離する工程と
を含むことを特徴とする。
The electronic component of the present invention is
A plurality of electronic components having an electrode forming surface on which electrodes are formed;
Insulating resin material in which the plurality of electronic components are embedded and integrally formed so as to expose the electrode formation surface;
It is arranged on the back side of the plurality of electronic components, and has a plurality of grooves formed in the insulating resin material.
In addition, the method of manufacturing the electronic component of the present invention includes
Arranging and fixing a plurality of electronic components having an electrode forming surface on which electrodes are formed on a mounting table so as not to contact the insulating resin material on the electrode forming surface; and
On the mounting table, with the insulating resin material, covering and integrating the side surfaces and back surfaces of the plurality of electronic components, and forming an insulating resin material molded body so as to have a plurality of grooves on the back surface;
Separating the insulating resin material molded body from the mounting table.
The electronic device of the present invention is
A plurality of electronic components having an electrode forming surface on which electrodes are formed;
Insulating resin material in which the plurality of electronic components are embedded and integrally formed so as to expose the electrode formation surface;
It is arranged on the back side of the plurality of electronic components, and has a plurality of grooves formed in the insulating resin material.
In addition, the method for manufacturing the electronic device of the present invention includes:
Arranging and fixing a plurality of electronic components having an electrode forming surface on which electrodes are formed on a mounting table so as not to contact the insulating resin material on the electrode forming surface; and
On the mounting table, with the insulating resin material, covering and integrating the side surfaces and back surfaces of the plurality of electronic components, and forming an insulating resin material molded body so as to have a plurality of grooves on the back surface;
Separating the insulating resin material molded body from the mounting table.
本発明の、多くの溝を有する絶縁性の樹脂材成型体を形成し、一括配線形成を行った後、ダイシングして得られるチップ状などの電子部品や電子機器の製造方法は、樹脂材成型体の反りが大きく抑制されているために、多層で微細なチップ間の配線などをモールド基板面上の一括処理で、高い歩留で行うことが可能である。 According to the present invention, an insulating resin material molded body having many grooves is formed, and after batch wiring is formed, a chip-like electronic component or electronic device manufacturing method obtained by dicing is resin material molding. Since the warpage of the body is greatly suppressed, it is possible to carry out a multi-layered and fine wiring between chips at a high yield by batch processing on the mold substrate surface.
そして、樹脂材成型体の形成を経由して製造され、薄く軽量な（樹脂）基板上に多様多種な半導体チップなどの電子部品を、高密度多層配線を用いて、高歩留で高集積に一体デバイス化するといった本発明のチップ状などの電子部品や電子機器は、従来のワンチップシステムＬＳＩや従来の電子機器に比べ高歩留が期待でき、また従来のＭＣＭなどに比べ、とくに高集積化、配線工程での高歩留化などが可能となる。 And it is manufactured through the formation of resin material moldings, and a wide variety of electronic components such as semiconductor chips on a thin and lightweight (resin) substrate can be integrated with high yield and high density. Electronic components and electronic devices such as chip-shaped devices of the present invention that are integrated into devices can be expected to have a higher yield than conventional one-chip system LSIs and conventional electronic devices, and are particularly highly integrated compared to conventional MCMs and the like. And higher yield in the wiring process.
以下に、本発明の実施の形態を、添付図を参照しつつ説明する。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
（実施例）
図１〜７の（１）〜（１０）に示した各図は、本発明の電子部品の製造工程を説明するための断面模式図である。
(Example)
Each of the drawings shown in (1) to (10) of FIGS. 1 to 7 is a schematic cross-sectional view for explaining the manufacturing process of the electronic component of the present invention.
図１において、電子部品を作製するための、載置台およびその周辺の構成を示す。図１（１）（ａ）はその構成の上面図、また図中Ａ−Ｂ間の断面図を、図１（１）（ｂ）に示す。図において、載置台１は載置台ホルダ２上にセットされる。この載置台１は、下部側からの図示しないUV光に対して透明で、線膨張係数が小さく熱プロセスによる変形の小さい、例えば、石英基板、ガラス基板、セラミック基板などを適用できる。載置台１の表面には、UV粘着シート３を貼付し、いわゆる「疑似ウエハ」形成後にUVを照射することにより、「疑似ウエハ」の剥離を容易にする。 In FIG. 1, the structure of the mounting base and its periphery for producing an electronic component is shown. FIGS. 1A and 1A are top views of the structure, and a cross-sectional view taken along a line AB in FIGS. 1A and 1B. In the figure, the mounting table 1 is set on a mounting table holder 2. The mounting table 1 is transparent to UV light (not shown) from the lower side, and has a small linear expansion coefficient and small deformation due to a thermal process, for example, a quartz substrate, a glass substrate, a ceramic substrate, or the like. A UV adhesive sheet 3 is affixed to the surface of the mounting table 1, and UV irradiation is performed after forming a so-called “pseudo wafer” to facilitate peeling of the “pseudo wafer”.
また、載置台１上に、その外周部を囲むように、樹脂材型枠４を配する。これにより、後述の樹脂材によるモールド成型工法を適用する時において、樹脂材が載置台１の外縁に漏れるのを防ぐ。樹脂材型枠４の形状は、載置台１の形状が、例えば、オリエンテーション・フラット付の円形のウエハ形状であればそれに沿った型枠とし、矩形であるならば、適宜それに合わせて矩形型枠とする。 In addition, a resin material mold 4 is arranged on the mounting table 1 so as to surround the outer periphery thereof. This prevents the resin material from leaking to the outer edge of the mounting table 1 when a molding method using a resin material described later is applied. For example, if the shape of the mounting table 1 is, for example, a circular wafer shape with an orientation flat, the shape of the resin material mold 4 is a mold frame along the shape. And
図２（２）は、載置台１上に半導体チップなどの複数の電子部品を搭載する状況を示す図である。図２（２）（ａ）において、ベアチップの半導体チップ５を、その電極形成面（＝回路形成側の面）６を下に、裏面７を上にし、図示しない、例えば光学的な測定システムと、半導体チップ５および載置台ホルダ２の駆動システムを用いて所定位置へのアライメントを行って、所定の間隔で所定の位置の載置し、載置台１上のUV粘着シート３に固定する。その状況を、図２（２）（ｂ）に示す。このとき、図示するように、各半導体チップ５の電極形成面６は載置台１に面して、その反対側の各半導体チップ５の裏面７および側面８は接しない。 FIG. 2 (2) is a diagram showing a situation where a plurality of electronic components such as semiconductor chips are mounted on the mounting table 1. 2 (a) and 2 (a), a bare chip semiconductor chip 5 has an electrode formation surface (= surface on the circuit formation side) 6 down and a back surface 7 up, for example, an optical measurement system not shown. Then, alignment to a predetermined position is performed using a drive system for the semiconductor chip 5 and the mounting table holder 2, mounting at a predetermined position at a predetermined interval, and fixing to the UV adhesive sheet 3 on the mounting table 1. The situation is shown in FIGS. 2 (2) and 2 (b). At this time, as shown in the drawing, the electrode forming surface 6 of each semiconductor chip 5 faces the mounting table 1, and the back surface 7 and the side surface 8 of each semiconductor chip 5 on the opposite side do not contact each other.
図３（３）に示すように、樹脂材型枠４内に、全ての半導体チップ５を覆うように樹脂材９を導入する。この樹脂材９は、半導体素子５を覆うため絶縁性を有する、熱硬化性の樹脂（シリカフィラー含有エポキシ）が好ましい。例えばアクリル系の樹脂やエポキシ樹脂などの有機系絶縁性樹脂が挙げられる。 As shown in FIG. 3 (3), a resin material 9 is introduced into the resin material mold 4 so as to cover all the semiconductor chips 5. The resin material 9 is preferably a thermosetting resin (silica filler-containing epoxy) having insulation to cover the semiconductor element 5. Examples thereof include organic insulating resins such as acrylic resins and epoxy resins.
次いで、図３（４）に示すように、樹脂材９上に、予め搭載される半導体チップ５の配置や樹脂材９の厚さを考慮して設計された突出構造１０を有する裏面形成用金型１１を樹脂材９中に送出する。 Next, as shown in FIG. 3 (4), a back surface forming gold having a protruding structure 10 designed on the resin material 9 in consideration of the arrangement of the semiconductor chips 5 mounted in advance and the thickness of the resin material 9. The mold 11 is sent into the resin material 9.
図４（５）に示すように、載置台ホルダ２上の樹脂材型枠４で停止するまで裏面形成用金型１１を送出して固定し、この状態で、半導体チップ５とともに樹脂材９を加熱・加圧などして成型する。金型系全体の空気冷却後、図４（６）に示すように、裏面形成用金型１１よび樹脂材型枠４を取り外すことにより、載置台１に配置固定した全半導体チップ５が、その裏面７および側面８において、樹脂材９からなる上記裏面形成用金型１１の突出構造１０を反映した樹脂材成型支持板１２と固定一体化した状態で、載置台１上に形成されることとなる。 As shown in FIG. 4 (5), the back surface forming mold 11 is sent and fixed until it stops at the resin material mold 4 on the mounting table holder 2, and in this state, the resin material 9 is attached together with the semiconductor chip 5. Molded by heating and pressing. After air cooling of the entire mold system, as shown in FIG. 4 (6), all the semiconductor chips 5 arranged and fixed on the mounting table 1 are removed by removing the back surface forming mold 11 and the resin material mold 4. The back surface 7 and the side surface 8 are formed on the mounting table 1 in a state of being fixed and integrated with the resin material molding support plate 12 reflecting the protruding structure 10 of the back surface forming mold 11 made of the resin material 9; Become.
次に、図５（７）に示すように、載置台１の粘着シート３を介して固着している半導体チップ５を、シートにUV光を照射してその粘着性を解消して半導体チップ５（及び樹脂材９）を粘着シート３から分離して、樹脂材成型支持板１２と多数の半導体チップ５とが一体化した絶縁性の樹脂を用いた樹脂材成型体１３を分離形成する。なお、本発明の説明においては、半導体ウエハ表面全体に多数のベアチップが配置形成された状態の半導体基板との類似から、上記のようにモールド成型工法によって製作可能なことから、この樹脂材成型体１３を、本明細書においては、モールド基板１３とも称する。またこれは、先に述べた、「擬似ウエハ」と、材料構成において類似する。 Next, as shown in FIG. 5 (7), the semiconductor chip 5 fixed through the adhesive sheet 3 of the mounting table 1 is irradiated with UV light to eliminate the adhesiveness of the semiconductor chip 5. (And the resin material 9) are separated from the pressure-sensitive adhesive sheet 3, and a resin material molded body 13 using an insulating resin in which the resin material molding support plate 12 and a large number of semiconductor chips 5 are integrated is formed separately. In the description of the present invention, this resin material molded body can be manufactured by the molding method as described above because it is similar to the semiconductor substrate in which a large number of bare chips are arranged and formed on the entire surface of the semiconductor wafer. 13 is also referred to as a mold substrate 13 in this specification. This is similar to the “pseudo-wafer” described above in terms of material structure.
このモールド基板（樹脂材成型体）１３の半導体チップ５の表面側は、電極が形成された回路形成面である。また各半導体チップ５の表面はモールド基板１３において同一平面上にある。従って、半導体ウエハ上に形成されたベアチップの電極を用いてチップ間配線を行うのと同様な配線製造方法を適用できる。モールド基板１３においては、多くの場合、搭載された半導体チップ間を配線接続して、複数の半導体チップを有する一つのチップ状などの電子部品を構成する。 The surface side of the semiconductor chip 5 of the mold substrate (resin material molded body) 13 is a circuit forming surface on which electrodes are formed. The surface of each semiconductor chip 5 is on the same plane in the mold substrate 13. Therefore, a wiring manufacturing method similar to that for performing inter-chip wiring using bare chip electrodes formed on a semiconductor wafer can be applied. In the mold substrate 13, in many cases, electronic components such as one chip having a plurality of semiconductor chips are configured by wiring connection between mounted semiconductor chips.
図５（８）（ａ）は多数の（そして各種の）半導体チップ５がモールド基板１３上に形成された状況を示し、この一部の、この場合は、隣り合う２つの（異なる）半導体チップの領域で、単一電子部品領域１４を形成するものとする。（８）（ｂ）は、その単一電子部品領域１４の拡大断面模式図である。各半導体チップ５の表面には、埋め込み形成された回路から導出されている個所に、例えば、所定の大きさのアルミ（Ａｌ）電極１５が形成され、半導体チップ５の表面は電極の開口部を除いて、パッシベーション膜１６で覆われている。 5 (8) (a) shows a situation in which a large number (and various types) of semiconductor chips 5 are formed on the mold substrate 13, and a part of this, in this case, two adjacent (different) semiconductor chips. The single electronic component region 14 is formed in the region. (8) and (b) are enlarged cross-sectional schematic diagrams of the single electronic component region. On the surface of each semiconductor chip 5, for example, an aluminum (Al) electrode 15 having a predetermined size is formed at a position derived from the embedded circuit, and the surface of the semiconductor chip 5 has an electrode opening. Except for this, it is covered with a passivation film 16.
図６（９）は、（２つの半導体チップ５からなる）単一電子部品領域において、配線形成された後の、配線形成単一電子部品領域１７の例の断面模式図を示す。図において、アルミ電極１５及びパッシベーション膜１６上に、更に多層に形成するパッシベーション膜１８と金属配線のパターニング形成により、一方半導体チップ５のアルミ電極１５からの配線を他方の半導体チップ５のアルミ電極１５とを接続するチップ間配線１９や、パッシベーション膜１８の面上に電極を引き出す引き出しパッド２０などが、従来から標準的に行われる多層配線形成技術を用いて形成される。このようにして配線形成されたモールド基板１３を、半導体基板をチップ単位にダイシングするように、配線形成単一電子部品領域１７毎にダイシングして、個別の電子部品を形成する。 FIG. 6 (9) shows a schematic cross-sectional view of an example of the wiring-forming single electronic component region 17 after the wiring is formed in the single electronic component region (comprising two semiconductor chips 5). In the figure, the wiring from the aluminum electrode 15 of one semiconductor chip 5 is connected to the aluminum electrode 15 of the other semiconductor chip 5 by patterning the passivation film 18 and metal wiring formed in multiple layers on the aluminum electrode 15 and the passivation film 16. The inter-chip wiring 19 that connects the two and the lead-out pad 20 that draws an electrode on the surface of the passivation film 18 are formed using a multilayer wiring forming technique that is conventionally performed as a standard. The mold substrate 13 thus formed with wiring is diced for each wiring formation single electronic component region 17 so that the semiconductor substrate is diced in units of chips to form individual electronic components.
図７（１０）（ａ）は、配線済みのモールド基板１３を単一電子部品単位にダイシングした状態に断面模式図であり、（１０）（ｂ）は、個別となった、本発明の電子部品２１の断面模式図を示す。 FIGS. 7 (10) and 7 (a) are cross-sectional schematic views in a state where the wired mold substrate 13 is diced into single electronic component units, and FIGS. 7 (b) and 10 (b) are individual views of the electronic of the present invention. The cross-sectional schematic diagram of the component 21 is shown.
図７（１０）（ｂ）に示した、本実施例の電子部品２１は、樹脂材で形成した樹脂材成型支持板１２の部分に関し、裏面の全面に、溝２２を形成している。この例では、溝の深さは半導体チップ５の背面まで達し、半導体チップ５のチップ間隔の裏面側のチップ間隔樹脂材２３の部分も溝２２が形成されている。 In the electronic component 21 of this embodiment shown in FIGS. 7 (10) and 7 (b), a groove 22 is formed on the entire back surface of the resin material molded support plate 12 formed of a resin material. In this example, the depth of the groove reaches the back surface of the semiconductor chip 5, and the groove 22 is also formed in the portion of the chip interval resin material 23 on the back side of the chip interval of the semiconductor chip 5.
図８は、同様に製作され、但し樹脂材成型支持板１２に溝を形成しない、溝無し電子部品２４の断面模式図である。こうした構造の電子部品では、図示するように、半導体チップ５形成側に圧縮ストレスＳが働いて、その面を凹にして、反り量△Ｓが発生しており、この反り量△Ｓは、樹脂材成型支持板１２の厚さＴに依存する。こうしたチップ状電子部品のモールド基板（図７（１０）のモールド基板１３において、溝２２が形成されない形状の基板）を一括配線したとき、配線歩留まりが大きく低下している。 FIG. 8 is a schematic cross-sectional view of the non-grooved electronic component 24 manufactured in the same manner but without forming grooves in the resin material support plate 12. In the electronic component having such a structure, as shown in the figure, a compressive stress S acts on the side where the semiconductor chip 5 is formed, and the surface thereof is recessed to generate a warp amount ΔS. It depends on the thickness T of the material molding support plate 12. When such a chip-shaped electronic component mold substrate (a substrate in which the groove 22 is not formed in the mold substrate 13 of FIG. 7 (10)) is collectively wired, the wiring yield is greatly reduced.
図９は、配線前の、モールド基板（樹脂材成型体）における、反り量と樹脂材成型支持板厚の関係の実験結果を示す。本図において、縦軸は、配線前のモールド基板の反り量を示し、横軸は、樹脂材成型支持板の厚さを示す。使用したモールド基板の構造は、直径１５０ｍｍの円盤状をしており、これに、１０ｍｍ（長）×５ｍｍ（幅）×（０．５ｍｍ、０．４ｍｍ、０．３ｍｍ）（厚）の半導体チップ（同一種類）を７個×１８個、配列しているものを用いた。また、樹脂材としては、シリカフィラー含有エポキシ樹脂を用いた。 FIG. 9 shows the experimental results of the relationship between the amount of warpage and the thickness of the resin material molding support plate in the mold substrate (resin material molding) before wiring. In this figure, the vertical axis represents the amount of warpage of the mold substrate before wiring, and the horizontal axis represents the thickness of the resin material molding support plate. The structure of the mold substrate used is a disk shape having a diameter of 150 mm, and a semiconductor chip of 10 mm (length) × 5 mm (width) × (0.5 mm, 0.4 mm, 0.3 mm) (thickness) 7 (18) of the same type were used. As the resin material, a silica filler-containing epoxy resin was used.
図中、折れ線で示したものは、モールド基板の樹脂材成型支持板が溝無しで、厚さが０．１ｍｍ、０．２ｍｍ、０．３ｍｍの場合を示す。但し、同じく、配線形成前である。これらの場合、反り量が、２ｍｍ〜４ｍｍ程度と大きな反りが発生することがわかる。一方、図中、溝ありで示した測定点は、同じ構成・材料を用い、モールド成型支持板の厚さは０．２５ｍｍ、そこに溝を上記の実施例と同様な型で溝を形成する方法によった、溝形状は円柱形で溝の直径２．５ｍｍ、隣接する円柱中心間距離３．０ｍｍで、溝の深さはチップ裏面に達する深さ（０．３mm）として樹脂材成型支持板全面に一様に分布したものによる測定点である。同様に配線形成前である。このとき、反り量は０．２ｍｍないしそれ以下でモールド基板に殆ど歪みは発生せず、この溝の導入の効果が顕著に見られる。 In the figure, what is indicated by a broken line indicates a case where the resin material molding support plate of the mold substrate has no groove and the thickness is 0.1 mm, 0.2 mm, or 0.3 mm. However, it is also before wiring formation. In these cases, it can be seen that a large amount of warpage occurs in the amount of warpage of about 2 mm to 4 mm. On the other hand, the measurement points shown with a groove in the figure use the same structure and material, the thickness of the molding support plate is 0.25 mm, and the groove is formed in the same mold as the above embodiment. According to the method, the groove shape is cylindrical, the groove diameter is 2.5 mm, the distance between adjacent cylinder centers is 3.0 mm, and the groove depth is the depth to reach the back of the chip (0.3 mm). The measurement points are distributed uniformly over the entire surface of the plate. Similarly, before wiring formation. At this time, the warping amount is 0.2 mm or less, and the mold substrate is hardly distorted, and the effect of introducing the groove is noticeable.
溝の導入は、モールド基板の裏面側（樹脂材成型支持板側）の樹脂材の全体量を減らし、表裏での熱線膨張係数の差による表面側の圧縮ストレス量を大きく減少させる効果をもたらしているものと考えることができる。従って、この溝の体積を、モールド基板の強度を損なわせない範囲で効果的の減少させることが重要である。 The introduction of the groove has the effect of reducing the total amount of resin material on the back side (resin material molding support plate side) of the mold substrate and greatly reducing the amount of compressive stress on the surface side due to the difference in the coefficient of thermal expansion between the front and back sides. Can be considered. Therefore, it is important to effectively reduce the volume of the groove as long as the strength of the mold substrate is not impaired.
このように、樹脂材成型支持板に多くの溝を有するモールド基板（樹脂材成型体）を形成し、一括配線形成を行った後、ダイシングして得られる本発明の電子部品の製造方法は、モールド基板の反りが大きく抑制されているために、多層で微細なチップ間の配線などをモールド基板面上の一括処理で、高い歩留で行うことが可能であり、勿論、ダイシングされたチップ状などの電子部品単体にも反りが殆ど無い。 Thus, after forming a mold substrate (resin material molded body) having many grooves on a resin material molding support plate and performing collective wiring formation, the manufacturing method of the electronic component of the present invention obtained by dicing is as follows. Since the warpage of the mold substrate is greatly suppressed, it is possible to perform wiring between multi-layered and minute chips at a high yield by batch processing on the mold substrate surface, and of course, a diced chip shape There is almost no warpage in a single electronic component.
そして、モールド基板形成を経由して製造され、薄く軽量な（樹脂）基板上に多様多種な半導体チップなどの電子部品を、高密度多層配線を用いて、高歩留で高集積に一体デバイス化するといった本発明の電子部品は、従来のワンチップシステムＬＳＩに比べ高歩留が期待でき、また従来のＭＣＭに比べ、とくに高集積化、配線工程での高歩留化などが可能と考えられる。 And it is manufactured through mold substrate formation, and various electronic parts such as various semiconductor chips are made into a single device with high yield and high integration on a thin and lightweight (resin) substrate using high-density multilayer wiring. The electronic component according to the present invention can be expected to have a higher yield than the conventional one-chip system LSI, and can be particularly highly integrated and have a higher yield in the wiring process than the conventional MCM. .
上記実施例で述べた、本発明の電子部品の構成、及びその製造方法は一例に過ぎず、本発明の趣旨に沿った他の構成や製造方法があることは言うまでもない。 The configuration of the electronic component of the present invention and the manufacturing method thereof described in the above embodiment are merely examples, and it goes without saying that there are other configurations and manufacturing methods in accordance with the spirit of the present invention.
図１０は、他の電子部品例（１）２５の断面模式図である。図１０において、この電子部品では、樹脂材成型支持板１２部分において、溝２２は半導体チップ５の裏面部分のみ形成され、チップ間隔樹脂材２３の領域には形成されていない。この構成は、図７（１０）（ｂ）の電子部品２１に比べ、樹脂材の絶対量は多く、そのため熱線膨張係数ギャップ緩和作用は劣るが、反面、隣接する半導体チップ５の間の接続強度はより強化されており、溝２２の多数形成によるチップ状などのこの電子部品自体の物理的強度の低下、特に半導体チップ間の強度劣化を防ぐ有力な方法である。 FIG. 10 is a schematic cross-sectional view of another electronic component example (1) 25. 10, in this electronic component, in the resin material molding support plate 12 portion, the groove 22 is formed only in the back surface portion of the semiconductor chip 5 and is not formed in the region of the chip interval resin material 23. In this configuration, the absolute amount of the resin material is larger than that of the electronic component 21 shown in FIGS. 7 (10) and 7 (b). Therefore, the thermal linear expansion coefficient gap relaxation action is inferior, but on the other hand, the connection strength between the adjacent semiconductor chips 5. This is an effective method for preventing a decrease in physical strength of the electronic component itself such as a chip shape due to the formation of a large number of grooves 22, especially a deterioration in strength between semiconductor chips.
図１１に、他の電子部品例（２）２６の断面模式図を示す。図において、この電子部品では、樹脂材成型支持板１２部分において、溝２２は裏面全体に一様に形成されているが、その深さは、半導体チップ５の裏面部分に達していない。この構成も、図７（１０）（ｂ）の電子部品２１に比べ、樹脂材の絶対量は多く、そのため熱線膨張係数ギャップ緩和作用は劣るが、溝２２の多数形成による電子部品自体の全体的な物理的強度の低下を防ぐ効果がある。勿論、この変形として、溝２２は半導体チップ５の裏面部分のみ形成され、チップ間隔樹脂材２３の領域には形成されない構成もあろう。 FIG. 11 is a schematic cross-sectional view of another electronic component example (2) 26. In the figure, in this electronic component, the groove 22 is uniformly formed on the entire back surface of the resin material support plate 12, but the depth does not reach the back surface of the semiconductor chip 5. This configuration also has a larger absolute amount of resin material than the electronic component 21 shown in FIGS. 7 (10) and 7 (b). Therefore, the thermal linear expansion coefficient gap relaxation action is inferior, but the entire electronic component itself is formed by forming a large number of grooves 22. There is an effect of preventing a decrease in physical strength. Of course, as a modification, the groove 22 may be formed only in the back surface portion of the semiconductor chip 5 and not in the region of the chip interval resin material 23.
図１２に、本発明の他の電子部品例（３）２７の断面模式図を示す。図において、この電子部品では、半導体チップ５−１と半導体チップ５−２の厚さが異なり（勿論、両者の電極形成面の水平面は一致）、溝２２の深さは厚い半導体チップ５−１の裏面に達し、同じ深さの溝２２は、薄い半導体チップ５−２の裏面に達していない。チップ間隔樹脂材２３の領域には形成されていない。勿論、溝２２の深さを変えて、両方の半導体チップ５−１、−２の裏面に達する構成にすれば、樹脂材の絶対量はより少なくなって、歪みの抑制効果が増大する一方、物理的強度の劣化は避けられない。チップ間隔樹脂材２３の領域に溝を形成するバリエーションも考えられる。 FIG. 12 is a schematic cross-sectional view of another electronic component example (3) 27 of the present invention. In this figure, in this electronic component, the thickness of the semiconductor chip 5-1 and the semiconductor chip 5-2 are different (of course, the horizontal surfaces of the electrode forming surfaces of both are the same), and the depth of the groove 22 is thick. The groove 22 having the same depth does not reach the back surface of the thin semiconductor chip 5-2. It is not formed in the region of the chip interval resin material 23. Of course, if the depth of the groove 22 is changed to reach the back surfaces of both the semiconductor chips 5-1, -2, the absolute amount of the resin material becomes smaller, and the distortion suppressing effect increases. Degradation of physical strength is inevitable. Variations in which grooves are formed in the region of the chip interval resin material 23 are also conceivable.
上記の実施例においては、搭載されるチップ部品に関し、半導体チップを用いた場合について述べた。半導体チップに関し、ベアチップである必要は無く、モールドパッケージ、セラミックパッケージなどのパッケージ化された半導体製品でも、チップ製品（部品）と見做されハンドリングできるものであるなら、上記実施例において採用可能である。さらに、半導体チップ製品に限らず、抵抗・容量素子などチップ状パッケージされたものも適用する事ができ、半導体チップと述べたものは、一般にチップ形状などの電子部品全般を適用できる。 In the above embodiment, the case where a semiconductor chip is used has been described regarding the chip components to be mounted. The semiconductor chip does not have to be a bare chip, and a packaged semiconductor product such as a mold package or a ceramic package can be adopted in the above embodiment as long as it can be regarded as a chip product (component) and can be handled. . Furthermore, not only semiconductor chip products but also chip-shaped packages such as resistance / capacitance elements can be applied. In general, electronic components such as chip shapes can be applied to semiconductor chips.
本発明で適用される溝の形状に関し、実施例で述べたような円柱状に限る必要は無い。例えば、三角や四角、多角形格子、さらに円筒状を組み合わせた格子などの枠内の角柱・円柱が溝となるもの、逆にそれら枠自体が溝をなすもの、またそのサイズ、溝密度なども適宜設計可能である。また、絶縁樹脂材の厚さについても、樹脂材料自体の反り発生に関わる特性、搭載電子部品のサイズ、数、配置状況、製作電子部品の大きさなどをもとに、許容反りを考慮して適宜決定することができる。 The shape of the groove applied in the present invention need not be limited to the cylindrical shape as described in the embodiments. For example, a prism or cylinder in a frame such as a triangular, square, polygonal lattice, or a combination of cylindrical shapes becomes a groove, conversely, the frame itself forms a groove, and its size, groove density, etc. It can be designed as appropriate. In addition, with regard to the thickness of the insulating resin material, considering the allowable warpage based on the characteristics related to the occurrence of warpage of the resin material itself, the size, number, arrangement status, size of the manufactured electronic components, etc. It can be determined as appropriate.
本発明のモールド基板の製造方法は、上記実施例においては、載置台上に半導体チップをフェイスダウンに位置合わせして配置し、金型を用いた樹脂モールド工法により、チップの裏面・側面で一度に一体化する方法を述べたが、採りうる製造工程はこれに限らない。例えば、チップ間は載置台上で主に側面を用いて絶縁樹脂材により一体化して「チップ一体化板」を形成し、他方、「裏面貼付用絶縁樹脂材板」を用いて、これにエンボス工法などで所要の溝を形成し、これと前記「チップ一体化板」を熱や接着用絶縁樹脂材などにより、接合することでも形成できるなど、他の方法も適用可能である。 In the above embodiment, the mold substrate manufacturing method of the present invention is arranged by placing the semiconductor chip face-down on the mounting table, and once by the resin mold method using a mold on the back and side surfaces of the chip. However, the manufacturing process that can be adopted is not limited to this. For example, the chip is integrated with an insulating resin material mainly on the side surface on the mounting table to form a “chip integrated plate”, and on the other hand, an “insulating resin material plate for affixing the back surface” is used to emboss it. Other methods are also applicable, such as forming a required groove by a construction method, etc., and bonding the chip and the “chip integrated plate” with heat or an insulating resin material for bonding.
これまでの記述においては、完成する製品は、例えば、チップ形状などを含む電子部品とし、また電子部品の製造方法としてきた。しかし、上記と同様な形態で、これに搭載されるものが半導体等チップ形状部品に限らず、各種部品が集積・システム化されたパッケージ（状部品）等を複数種・複数個搭載して特定の機器機能をもったものを完成させたとき、完成した製品は電子機器を形成することとなる。即ち、本発明の形態によって電子機器をなすことができ、また本発明の同等の方法で、電子機器を製造することができることは言うまでもない。 In the description so far, the finished product is, for example, an electronic component including a chip shape and the like, and has been a manufacturing method of the electronic component. However, in the same form as above, what is mounted on this is not limited to chip-shaped components such as semiconductors, but is specified by mounting multiple types and multiple packages (shaped components) in which various components are integrated and systematized. When the product having the device function is completed, the completed product forms an electronic device. That is, it is needless to say that an electronic device can be made according to the embodiment of the present invention, and the electronic device can be manufactured by an equivalent method of the present invention.
以上の実施例を含む実施の形態に関し、以下の付記を開示する。
（付記１）
電極が形成された電極形成面を有する複数の電子部品と、
前記電極形成面を露出するように前記複数の電子部品が埋め込まれ、一体形成された絶縁樹脂材と、
前記複数の電子部品の裏面側に配置され、前記絶縁樹脂材中に形成された複数の溝とを有することを特徴とする電子部品。
（付記２）
前記電子部品によって画定される領域にのみ、前記複数の溝は形成されることを特徴とする付記１記載の電子部品。
（付記３）
前記複数の溝の少なくとも一部は、前記複数の電子部品の裏面に達する深さを有することを特徴とする付記１または２記載の電子部品。
（付記４）
前記絶縁樹脂材は前記複数の電子部品の保護材であることを特徴とする付記１ないし３のいずれかに記載の電子部品。
（付記５）
前記複数の電子部品は、厚さが互いに異なる電子部品を含むことを特徴とする付記１ないし４のいずれかに記載の電子部品。
（付記６）
載置台上に、電極が形成された電極形成面を有する複数の電子部品を、前記電極形成面に絶縁樹脂材が接しないように配置し固定する工程と、
前記載置台上において、前記絶縁樹脂材によって、前記複数の電子部品の側面及び裏面を覆って一体化し、かつ前記裏面に複数の溝を有するように絶縁樹脂材成型体を形成する工程と、
前記絶縁樹脂材成型体を前記載置台から分離する工程と
を含むことを特徴とする電子部品の製造方法。
（付記７）
さらに、前記絶縁樹脂材成型体をダイシングして複数の電子部品を有する個別の電子部品に分割する工程と
を含むことを特徴とする付記６記載の電子部品の製造方法。
（付記８）
前記複数の溝は、前記間隔の領域の前記裏面を覆う前記絶縁樹脂材領域を除いて形成されることを特徴とする付記６または７記載の状電子部品の製造方法。
（付記９）
前記複数の溝の少なくとも一部は、前記複数の電子部品の前記裏面に達する深さを有することを特徴とする付記６ないし８のいずれかに記載の電子部品の製造方法。
（付記１０）
前記絶縁樹脂材は、前記複数の電子部品の保護材であることを特徴とする請求項６ないし９のいずれかに記載の電子部品の製造方法。
（付記１１）
電極が形成された電極形成面を有する複数の電子部品と、
前記電極形成面を露出するように前記複数の電子部品が埋め込まれ、一体形成された絶縁樹脂材と、
前記複数の電子部品の裏面側に配置され、前記絶縁樹脂材中に形成された複数の溝とを有することを特徴とする電子機器。
（付記１２）
載置台上に、電極が形成された電極形成面を有する複数の電子部品を、前記電極形成面に絶縁樹脂材が接しないように配置し固定する工程と、
前記載置台上において、前記絶縁樹脂材によって、前記複数の電子部品の側面及び裏面を覆って一体化し、かつ前記裏面に複数の溝を有するように絶縁樹脂材成型体を形成する工程と、
前記絶縁樹脂材成型体を前記載置台から分離する工程と
を含むことを特徴とする電子機器の製造方法。
The following additional notes are disclosed regarding the embodiments including the above examples.
(Appendix 1)
A plurality of electronic components having an electrode forming surface on which electrodes are formed;
Insulating resin material in which the plurality of electronic components are embedded and integrally formed so as to expose the electrode formation surface;
An electronic component comprising: a plurality of grooves disposed in a back surface side of the plurality of electronic components and formed in the insulating resin material.
(Appendix 2)
The electronic component according to appendix 1, wherein the plurality of grooves are formed only in a region defined by the electronic component.
(Appendix 3)
The electronic component according to appendix 1 or 2, wherein at least a part of the plurality of grooves has a depth reaching a back surface of the plurality of electronic components.
(Appendix 4)
4. The electronic component according to any one of appendices 1 to 3, wherein the insulating resin material is a protective material for the plurality of electronic components.
(Appendix 5)
The electronic component according to any one of appendices 1 to 4, wherein the plurality of electronic components include electronic components having different thicknesses.
(Appendix 6)
A step of arranging and fixing a plurality of electronic components having an electrode forming surface on which electrodes are formed on a mounting table so that an insulating resin material does not contact the electrode forming surface;
On the mounting table, with the insulating resin material, covering and integrating the side surfaces and back surfaces of the plurality of electronic components, and forming an insulating resin material molded body so as to have a plurality of grooves on the back surface;
A step of separating the insulating resin material molded body from the mounting table.
(Appendix 7)
The method of manufacturing an electronic component according to appendix 6, further comprising a step of dicing the insulating resin material molded body into individual electronic components having a plurality of electronic components.
(Appendix 8)
8. The method of manufacturing an electronic component according to appendix 6 or 7, wherein the plurality of grooves are formed except for the insulating resin material region covering the back surface of the space region.
(Appendix 9)
9. The method of manufacturing an electronic component according to any one of appendices 6 to 8, wherein at least a part of the plurality of grooves has a depth reaching the back surface of the plurality of electronic components.
(Appendix 10)
10. The method of manufacturing an electronic component according to claim 6, wherein the insulating resin material is a protective material for the plurality of electronic components.
(Appendix 11)
A plurality of electronic components having an electrode forming surface on which electrodes are formed;
Insulating resin material in which the plurality of electronic components are embedded and integrally formed so as to expose the electrode formation surface;
An electronic apparatus comprising: a plurality of grooves disposed in a back surface side of the plurality of electronic components and formed in the insulating resin material.
(Appendix 12)
A step of arranging and fixing a plurality of electronic components having an electrode forming surface on which electrodes are formed on a mounting table so that an insulating resin material does not contact the electrode forming surface;
On the mounting table, with the insulating resin material, covering and integrating the side surfaces and back surfaces of the plurality of electronic components, and forming an insulating resin material molded body so as to have a plurality of grooves on the back surface;
And a step of separating the molded molded product of the insulating resin material from the mounting table.
１ 載置台
２ 載置台ホルダ
３ UV粘着シート
４ 樹脂材型枠
５ 半導体チップ
６ 電極形成面
７ 裏面
８ 側面
９ 樹脂材
１０ 突出構造
１１ 裏面形成用金型
１２ 樹脂材成型支持板
１３ 樹脂材成型体・モールド基板
１４ 単一電子部品領域
１５ アルミ電極
１６ パッシベーション膜
１７ 配線形成単一電子部品領域
１８ パッシベーション膜
１９ チップ間配線
２０ 引き出しパッド
２１ 電子部品
２２ 溝
２３ チップ間隔樹脂材
２４ 溝無し電子部品
２５ 電子部品例（１）
２６ 電子部品例（２）
２７ 電子部品例（３）
DESCRIPTION OF SYMBOLS 1 Mounting base 2 Mounting base holder 3 UV adhesive sheet 4 Resin material form 5 Semiconductor chip 6 Electrode formation surface 7 Back surface 8 Side surface 9 Resin material 10 Protrusion structure 11 Mold for back surface formation 12 Resin material molding support plate 13 Resin material molding Mold substrate 14 Single electronic component region 15 Aluminum electrode 16 Passivation film 17 Wiring formation single electronic component region 18 Passivation film 19 Inter-chip wiring 20 Drawer pad 21 Electronic component 22 Groove 23 Chip spacing resin material 24 Non-groove electronic component 25 Electron Part example (1)
26 Electronic parts example (2)
27 Examples of electronic components (3)
Claims (7)
前記電極形成面を露出するように前記複数の電子部品が埋め込まれ、一体形成された絶縁樹脂材と、
前記電子部品毎に、前記複数の電子部品の裏面側に配置され、前記絶縁樹脂材中に形成された複数の溝と、を有し、前記溝の少なくとも一部は、前記電子部品の前記裏面に達する深さを有することを特徴とする電子部品。 A plurality of electronic components having an electrode forming surface on which electrodes are formed;
Insulating resin material in which the plurality of electronic components are embedded and integrally formed so as to expose the electrode formation surface;
Wherein the electronic each component, the arranged plurality of the rear surface side of the electronic component, the insulating resin material a plurality of which are formed in the grooves, has, at least a portion of the groove, the back surface of the electronic component An electronic component having a depth reaching
前記載置台上において、前記絶縁樹脂材によって、前記複数の電子部品の側面及び裏面を覆って一体化し、かつ前記電子部品毎に、前記裏面に複数の溝を有し、前記溝の少なくとも一部は、前記電子部品の前記裏面に達する深さを有するように絶縁樹脂材成型体を形成する工程と、
前記絶縁樹脂材成型体を前記載置台から分離する工程と、
を含むことを特徴とする電子部品の製造方法。 A step of arranging and fixing a plurality of electronic components having an electrode forming surface on which electrodes are formed on a mounting table so that an insulating resin material does not contact the electrode forming surface;
On the mounting table, the insulating resin material covers and integrates side surfaces and back surfaces of the plurality of electronic components, and each electronic component has a plurality of grooves on the back surface, and at least a part of the grooves. Is a step of forming an insulating resin material molded body having a depth reaching the back surface of the electronic component;
Separating the insulating resin material molded body from the mounting table,
The manufacturing method of the electronic component characterized by including.
を含むことを特徴とする請求項４記載の電子部品の製造方法。 Further, the step of dicing the insulating resin material molded body and dividing it into individual electronic components having a plurality of electronic components;
The manufacturing method of the electronic component of Claim 4 characterized by the above-mentioned.
前記電極形成面を露出するように前記複数の電子部品が埋め込まれ、一体形成された絶縁樹脂材と、
前記電子部品毎に、前記複数の電子部品の裏面側に配置され、前記絶縁樹脂材中に形成された複数の溝と、を有し、前記溝の少なくとも一部は、前記電子部品の前記裏面に達する深さを有することを特徴とする電子機器。 A plurality of electronic components having an electrode forming surface on which electrodes are formed;
Insulating resin material in which the plurality of electronic components are embedded and integrally formed so as to expose the electrode formation surface;
Wherein the electronic each component, the arranged plurality of the rear surface side of the electronic component, the insulating resin material a plurality of which are formed in the grooves, has, at least a portion of the groove, the back surface of the electronic component An electronic device having a depth that reaches
前記載置台上において、前記絶縁樹脂材によって、前記複数の電子部品の側面及び裏面を覆って一体化し、かつ前記電子部品毎に、前記裏面に複数の溝を有し、前記溝の少なくとも一部は、前記電子部品の前記裏面に達する深さを有するように絶縁樹脂材成型体を形成する工程と、
前記絶縁樹脂材成型体を前記載置台から分離する工程と、
を含むことを特徴とする電子機器の製造方法。 A step of arranging and fixing a plurality of electronic components having an electrode forming surface on which electrodes are formed on a mounting table so that an insulating resin material does not contact the electrode forming surface;
On the mounting table, the insulating resin material covers and integrates side surfaces and back surfaces of the plurality of electronic components, and each electronic component has a plurality of grooves on the back surface, and at least a part of the grooves. Is a step of forming an insulating resin material molded body having a depth reaching the back surface of the electronic component;
Separating the insulating resin material molded body from the mounting table,
The manufacturing method of the electronic device characterized by including.
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| US9023690B2 (en) * | 2012-11-19 | 2015-05-05 | United Test And Assembly Center | Leadframe area array packaging technology |
| JP2016174101A (en) * | 2015-03-17 | 2016-09-29 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
| WO2024185056A1 (en) * | 2023-03-08 | 2024-09-12 | 日本電信電話株式会社 | Semiconductor device production method and semiconductor device |
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| JPH0878572A (en) * | 1994-08-31 | 1996-03-22 | Hitachi Ltd | Semiconductor package and manufacturing method thereof as well as circuit board and electronic equipment using the same |
| US5866952A (en) * | 1995-11-30 | 1999-02-02 | Lockheed Martin Corporation | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
| JP3842478B2 (en) * | 1999-02-26 | 2006-11-08 | 京セラ株式会社 | Mounting structure of semiconductor device mounting wiring board |
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