JP2008270633A - Semiconductor-element integrating substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor-element integrating substrate wherein the connective reliability present between the metal bumps of a semiconductor element and its conductor layer is excellent even when the pitch of the metal bumps to be the outer connecting electrodes of the semiconductor element is reduced. <P>SOLUTION: The semiconductor-element integrating substrate is provided with a semiconductor element integrated by a flip-chip mounting. In the substrate, metal bumps to be the outer connecting electrodes of the semiconductor element are fastened to the substrate by an adhesive agent, and are connected with the conductor layer constituted of metal plating. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a substrate with a built-in semiconductor element, and more particularly to a substrate with a built-in semiconductor element that has excellent connection reliability even when the pitch of metal bumps that serve as external connection electrodes of the semiconductor element is narrow.

  A structural example of a conventional substrate with a built-in semiconductor element will be described with reference to FIG. In FIG. 8, K is a substrate with a built-in semiconductor element. A semiconductor element 804 is mounted on an upper surface of an insulating layer 801 formed on the upper surface of the copper foil 802 with an adhesive 806, and the outside of the semiconductor element 804 is provided. Metal bumps 805 serving as connection electrodes are connected to the metal layer 802 via solder 813, and an insulating base 807 is formed on the side and upper layers of the semiconductor element 804, and the upper surface of the insulating base 807 A copper foil 808 is formed on the substrate.

Next, a conventional method for manufacturing a substrate with a built-in semiconductor element will be described with reference to FIG.
First, in order to flip-chip mount a semiconductor element, an insulating layer 801 shown in FIG. 9A is bonded to a copper foil 802 to obtain a base material shown in FIG. 9B. Next, as shown in FIG. 9C, openings 803 corresponding to the metal bumps 805 to be external connection electrodes of the semiconductor element 804 are formed in the insulating layer 801 of the base material by laser processing. Next, as illustrated in FIG. 9D, after applying cream solder to the opening 803, the semiconductor element 804 including the metal bumps 805 is interposed between the semiconductor element 804 and the insulating layer 801 with an adhesive 806. It is mounted and the solder 813 is melted and joined by heat from reflow. Next, as shown in FIG. 9E, a semi-cured insulating base material 807 and a copper foil 808 are disposed on the side of the semiconductor element 804 and laminated, and the semiconductor shown in FIG. An element-embedded substrate K is obtained. The substrate K is further formed by exposing and developing an etching resist by photographic method and forming circuits on the upper and lower copper foils.

  According to such a conventional manufacturing method, if the pitch of the metal bumps 805 serving as the external connection electrodes of the semiconductor element 804 is 60 μm or more, the machine during laser processing of the opening 803 provided in the insulating layer 801 for mounting the semiconductor element It was possible to manufacture a substrate with a built-in semiconductor element even in consideration of the accuracy and the amount of deviation due to exposure during circuit formation.

However, when the pitch of the metal bumps 805 serving as the external connection electrodes of the semiconductor element 804 is 50 μm or less, the hole diameter and the land diameter are also reduced, so that the margin of positional deviation on processing is reduced, and the amount of mechanical processing deviation is reduced. As a result, the acid cleaning chemical solution at the time of circuit formation or the solder in which the etching solution is solidified in the etching process is dissolved, resulting in a problem in joining the semiconductor elements. FIG. 10 shows the semiconductor element built-in substrate K2 in which the solidified solder 813 is dissolved in an acid cleaning chemical solution or an etching solution when the circuits 809 and 810 are formed, and the bonding failure is caused. As a result, a dissolution defect M was formed, and a connection failure with the circuit 809 was inevitable.
Further, since the hole diameter and the land diameter are reduced, the problem that it becomes difficult to apply the cream solder is caused, and the pitch is narrowed, so that the problem of bridging due to the molten solder is also generated.

  In addition, as a conventional substrate with a built-in semiconductor element, a printed wiring board with a built-in semiconductor element by face-up mounting has already been reported (for example, see Patent Document 1). It could not cope with the narrow pitch of the bumps.

In particular, when the concave portion is formed by counterboring the base material, since the processing accuracy is loose, mounting the semiconductor element by face up is rather unsuitable for the external connection electrode of the semiconductor element having a narrow pitch. .
JP-A-9-321408

  In view of the above-mentioned problems, the present invention provides a semiconductor element-embedded substrate that can improve the connection reliability between a metal bump and a conductor layer, and can cope with a narrow pitch of the metal bump that serves as an external connection electrode. It is said.

  The present invention is a substrate in which a semiconductor element is incorporated by flip-chip mounting, and metal bumps serving as external connection electrodes of the semiconductor element are fixed with an adhesive and connected to a conductor layer made of metal plating. The above-described problems are solved by a substrate with a built-in semiconductor element.

  A semiconductor element-embedded substrate that does not impair connection reliability even when the pitch of metal bumps that serve as external connection electrodes is narrowed by connecting metal bumps that serve as external connection electrodes and a conductor layer made of metal plating is provided. I can do it.

  In the present invention, the metal bump is fixed by an adhesive interposed between the semiconductor element and the insulating layer in an opening provided in the insulating layer in advance, and is exposed from the insulating layer. It is a feature.

  Since the metal bumps are exposed from the insulating layer, stable connection with the conductor layer made of metal plating is possible.

  Further, the present invention is characterized in that the metal bump is exposed flush with the insulating layer.

  Since the end face of the metal bump is exposed flush with the insulating layer, a stable connection with the conductor layer made of metal plating is possible.

  Further, the present invention is characterized in that the metal bump is exposed in a convex shape from the insulating layer.

  Since the metal bumps are exposed in a convex shape from the insulating layer, the connection area with the conductor layer made of metal plating increases, and the amount of misalignment due to machining can be absorbed.

  Further, the present invention is characterized in that a conductor layer connected to the metal bump is formed in a semi-additive circuit.

  Since the circuit can be formed with higher positional accuracy when the metal foil is formed by semi-additive (electroless / electrolytic plating) than when the circuit is formed by the subtractive method, the positional deviation is reduced. It is also possible to form a finer circuit.

  ADVANTAGE OF THE INVENTION According to this invention, even if the metal bump pitch used as the external connection electrode of a semiconductor element is narrowed, the board | substrate with a built-in semiconductor element excellent in the connection reliability of the said metal bump and a conductor layer can be provided.

A first embodiment of a substrate with a built-in semiconductor element according to the present invention will be described with reference to FIG.
In FIG. 1, P is a substrate with a built-in semiconductor element, on which a semiconductor element 104 is mounted above an insulating layer 101 via an adhesive 106, and metal bumps 105 serving as external connection electrodes of the semiconductor element 104 are bonded. While being fixed by the agent 106, it is connected to the conductor layer 109 made of the electroless metal plating 109a and the electrolytic metal plating 109b. In addition, an insulating base material 107 is formed on the side and upper layers of the semiconductor element 104, and a conductor layer 110 made of metal plating 110 a and 110 b is formed on the upper surface of the insulating base material 107.

Next, a method for manufacturing the semiconductor element-embedded substrate P of the present invention will be described with reference to FIGS.
First, the insulating layer 101 shown in FIG. 2A is prepared and bonded to the metal layer 102 shown in FIG. Next, as shown in FIG. 2C, openings 103 corresponding to the metal bumps 105 serving as external electrodes of the semiconductor element 104 are formed in the insulating layer 101 by laser processing. Next, as shown in FIG. 2D, the semiconductor element 104 including the metal bumps 105 is mounted and fixed between the semiconductor element 104 and the insulating layer 101 with an adhesive 106 interposed therebetween. Next, as shown in FIG. 2 (e), a sheet-like semi-cured insulating base material 107 is disposed on the side of the semiconductor element 104, and a metal foil 108 is disposed on the upper surface thereof, laminated, and FIG. A substrate shown in FIG.

Here, the insulating layer 101 to be bonded to the metal layer 102 is not particularly limited. However, a glass cloth is not used. However, when the opening 103 is formed by laser processing, no burr or the like of the glass cloth is generated. It is preferable because a hole can be formed.
As the insulating layer 101, an epoxy resin filled with an inorganic filler is preferably used.

  The semiconductor element 104 includes metal bumps 104 that serve as external connection electrodes. Examples of the metal bumps 105 include gold bumps, silver bumps, copper bumps, and nickel bumps.

  As the adhesive 106 for fixing the semiconductor element 104, NCP (Non-Conductive-Paste), NCF (Non-Conductive-Film), or the like can be used. The external connection electrode of the semiconductor element 104 is previously formed on the insulating layer 101. In order to provide the opening 103 serving as a temporary installation for mounting the metal bump 105, it is preferable to use NCP in consideration of the filling property of the adhesive 106 into the opening 103. The adhesive 106 also serves to alleviate the difference in linear expansion coefficient between the semiconductor element 104 made of silicon and the insulating layer 101.

  As the sheet-like semi-cured insulating substrate 107 provided on the side of the semiconductor element 104, a glass cloth impregnated with epoxy resin is impregnated with prepreg or aramid fiber impregnated with epoxy resin in order to maintain the rigidity of the printed wiring board. A sheet-like insulating base material is preferably used.

  The insulating base 107 is processed at the portion corresponding to the semiconductor element 104 because the reinforcing material such as glass cloth does not overlap the semiconductor element when the insulating base 107 is cut by a die or a router. From the viewpoint of sex.

The insulating base 107 may be formed using a single layer insulating base or a plurality of layers of insulating base, for example, three prepregs.
In terms of controllability of the filling amount of the epoxy resin impregnated in the insulating base material 107, the use of a plurality of insulating base materials increases the resin flow in the lamination process, and can prevent unfilling of the resin. preferable.

  The insulating substrate 107 is not limited to a sheet-like insulating substrate, and a flat surface can be formed by mechanical polishing such as buffing after applying resin by electrostatic spraying and curing.

  Furthermore, although the copper layer, aluminum foil, nickel foil, etc. can be used for the metal layer 108 laminated | stacked on the upper layer, the copper foil which is cheap and easy to process is used suitably.

  Next, as shown in FIG. 3G, the upper and lower metal layers 108 are removed by etching. Next, as shown in FIG. 3 (h), the insulating layer 101 and the adhesive layer 106 are polished by a dry process, for example, excimer laser, plasma desmear, buffing, mechanical polishing, etc., so that the metal bumps 105 are flush with the insulating layer 101. Is polished until the end face of the metal bump 105 is exposed from the insulating layer 101. Next, after electroless metal plating is performed on the entire surface, a plating resist is formed on the electroless metal plating, and portions of the plating resist that become the conductor layers 109 and 110 are removed by exposure and development. Next, after performing electrolytic metal plating, the plating resist is peeled off, and the exposed electroless metal plating is removed by flash etching. As shown in FIG. A substrate P with a built-in semiconductor element of the present invention connected to the conductor layer 109 made of electrolytic metal plating 109b is obtained.

  Here, as a polishing method for exposing the end surfaces of the metal bumps 105, the metal bumps 105 are polished until they are flush with the insulating layer 101 by chemical polishing by a wet process instead of the above-described dry process. The end face of the metal bump 105 may be exposed from the insulating layer 101.

  Further, if the adhesive 106 around the insulating layer 101 and the metal bump 105 is further polished by a wet process to form a structure in which the metal bump 105 is exposed from the insulating layer 101 as shown in FIG. Since the connection area with the conductor layer 109 made of is increased, it is more preferable.

  Examples of the polishing by the wet process include desmear treatment. Here, as the desmear treatment liquid, a sodium permanganate solution or the like is used, and the insulating layer 101 and the adhesive 106 are dissolved by an immersion method. In this case, it is preferable to select a material having substantially the same dissolution speed of the insulating layer 101 and the adhesive 106 such as a sodium permanganate solution.

Next, a second embodiment of the substrate with a built-in semiconductor element according to the present invention will be described with reference to FIG.
The semiconductor element-embedded substrate P2 according to the second embodiment is different from the semiconductor element 104 except that the core substrate 111 having conductor circuits formed on both sides is disposed in the insulating base 107 on the side of the semiconductor element 104. The configuration is the same as that of the semiconductor element built-in substrate P according to the first embodiment.
In this manner, by effectively using the space of the insulating base material 107 disposed on the side of the semiconductor element 104, the thickness of the substrate in which the semiconductor element 104 is built can be reduced.

Next, a third embodiment of the substrate with a built-in semiconductor element according to the present invention will be described with reference to FIG.
The semiconductor element-embedded substrate P3 according to the third embodiment is a semiconductor according to the first embodiment except that the insulating layer 112 is provided on the semiconductor element 104 and the side insulating base 107. The configuration is the same as that of the element-embedded substrate P. Here, an insulating material different from that of the insulating layer 101 may be used for the insulating layer 112, but it is more preferable to use the same material. That is, by using the same material for the insulating layer 101 and the insulating layer 112, the semiconductor element 104 and the side insulating base material 107 have a vertically symmetrical structure as the center, so that warpage as a substrate can be reduced. is there.

  Next, a fourth embodiment of the substrate with a built-in semiconductor element according to the present invention will be described with reference to FIG. The semiconductor element-embedded substrate P6 according to the fourth embodiment has a structure in which one build-up layer is provided above and below the semiconductor element-embedded substrate P shown in FIG.

Such a semiconductor element built-in substrate P6 is manufactured, for example, as follows.
First, as shown in FIG. 7A, a semiconductor element-embedded substrate P shown in FIG. 1 is prepared. Next, as shown in FIG. 7B, insulating bases made of a build-up base 113 are laminated on the upper and lower sides of the conductor layers 109 and 110 to form through holes and non-through holes. Apply electrolytic plating. Next, after forming the circuit 116 by photographic method, as shown in FIG. 6A, the solder resist 117 is formed on the outermost layer, thereby having the interlayer connection via 114 and the through plating through hole 115. A semiconductor element-embedded substrate P4 having a single build-up layer is obtained.

  By connecting the metal bumps 105 and forming a circuit by the semi-additive method, the circuit can be formed with higher accuracy than when the conventional metal foil is formed by the subtractive method. It is also possible to form a finer circuit.

Next, a fifth embodiment of the semiconductor element-embedded substrate of the present invention will be described with reference to FIG.
The semiconductor element embedded substrate P5 according to the fifth embodiment has a structure in which two build-up layers are provided above and below the semiconductor element embedded substrate P shown in FIG.

  In such a semiconductor element built-in substrate P5, as shown in FIG. 7C, an insulating base material composed of a build-up base material 118 is further laminated on the substrate shown in FIG. After forming a non-through hole, applying electroless / electrolytic plating to the entire surface, forming a circuit by photographic method, and forming a solder resist 120 on the outermost layer, as shown in FIG. A semiconductor element-embedded substrate P5 having an interlayer connection via 119 and having two build-up layers on the upper and lower sides is obtained. At this time, the filler 121 is filled in the through-plating through hole before the second-stage buildup base material is laminated. In addition, the said filling material 121 may be filled before the buildup base material 118 lamination | stacking of the 2nd step | paragraph, and you may fill the hole after buildup base material 118 lamination | stacking.

  As the fourth and fifth embodiments of the present invention, the example of the semiconductor element-embedded substrate in which the one-stage and two-stage buildup base materials are laminated has been described, but the semiconductor element-embedded substrate P shown in FIG. Needless to say, there are various modifications centered on the above.

BRIEF DESCRIPTION OF THE DRAWINGS Schematic cross-sectional explanatory drawing which shows 1st embodiment of the board | substrate with a built-in semiconductor element of this invention. BRIEF DESCRIPTION OF THE DRAWINGS The schematic cross-sectional process explanatory drawing which shows the manufacturing method of the board | substrate with a built-in semiconductor element of this invention. FIG. 3 is a schematic cross-sectional process explanatory diagram subsequent to FIG. 2. Schematic cross-sectional explanatory drawing which shows the other exposure state of a metal bump. (A) is schematic sectional explanatory drawing which shows 2nd embodiment of the board | substrate with a built-in semiconductor element of this invention, (b) is schematic sectional explanatory drawing which shows the 3rd embodiment. (A) is schematic sectional explanatory drawing which shows 4th embodiment of the board | substrate with a built-in semiconductor element of this invention, (b) is schematic sectional explanatory drawing which shows the 5th embodiment. FIG. 7 is a schematic cross-sectional process explanatory diagram showing a manufacturing method of the build-up substrate shown in FIG. 6. Schematic sectional view explanatory drawing of the conventional semiconductor element built-in board | substrate. Schematic cross-sectional process explanatory drawing which shows the manufacturing method of the conventional semiconductor element built-in board | substrate. Schematic cross-sectional explanatory drawing which shows the state of the solder connection failure of the conventional board | substrate with a built-in semiconductor element.

Explanation of symbols

101, 112, 801: Insulating layer 102, 108: Metal layer 103, 803: Opening 104, 804: Semiconductor element 105, 805: Metal bump 106, 806: Adhesive 107, 807: Insulating base material 109, 110, 809 810: Conductive layers 109a, 110a: Electroless metal plating 109b, 110b: Electrolytic metal plating 111: Core substrate 113, 118: Build-up base material 114, 119: Interlayer connection via 115: Through-plating through hole 116: Circuit 117, 120: Solder resist 121: Filler 802, 808: Copper foil 813: Solder P, P2, P3, P4, P5: Semiconductor device built-in substrate K of the present invention, K2: Conventional semiconductor device built-in substrate M: Dissolved defect portion

Claims (5)

  A substrate in which a semiconductor element is incorporated by flip-chip mounting, and metal bumps that are external connection electrodes of the semiconductor element are fixed with an adhesive and connected to a conductor layer made of metal plating A substrate with a built-in semiconductor element.   2. The metal bump is fixed in an opening provided in the insulating layer in advance by an adhesive interposed between the semiconductor element and the insulating layer, and is exposed from the insulating layer. The board | substrate with a built-in semiconductor element of description.   3. The semiconductor element-embedded substrate according to claim 2, wherein the metal bump is exposed from the insulating layer flush.   3. The semiconductor element built-in substrate according to claim 2, wherein the metal bumps are exposed in a convex shape from the insulating layer.   5. The semiconductor element-embedded substrate according to claim 1, wherein the conductor layer connected to the metal bump is formed in a semi-additive circuit. 6.