JPS60227492A - Electronic circuit block - Google Patents

Electronic circuit block

Info

Publication number
JPS60227492A
JPS60227492A JP8531284A JP8531284A JPS60227492A JP S60227492 A JPS60227492 A JP S60227492A JP 8531284 A JP8531284 A JP 8531284A JP 8531284 A JP8531284 A JP 8531284A JP S60227492 A JPS60227492 A JP S60227492A
Authority
JP
Japan
Prior art keywords
board
circuit block
electronic circuit
small
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8531284A
Other languages
Japanese (ja)
Inventor
達彦 入江
茂成 高見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP8531284A priority Critical patent/JPS60227492A/en
Publication of JPS60227492A publication Critical patent/JPS60227492A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔技術分野」 この発明は半導体素子、電子部品等を実装せる電子回路
ブロックに関する。 ′ 〔背景技術」 従来の、プリント配線は、電気回路基板に半導体素子と
電子部品を混在実装する電子回路ブロックは一般に、ま
ず、半導体素子を、グイボンド、ワイヤボンドをへて固
定し封止した後に他の電子部品を半田等で同基板に取付
けるという方法で形成する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an electronic circuit block on which semiconductor elements, electronic components, etc. can be mounted. [Background technology] In conventional printed wiring, electronic circuit blocks in which semiconductor elements and electronic components are mixedly mounted on an electric circuit board are generally manufactured by first fixing and sealing the semiconductor elements using wire bonds and wire bonds. It is formed by attaching other electronic components to the same board using solder or the like.

この場合の問題点は、次の通りである。■ 半導体素子
の封止樹脂を、一定の形状に維持して封止することが困
難であるので耐湿性等の封止信頼性が不安定となる。■
 電気回路基板が大きい場合、基板ソリの影響により、
半導体素子のボンディングの信頼性が欠ける。■ 一般
に、ボンディング、封止工程は加熱工程となるため、電
気回路基板の導体都(通例、銅箔)が酸化を受け、後工
程での電子部品の半田付は性が低下する。
The problems in this case are as follows. (2) Since it is difficult to maintain the sealing resin of a semiconductor element in a fixed shape while sealing, sealing reliability such as moisture resistance becomes unstable. ■
When the electric circuit board is large, due to the influence of board warpage,
Bonding reliability of semiconductor elements is lacking. ■ Since the bonding and sealing processes generally involve heating, the conductor (usually copper foil) of the electrical circuit board is oxidized, which reduces the soldering properties of electronic components in the subsequent process.

〔発明の目的」 この発明は半導体素子封止の信頼性をあげた電子回路ブ
ロックを提供せんとする。
[Object of the Invention] The present invention aims to provide an electronic circuit block with improved reliability in encapsulating semiconductor elements.

〔発明の開示」 この発明による電子回路ブロックは、jl1図乃土弟3
図に示すように半導体素子(1)と電、子部品■)を混
在実装する電子回路ブロックにおいて、半導体素子(1
)は他の電子部品(2)をもあわせ搭載する電気回路基
板(母基板用3)とは別の小型の電気回路基板(小基板
)(4)にワイヤボンド、ダイボンド等で実装し、他方
、母基板(3)には孔(6)をあけ、前記小基板(4)
を、塔載せる半導体素子(1)を絞孔(6)に入れると
共に各々の電極(7)、(8)をフェースダウン接ブロ
ックである。
[Disclosure of the invention] The electronic circuit block according to this invention is
As shown in the figure, in an electronic circuit block in which a semiconductor element (1) and an electronic component (■) are mixedly mounted, the semiconductor element (1)
) is mounted by wire bonding, die bonding, etc. on a small electric circuit board (small board) (4) that is separate from the electric circuit board (mother board 3) on which other electronic components (2) are also mounted, and , a hole (6) is made in the mother board (3), and the small board (4)
The semiconductor element (1) to be mounted thereon is placed in the aperture hole (6), and the respective electrodes (7) and (8) are connected face-down to the block.

この発明による電子回路ブロックの製造工程は次の通り
である。
The manufacturing process of the electronic circuit block according to the present invention is as follows.

半導体素子(1)は小基板(4)にダイボンド、ワイヤ
ボンドにより実装する。
A semiconductor element (1) is mounted on a small substrate (4) by die bonding or wire bonding.

同小基板(4)周辺部の電極(7)を、前記半導体素子
(1)を内包可能な母基板(3)上の孔(6)周辺部の
所定の電極8)にフェースダウン方式で接合する形で、
他の電子部品(2)と共に半田付けする。
The electrode (7) on the periphery of the small substrate (4) is bonded face-down to a predetermined electrode 8) on the periphery of the hole (6) on the mother substrate (3) that can contain the semiconductor element (1). in the form of
Solder together with other electronic components (2).

その上で母基板(3)を逆転させ、前述の母基板(3)
上の孔(6)に封止樹脂(5)を注入し加熱硬化させ半
導体素子を封止することにより完成品としている。
Then, reverse the mother board (3) and place the mother board (3) as described above.
A finished product is obtained by injecting the sealing resin (5) into the upper hole (6) and curing it by heating to seal the semiconductor element.

し発明の効果〕 以上のようにこの発明の電子回路ブロックによれば、母
基板(3)の孔(6)を利用して、封止樹脂(51を一
定の厚さ、形状で硬化させることが可能となり、半導体
素子(1)の封止信頼性が向上する。
[Effects of the Invention] As described above, according to the electronic circuit block of the present invention, the hole (6) of the mother board (3) can be used to harden the sealing resin (51) to a constant thickness and shape. This makes it possible to improve the sealing reliability of the semiconductor element (1).

半導体素子(1)を実装する小基板(4)は小さく形成
すること可能であり、母基板(3)のソリの影響受けに
く\、ボンディング信頼性が向上する。
The small substrate (4) on which the semiconductor element (1) is mounted can be formed small, is less affected by warpage of the mother substrate (3), and bonding reliability is improved.

半導体素子(1)を実装する小基板(4)はフェースダ
ウン方式で母基板(3)に実装するため、片面電気回路
基板の使用で形成可能であり、経済的な製作ができる。
Since the small substrate (4) on which the semiconductor element (1) is mounted is mounted on the motherboard (3) in a face-down manner, it can be formed using a single-sided electric circuit board, and can be manufactured economically.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図に示すのはこの発明の一実施例を示す
図で、第1図及び第2図は斜視図、第3図は断面図であ
る。
1 to 3 are views showing one embodiment of the present invention, in which FIGS. 1 and 2 are perspective views, and FIG. 3 is a sectional view.

Claims (1)

【特許請求の範囲】[Claims] (11半導体素子(1)と電子部品<2)を混在実装す
る電子回路ブロックに2いて、半導体素子(11は他の
電子部品シ)をもあわせ塔載する電気回路基板(母基板
)(3)とは別の小型の電気回路基板(小基板)(4)
にワイヤボンド、ダイホント等で実装し、他方、母基板
(3)には孔(6)をあけ、前記小基板(4)を、塔載
せる半導体素子(1)を鎖孔(67に入れると共に各々
の電極(71,(81をフェースダウン接続するように
(11 is an electronic circuit block on which semiconductor elements (1) and electronic components <2) are mixedly mounted, and an electric circuit board (mother board) (3) on which semiconductor elements (11 is other electronic components) is also mounted. ) A small electric circuit board (small board) (4)
On the other hand, a hole (6) is made in the mother board (3), and the semiconductor element (1) to be mounted on the small board (4) is inserted into the chain hole (67), and each Connect the electrodes (71, (81) face down.
JP8531284A 1984-04-25 1984-04-25 Electronic circuit block Pending JPS60227492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8531284A JPS60227492A (en) 1984-04-25 1984-04-25 Electronic circuit block

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8531284A JPS60227492A (en) 1984-04-25 1984-04-25 Electronic circuit block

Publications (1)

Publication Number Publication Date
JPS60227492A true JPS60227492A (en) 1985-11-12

Family

ID=13855085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8531284A Pending JPS60227492A (en) 1984-04-25 1984-04-25 Electronic circuit block

Country Status (1)

Country Link
JP (1) JPS60227492A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62180970U (en) * 1986-05-08 1987-11-17
JP2008294330A (en) * 2007-05-28 2008-12-04 Shinko Electric Ind Co Ltd Substrate with built-in chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515187A (en) * 1974-03-11 1976-01-16 Baker Perkins Holdings Ltd SHINAMONOOKURISOCHI
JPS5946085A (en) * 1982-09-09 1984-03-15 ソニー株式会社 Card

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515187A (en) * 1974-03-11 1976-01-16 Baker Perkins Holdings Ltd SHINAMONOOKURISOCHI
JPS5946085A (en) * 1982-09-09 1984-03-15 ソニー株式会社 Card

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62180970U (en) * 1986-05-08 1987-11-17
JP2008294330A (en) * 2007-05-28 2008-12-04 Shinko Electric Ind Co Ltd Substrate with built-in chip

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