JP3257931B2 - Semiconductor package, method of manufacturing the same, and semiconductor device - Google Patents
Semiconductor package, method of manufacturing the same, and semiconductor deviceInfo
- Publication number
- JP3257931B2 JP3257931B2 JP18370695A JP18370695A JP3257931B2 JP 3257931 B2 JP3257931 B2 JP 3257931B2 JP 18370695 A JP18370695 A JP 18370695A JP 18370695 A JP18370695 A JP 18370695A JP 3257931 B2 JP3257931 B2 JP 3257931B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- adhesive
- semiconductor chip
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体パッケージに
関し、特に基板と該基板上に搭載される半導体チップと
の間に両面が粗面化された絶縁性フィルムを介装し、基
板上の半導体チップの搭載部内にある配線回路、スルー
ホールと半導体チップとの間の電気的絶縁を行った半導
体パッケージに関する。また、当該半導体パッケージを
用いた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor chip having a roughened surface on both sides between a substrate and a semiconductor chip mounted on the substrate. And a semiconductor package in which electrical insulation is provided between a through-hole and a semiconductor chip in a mounting portion. Further, the present invention relates to a semiconductor device using the semiconductor package.
【０００２】[0002]
【従来の技術】近年、一つの基板上に複数の半導体チッ
プを搭載するマルチチップモジュール等の高密度半導体
装置が実用化されている。このような高密度半導体装置
においては、基板自体の大きさは規格等によって制限さ
れてしまうため、半導体チップ自体を他の半導体チップ
と接近させて基板上に搭載する必要がある。また半導体
チップの端子の数も多くなり、それに伴って基板に設け
るリードピンの数も多くなり、基板全体にわたってスル
ーホールや配線回路を設ける必要がある。よって、基板
上に形成されたこれら配線回路、スルーホール上にも半
導体チップを搭載する場合もあり、例えば特開平４−１
０３１５２号に開示されているように配線回路、スルー
ホールと半導体チップとの間の電気的絶縁を確保すべ
く、絶縁性フィルムを配線回路、スルーホールと半導体
チップとの間に介装し、同じく電気的絶縁性を有する接
合用接着剤を用いて基板上に絶縁性フィルムおよび半導
体チップを順次接着して搭載している。2. Description of the Related Art In recent years, high-density semiconductor devices such as a multi-chip module in which a plurality of semiconductor chips are mounted on one substrate have been put to practical use. In such a high-density semiconductor device, since the size of the substrate itself is limited by the standard or the like, it is necessary to mount the semiconductor chip itself on the substrate so as to approach another semiconductor chip. In addition, the number of terminals of the semiconductor chip increases, and accordingly, the number of lead pins provided on the substrate also increases, and it is necessary to provide through holes and wiring circuits over the entire substrate. Therefore, a semiconductor chip may be mounted on these wiring circuits and through holes formed on the substrate.
No. 03152, an insulating film is interposed between the wiring circuit, the through-hole and the semiconductor chip so as to secure electrical insulation between the wiring circuit and the through-hole and the semiconductor chip. An insulating film and a semiconductor chip are sequentially bonded and mounted on a substrate using a bonding adhesive having electrical insulation.
【０００３】[0003]
【発明が解決しようとする課題】半導体チップと基板の
配線回路、スルーホールとの間に介装される上記の絶縁
性フィルムには、通常ポリイミドフィルムなどの低誘電
率な有機材料を用い、半導体チップや基板上の配線回路
を通る信号伝送の高速化を図っている。しかしながら、
一般的にポリイミドフィルムなどの有機材料を使用した
絶縁性フィルムの表面は滑らかであり、接合用接着剤が
硬化した後に温度変化によって半導体チップや基板、絶
縁性フィルムが膨張・収縮を繰り返す際に、接合用接着
剤と絶縁性フィルムとの間で剥離が生じる可能性がある
という課題がある。The insulating film interposed between the semiconductor chip and the wiring circuit of the substrate and the through hole is usually made of a low dielectric constant organic material such as a polyimide film. It aims to speed up signal transmission through wiring circuits on chips and substrates. However,
In general, the surface of an insulating film using an organic material such as a polyimide film is smooth, and when a semiconductor chip, a substrate, and an insulating film repeat expansion and contraction due to a temperature change after the bonding adhesive is cured, There is a problem that peeling may occur between the bonding adhesive and the insulating film.
【０００４】従って、本発明は上記課題を解決すべくな
され、その目的とするところは、温度変化に対しても接
合用接着剤と絶縁性フィルムとの間で剥離が生じるおそ
れの少ない半導体パッケージおよび半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor package and a semiconductor package which are less likely to peel between a bonding adhesive and an insulating film even with a temperature change. It is to provide a semiconductor device.
【０００５】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、本発明にかかる
半導体パッケージは、半導体チップ搭載部に配線回路及
びスルーホールが形成された基板と、両面が粗面化さ
れ、片面側が接合用接着剤により、前記基板の半導体チ
ップ搭載部に接着された絶縁性フイルムとを具備するこ
とを特徴とする。 また、半導体チップ搭載部に配線回路
及びスルーホールが形成された基板と、 両面に粗化用接
着剤層が形成され、この各粗化用接着剤層の表面が粗面
に形成されると共に、この粗面に形成された面の片面側
が接合用接着剤により、前記基板の半導体チップ搭載部
に接着された絶縁性フイルムとを具備することを特徴と
する。この構成を採用することにより、接合用接着剤は
粗面の凹凸内に入り込んで硬化するために、接合用接着
剤と絶縁性フィルムとの間で剥離が生じにくくなる。ま
た、前記絶縁性フイルムがポリイミドフイルムからな
り、前記粗化用接着剤層がポリイミド系樹脂接着剤から
なることを特徴とする。 さらに、前記接合用接着剤がエ
ポキシ樹脂接着剤からなることを特徴とする。 前記絶縁
性フィルムの半導体チップが搭載される面側の周縁に
は、接合用接着剤の流れ止め用の枠体を配置すると、接
合用接着剤が絶縁性フイルム上から垂れるのを防止でき
る。また本発明に係る半導体パッケージの製造方法で
は、絶縁性フィルムの両面に、粗化用接着剤層を形成す
る工程と、該各粗化用接着剤層に表面が粗面に形成され
た金属箔の粗面側を熱圧着する工程と、前記各金属箔を
剥離またはエッチングして除去し、金属箔の粗面の凹凸
を前記各粗化用接着剤層の表面に転写する工程と、両面
に形成された各粗化用接着剤層の表面が粗面に形成され
た前記絶縁性フイルムの片面側を接合用接着剤により、
半導体チップ搭載部に配線回路及びスルーホールが形成
された基板の前記半導体チップ搭載部に接着する工程と
を具備することを特徴とする。 また本発明に係る半導体
装置は、上記の半導体パッケージの前記絶縁性フィルム
上に半導体チップが接合用接着剤により接着されて搭載
され、該半導体チップが樹脂封止されてなることを特徴
とする。 これにより、半導体チップの温度変化に対して
も接合用接着剤と絶縁性フイルムとの間で剥離が生じに
くくすることができる。 The present invention has the following arrangement to achieve the above object. That is, the semiconductor package according to the present invention includes a wiring circuit and a
Substrate with through holes and through holes
One side is bonded to the semiconductor chip of the substrate with a bonding adhesive.
And an insulating film adhered to the
And features. In addition, the wiring circuit
And roughening contacts on both sides
An adhesive layer is formed, and the surface of each of the roughening adhesive layers is roughened.
And one side of the rough surface
Is a semiconductor chip mounting portion of the substrate by a bonding adhesive.
And an insulating film bonded to the
I do. By adopting this configuration, the bonding adhesive enters into the unevenness of the rough surface and is hardened, so that peeling between the bonding adhesive and the insulating film hardly occurs. Ma
Further, the insulating film is made of a polyimide film.
The roughening adhesive layer is made of a polyimide resin adhesive.
It is characterized by becoming. Further, the bonding adhesive is
It is characterized by being made of a epoxy resin adhesive. The insulation
Around the surface of the conductive film on which the semiconductor chip is mounted
When the frame for stopping the flow of the bonding adhesive is placed,
This prevents the adhesive from dripping from the insulating film.
You. In the method for manufacturing a semiconductor package according to the present invention , the roughening adhesive layers are formed on both surfaces of the insulating film.
Forming a rough surface on each of the roughening adhesive layers.
Step of thermocompression bonding the rough side of the metal foil,
Removed by peeling or etching, uneven surface of metal foil
Transferring to the surface of each of the roughening adhesive layer,
The surface of each roughening adhesive layer formed on the
One side of the insulating film was bonded with a bonding adhesive,
Wiring circuits and through holes are formed in the semiconductor chip mounting area
Adhering to the semiconductor chip mounting portion of the formed substrate;
It is characterized by having. The semiconductor according to the present invention
The apparatus is provided with the insulating film of the semiconductor package described above.
A semiconductor chip is mounted on top with a bonding adhesive
Characterized in that the semiconductor chip is resin-sealed.
And This allows the semiconductor chip to respond to temperature changes
Also causes peeling between the bonding adhesive and the insulating film.
You can make it.
【０００６】[0006]
【発明の実施の形態】以下、本発明に係る半導体装置の
好適な実施形態を添付図面に基づいて詳細に説明する。
まず、図１、図２、図３を用いて半導体装置１０の一般
的な構造について説明する。１２は半導体チップであ
る。１４は基板であり、半導体パッケージの一部を構成
し、表面には図１や図２に示すように配線回路１６やス
ルーホール１８等が形成されており、一点鎖線内は半導
体チップ１２が搭載される搭載部Ｗである。基板１４
は、ガラス布エポキシやガラス布ＢＴやガラス布ポリイ
ミド等の樹脂材料の積層板で構成される場合や、またセ
ラミックで構成される場合もある。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.
First, a general structure of the semiconductor device 10 will be described with reference to FIGS. 1, 2, and 3. FIG. Reference numeral 12 denotes a semiconductor chip. Reference numeral 14 denotes a substrate, which constitutes a part of a semiconductor package, on the surface of which a wiring circuit 16 and a through hole 18 are formed as shown in FIGS. 1 and 2, and a semiconductor chip 12 is mounted in a dashed line. Mounting section W to be mounted. Substrate 14
May be composed of a laminate of a resin material such as glass cloth epoxy, glass cloth BT, or glass cloth polyimide, or may be composed of ceramic.
【０００７】また、基板１４の裏面にも配線回路１６が
形成されており、基板１４の表面、裏面の配線回路１６
同志は図３に示すようにスルーホール１８内に形成した
導体により電気的に接続されている。基板１４裏面の配
線回路１６には、はんだバンプ等の外部接続端子１９
が、半導体チップ１２を樹脂封止した後に取り付けられ
る。また、外部接続端子１９はスルーホール内にリード
ピンを挿通し、形成したものであっても良い。外部接続
端子としてはんだバンプが用いられる場合、スルーホー
ルにはレジストが充填される。A wiring circuit 16 is also formed on the back surface of the substrate 14, and the wiring circuit 16 on the front surface and the back surface of the substrate 14 is formed.
The competitors were formed in the through holes 18 as shown in FIG.
They are electrically connected by conductors . External connection terminals 19 such as solder bumps are provided on the wiring circuit 16 on the back surface of the substrate 14.
Are attached after the semiconductor chip 12 is sealed with resin. Further, the external connection terminal 19 may be formed by inserting a lead pin into a through hole. When solder bumps are used as external connection terminals, the through holes are filled with resist.
【０００８】２０は絶縁性フィルムであり、半導体パッ
ケージの一部を構成し、半導体チップ１２と基板１４の
搭載部Ｗとの間に、両面に接合用接着剤２２が塗布され
た状態で介装され、半導体チップ１２が基板１４上に絶
縁性フィルム２０を介して接着・固定される。なお、絶
縁性フィルム２０はポリイミドフィルムなどの有機材料
で形成されている。また接合用接着剤２２には半導体チ
ップ１２や配線回路１６やスルーホール１８等に対する
接着性、および半導体チップ１２が発熱しても接着性が
維持できるように耐熱性を考慮して、エポキシ樹脂接着
剤が使用される。また絶縁性フィルム２０は、片面に塗
布した接合用接着剤２２で基板１４に予め接合してお
き、半導体チップ１２を搭載する際にもう一方の面に接
合用接着剤２２を塗布し、半導体チップ１２を接合する
ようにしても良い。半導体チップ１２は、配線回路１６
の一部として形成された接続用端子２３との間を接続線
２４で電気的に接続された後にエポキシ系の封止樹脂
（不図示）により封止される。なお、封止樹脂に代えて
キャップにより封止しても良い。Reference numeral 20 denotes an insulating film which constitutes a part of the semiconductor package and is interposed between the semiconductor chip 12 and the mounting portion W of the substrate 14 in a state where the bonding adhesive 22 is applied to both surfaces. Then, the semiconductor chip 12 is bonded and fixed on the substrate 14 via the insulating film 20. Note that the insulating film 20 is formed of an organic material such as a polyimide film. The bonding adhesive 22 has a semiconductor chip.
An epoxy resin adhesive is used in consideration of adhesiveness to the chip 12, the wiring circuit 16, the through hole 18, and the like, and heat resistance so that the adhesiveness can be maintained even when the semiconductor chip 12 generates heat. Also, the insulating film 20 is previously bonded to the substrate 14 with a bonding adhesive 22 applied to one surface, and when the semiconductor chip 12 is mounted, the bonding adhesive 22 is applied to the other surface. 12 may be joined. The semiconductor chip 12 includes a wiring circuit 16
Is electrically connected to the connection terminal 23 formed as a part of the connection terminal by a connection line 24, and then sealed with an epoxy-based sealing resin (not shown). In addition, you may seal with a cap instead of sealing resin.
【０００９】また、絶縁性フィルム２０の両面は図４に
示すように粗面に形成されている。その形成方法の一例
としては、絶縁性フィルム２０の両面に粗化用接着剤２
６を塗布し、裏面が粗面に形成された（細かな無数の凹
凸が形成された）銅箔等の金属箔（不図示）を熱圧着し
て粗化用接着剤２６を硬化させ、その後に金属箔を剥離
またはエッチングすることで金属箔を除去して、金属箔
の裏面の凹凸を粗化用接着剤２６に転写して粗面に形成
する方法がある。この粗化用接着剤２６には絶縁性フィ
ルム２０と同様のポリイミド系樹脂接着剤が使用され、
絶縁性フィルム２０との間の接着性を確保している。金
属箔の裏面の複雑な凹凸を利用することによって、絶縁
性フィルム２０の表面を、複雑な形状の凹凸で形成され
た粗面とすることができ、後述するように接合用接着剤
２２との接合性を向上できる。Further, both surfaces of the insulating film 20 are formed as rough surfaces as shown in FIG. As an example of the formation method, the roughening adhesive 2 is applied to both surfaces of the insulating film 20.
6 is applied, and a metal foil (not shown) such as a copper foil or the like having a rough rear surface (on which numerous countless irregularities are formed) is thermally pressed to cure the roughening adhesive 26, and thereafter There is a method in which the metal foil is removed by peeling or etching the metal foil, and the irregularities on the back surface of the metal foil are transferred to the roughening adhesive 26 to form the rough surface. For the roughening adhesive 26, a polyimide resin adhesive similar to the insulating film 20 is used.
Adhesion with the insulating film 20 is ensured. By using the complex irregularities on the back surface of the metal foil, the surface of the insulating film 20 can be made a rough surface formed with irregularities of a complicated shape. Joinability can be improved.
【００１０】このようにして絶縁性フィルム２０の両面
が粗面に形成されているため、粗面の凹凸２８の間隔や
接合用接着剤２２の硬化前の流動性を適宜に設定すれ
ば、硬化前に接合用接着剤２２が絶縁性フィルム２０の
表面に形成された無数の凹凸２８の隙間に入り込み、そ
の後に硬化させることができる。接合用接着剤２２の硬
化後は、接合用接着剤２２と絶縁性フィルム２０の表面
に接着されて粗面を構成する粗化用接着剤２６とが物理
的に噛み合った状態となる。よって、接合用接着剤２２
が硬化した後には、温度変化によって半導体チップ１２
や基板１４、絶縁性フィルム２０が膨張・収縮を繰り返
し、接合用接着剤２２と絶縁性フィルム２０との間に図
３の左右方向のズレが生じようとした場合でも、接合用
接着剤２２と絶縁性フィルム２０とが剥離することを低
減できる。Since both surfaces of the insulating film 20 are formed in a rough surface in this manner, if the spacing between the unevenness 28 on the rough surface and the fluidity of the bonding adhesive 22 before curing are appropriately set, the curing can be performed. The bonding adhesive 22 previously enters the gaps between the countless irregularities 28 formed on the surface of the insulating film 20 and can be cured thereafter. After the bonding adhesive 22 is cured, the bonding adhesive 22 and the roughening adhesive 26 that is bonded to the surface of the insulating film 20 to form a rough surface are in a state of being physically engaged. Therefore, the bonding adhesive 22
After hardening, the semiconductor chip 12
Even if the substrate 14 and the insulating film 20 repeatedly expand and contract, and the gap between the bonding adhesive 22 and the insulating film 20 tends to be shifted in the left-right direction in FIG. Separation from the insulating film 20 can be reduced.
【００１１】また、図５に示すように、絶縁性フィルム
２０の半導体チップ１２との接着面（図５の上面）の周
縁には、接合用接着剤２２の流れ止め用の枠体３０を配
置する構成としてもよい。枠体３０は、例えば銅等の金
属箔、金めっきパターン等のめっきによる金属層で形成
する方法がある。また、絶縁性フィルム２０自体を、そ
の上面の周縁部分が中央部分に比べて弱冠盛り上がる構
造となるように形成して、枠体３０としても良い。な
お、金属箔で枠体３０を形成する場合、粗面形成用の銅
箔等の金属箔を枠状に残すようにすれば好適である。As shown in FIG. 5, a frame 30 for stopping the flow of the bonding adhesive 22 is disposed on the periphery of the bonding surface of the insulating film 20 to the semiconductor chip 12 (the upper surface in FIG. 5). It is good also as a structure which performs. The frame 30 may be formed of a metal layer by plating such as a metal foil such as copper or a gold plating pattern. Further, the insulating film 20 itself may be formed so that the peripheral portion of the upper surface thereof has a structure in which the peripheral portion of the upper surface is slightly bulged as compared with the central portion, thereby forming the frame 30. When the frame 30 is formed of a metal foil, it is preferable to leave a metal foil such as a copper foil for forming a rough surface in a frame shape.
【００１２】以上、本発明の好適な実施形態について種
々述べてきたが、本発明は上述する実施形態に限定され
るものではなく、発明の精神を逸脱しない範囲で多くの
改変を施し得るのはもちろんである。As described above, various preferred embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.
【００１３】[0013]
【発明の効果】本発明に係る半導体パッケージを用いる
と、半導体チップは基板の半導体チップ搭載部に、両面
が粗面化された絶縁性フィルムを介して接合用接着剤に
より固定され、その接合用接着剤は絶縁性フィルムの表
面の凹凸に入り込んで硬化する。よって、接合用接着剤
と絶縁性フィルムとの間は物理的に噛み合った状態とな
るので、半導体チップや基板、絶縁性フィルムが温度変
化で膨張・収縮を繰り返した場合でも絶縁性フィルムと
接合用接着剤との間はずれにくく、従って剥離の発生が
少なくなる。また、絶縁性フィルムの周縁に枠体を設け
て、接合性接着剤の流れ止めとすれば、絶縁性フィルム
上面の接着剤の垂れを防止できる。また、絶縁性フィル
ムの粗面化は、粗化用接着剤を塗布し、裏面が粗面に形
成された金属箔を熱圧着し、この金属箔を剥離またはエ
ッチングすることで金属箔の裏面の凹凸を、塗布された
前記粗化用接着剤に転写して行うようにすれば、凹凸形
状の複雑な粗面を形成できる。また、このような半導体
パッケージを半導体装置に用いると、半導体チップの温
度変化に対しても接合用接着剤と絶縁性フィルムとの間
で剥離が生じにくい半導体装置を実現できるという著効
を奏する。When the semiconductor package according to the present invention is used, the semiconductor chip is fixed to the semiconductor chip mounting portion of the substrate via an insulating film having both surfaces roughened by a bonding adhesive. The adhesive enters the unevenness on the surface of the insulating film and cures. Therefore, the bonding adhesive and the insulating film are physically engaged with each other, so that even when the semiconductor chip, the substrate, and the insulating film repeatedly expand and contract due to a temperature change, the bonding between the bonding film and the insulating film is performed. It is difficult to separate from the adhesive, and therefore, the occurrence of peeling is reduced. If a frame is provided around the periphery of the insulating film to prevent the adhesive from flowing, the adhesive on the upper surface of the insulating film can be prevented from dripping. In addition, the roughening of the insulating film is performed by applying a roughening adhesive, thermocompression bonding a metal foil having a back surface formed on a rough surface, and peeling or etching the metal foil to form a back surface of the metal foil. If the irregularities are transferred to the applied roughening adhesive, a complicated rough surface having irregularities can be formed. Moreover, the use of such a semiconductor package in the semiconductor device exhibits a remarkable effect of realizing a semiconductor device which peeling is hard to occur between the even against the change in temperature of the semiconductor chip and the bonding adhesive and the insulating film.
【図１】半導体パッケージに使用される基板の平面図FIG. 1 is a plan view of a substrate used for a semiconductor package.
【図２】図１の基板と絶縁性フィルムから成る半導体パ
ッケージに半導体チップを搭載した半導体装置のＡ−Ａ
正面断面図FIG. 2 is a diagram illustrating an AA of a semiconductor device in which a semiconductor chip is mounted on a semiconductor package including a substrate and an insulating film of FIG. 1;
Front sectional view
【図３】図２のスルーホール部分の構造を示す要部拡大
図FIG. 3 is an enlarged view of a main part showing a structure of a through hole part in FIG. 2;
【図４】本発明に係る半導体パッケージの絶縁性フィル
ムと接合用接着剤との間の接着構造を示す説明図FIG. 4 is an explanatory view showing a bonding structure between an insulating film and a bonding adhesive of the semiconductor package according to the present invention.
【図５】本発明に係る半導体パッケージの他の実施形態
の構造を示す正面断面図FIG. 5 is a front sectional view showing the structure of another embodiment of the semiconductor package according to the present invention;
１０ 半導体装置 １２ 半導体チップ １４ 基板 １６ 配線回路 １８ スルーホール ２０ 絶縁性フィルム ２２ 接合用接着剤 DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Semiconductor chip 14 Substrate 16 Wiring circuit 18 Through hole 20 Insulating film 22 Adhesive for joining
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52,21/58 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21 / 52,21 / 58
Claims (7)
ーホールが形成された基板と、 両面が粗面化され、片面側が接合用接着剤により、前記
基板の半導体チップ搭載部に接着された絶縁性フイルム
とを具備することを特徴とする半導体パッケージ。 A wiring circuit and a through-hole are provided on a semiconductor chip mounting portion.
Substrate with holes formed, both surfaces are roughened, and one surface is
Insulating film adhered to the semiconductor chip mounting part of the substrate
And a semiconductor package comprising:
ーホールが形成された基板と、 両面に粗化用接着剤層が形成され、この各粗化用接着剤
層の表面が粗面に形成されると共に、この粗面に形成さ
れた面の片面側が接合用接着剤により、前記基板の半導
体チップ搭載部に接着された絶縁性フイルムとを具備す
ることを特徴とする半導体パッケージ。 2. A wiring circuit and a through-hole on a semiconductor chip mounting portion.
The substrate with the holes formed and the roughening adhesive layers formed on both sides
The surface of the layer is formed on a rough surface and
One side of the cut surface is bonded to the substrate by the bonding adhesive.
An insulating film adhered to the body chip mounting portion.
A semiconductor package, characterized in that:
ムからなり、前記粗化用接着剤層がポリイミド系樹脂接
着剤からなることを特徴とする請求項２記載の半導体パ
ッケージ。 3. The insulating film is a polyimide film.
And the roughening adhesive layer is made of polyimide resin.
3. The semiconductor package according to claim 2, comprising a binder.
Package.
からなることを特徴とする請求項１、２または３記載の
半導体パッケージ。 4. The bonding adhesive according to claim 1, wherein the bonding adhesive is an epoxy resin adhesive.
The method according to claim 1, 2, or 3, wherein
Semiconductor package.
載される面側の周縁には、接合用接着剤の流れ止め用の
枠体が配置されていることを特徴とする請求項１、２、
３または４記載の半導体パッケージ。 5. A semiconductor chip comprising said insulating film.
On the peripheral edge on the side where the
A frame is disposed, wherein the frame is arranged.
5. The semiconductor package according to 3 or 4.
層を形成する工程と、 該各粗化用接着剤層に表面が粗面に形成された金属箔の
粗面側を熱圧着する工程と、 前記各金属箔を剥離またはエッチングして除去し、金属
箔の粗面の凹凸を前記各粗化用接着剤層の表面に転写す
る工程と、 両面に形成された各粗化用接着剤層の表面が粗面に形成
された前記絶縁性フイ ルムの片面側を接合用接着剤によ
り、半導体チップ搭載部に配線回路及びスルーホールが
形成された基板の前記半導体チップ搭載部に接着する工
程とを具備することを特徴とする半導体パッケージの製
造方法。 6. A roughening adhesive on both sides of an insulating film.
Forming a layer, and forming a roughened surface of the metal foil on each of the roughening adhesive layers.
A step of thermocompression bonding the rough side, and removing or etching each of the metal foils,
Transfer the irregularities on the rough surface of the foil to the surface of each of the roughening adhesive layers.
Process, and the surface of each roughening adhesive layer formed on both surfaces is formed into a rough surface
The insulating Huy bonding adhesive one side of Lum, which is
Wiring circuits and through holes in the semiconductor chip mounting area
A step of bonding the formed substrate to the semiconductor chip mounting portion
Manufacturing a semiconductor package characterized by comprising the steps of:
Construction method.
導体パッケージの前記絶縁性フィルム上に半導体チップ
が接合用接着剤により接着されて搭載され、該半導体チ
ップが樹脂封止されてなることを特徴とする半導体装
置。 7. The half according to claim 1, 2, 3, 4 or 5.
A semiconductor chip on the insulating film of the conductor package;
Is mounted by bonding with a bonding adhesive, and the semiconductor chip is mounted.
Semiconductor device characterized in that the chip is sealed with resin.
Place.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18370695A JP3257931B2 (en) | 1995-07-20 | 1995-07-20 | Semiconductor package, method of manufacturing the same, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18370695A JP3257931B2 (en) | 1995-07-20 | 1995-07-20 | Semiconductor package, method of manufacturing the same, and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0936146A JPH0936146A (en) | 1997-02-07 |
| JP3257931B2 true JP3257931B2 (en) | 2002-02-18 |
Family
ID=16140534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18370695A Expired - Fee Related JP3257931B2 (en) | 1995-07-20 | 1995-07-20 | Semiconductor package, method of manufacturing the same, and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3257931B2 (en) |
-
1995
- 1995-07-20 JP JP18370695A patent/JP3257931B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0936146A (en) | 1997-02-07 |
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