JP4286640B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4286640B2
JP4286640B2 JP2003398372A JP2003398372A JP4286640B2 JP 4286640 B2 JP4286640 B2 JP 4286640B2 JP 2003398372 A JP2003398372 A JP 2003398372A JP 2003398372 A JP2003398372 A JP 2003398372A JP 4286640 B2 JP4286640 B2 JP 4286640B2
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lead wire
resist
bump
resin tape
lead
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JP2005159193A (en
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英之 金子
信之 幸谷
圭介 古谷
道成 手谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
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Description

本発明は、半導体装置およびその製造方法に関し、とくに樹脂テープ基材に形成されたリード線およびそのリード線上に接合用バンプを形成し、接合用バンプを介して半導体チップをリード線に接合した構造を持った半導体装置およびその製造方法に関するものである。具体的にはバンプを形成するためのドライフィルムレジストのラミネート方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular, a structure in which a lead wire formed on a resin tape base material and a bonding bump are formed on the lead wire, and a semiconductor chip is bonded to the lead wire via the bonding bump. The present invention relates to a semiconductor device having a structure and a manufacturing method thereof. Specifically, the present invention relates to a dry film resist laminating method for forming bumps.

図5に、従来の一般的なフレキシブル基板用テープに半導体チップがフリップチップボンディングでCOF接合される場合のリード線と金属バンプ付きチップの代表的な構造を示す。このCOF構造は図5に示す様に、樹脂テープ基材14にチップ12上の金属パッドと対向するリード線15を形成した構造を持つ。図5のCOF構造はデバイスホールを有しない。   FIG. 5 shows a typical structure of a lead wire and a chip with a metal bump when a semiconductor chip is bonded to a conventional general flexible substrate tape by flip chip bonding. As shown in FIG. 5, this COF structure has a structure in which a lead wire 15 facing a metal pad on a chip 12 is formed on a resin tape substrate 14. The COF structure of FIG. 5 has no device holes.

このCOF構造は樹脂テープ基材14にリード線(材質:Cu、Au、Sn等)15のみを形成している。チップ12を接合するための金属バンプ(材質:Au、Cu等)11は、対向するチップ12の電極の金属パッド上に形成される。この状態でリード線15とチップ12は位置合わせをし、加熱、加圧等によって接合されるのが一般的である。つまり、チップ12側に接合用バンプ11を形成し、樹脂テープ基材14側にはリード線15のみを形成する。13は封止樹脂である。   In this COF structure, only a lead wire (material: Cu, Au, Sn, etc.) 15 is formed on the resin tape substrate 14. Metal bumps (material: Au, Cu, etc.) 11 for bonding the chip 12 are formed on the metal pads of the electrodes of the chip 12 facing each other. In this state, the lead wire 15 and the chip 12 are generally aligned and joined by heating, pressing, or the like. That is, the bonding bumps 11 are formed on the chip 12 side, and only the lead wires 15 are formed on the resin tape base material 14 side. 13 is a sealing resin.

しかし、樹脂テープ基材14上のリード線15に、金属バンプ11を形成したチップ12を位置合わせをした後に接合する方法においては、2度の正確な位置合わせが必要となる。1つ目はチップ12上の電極に金属バンプ11を形成する際のマスク位置合わせ精度が必要である。2つ目はリード線15と金属バンプ11の位置合わせで、これについても高い精度が要求される。結果的に、双方の位置精度が総合して悪い場合、金属バンプ11がリード線15から外れることにもなり、正常な接合が成立しなくなる。   However, in the method in which the chip 12 on which the metal bumps 11 are formed is aligned with the lead wire 15 on the resin tape base material 14 and then joined, accurate alignment is required twice. The first requirement is mask alignment accuracy when forming the metal bumps 11 on the electrodes on the chip 12. The second is the alignment of the lead wire 15 and the metal bump 11, and this requires high accuracy. As a result, when the positional accuracy of both is poor, the metal bumps 11 are also detached from the lead wires 15 and normal bonding cannot be established.

本発明に関連するこれまでに出願された特許は無い。特許文献1には、樹脂テープ基材上に金属箔(銅箔など)を貼り、リードの配線にパターンに相当するマスクを形成し、その後下地の金属箔のみをエッチングし、配線パターンを形成する方法が紹介されている。
特開2003-37137
There are no previously filed patents related to the present invention. In Patent Document 1, a metal foil (copper foil or the like) is pasted on a resin tape substrate, a mask corresponding to a pattern is formed on a lead wiring, and then only the underlying metal foil is etched to form a wiring pattern. The method is introduced.
JP2003-37137

そこで、リード線側にバンプを形成し半導体チップを接合する方法が考えられた。   Therefore, a method has been considered in which bumps are formed on the lead wire side and semiconductor chips are bonded.

この方法によれば、従来の一般的な、金属バンプが形成されたチップとテープ基材上のリードとの接合に比べ、先述の一つ目の位置合わせ精度が必要でなくなりバンプ形成の位置精度が高精度である必要がなくなる。しかも、リードタイムの削減、製造コストの削減、リード線とバンプ間の位置ずれ解消などの効果がある。   According to this method, compared to the conventional general bonding of a chip on which a metal bump is formed and a lead on a tape substrate, the first alignment accuracy described above is not necessary and the positional accuracy of bump formation is eliminated. Need not be highly accurate. In addition, there are effects such as a reduction in lead time, a reduction in manufacturing cost, and elimination of misalignment between the lead wire and the bump.

しかし、樹脂テープ基材に形成したリード線上にバンプを形成する場合、リード線を形成した後に再度、めっきでバンプを積み上げる形をとるが、バンプ形成用のマスクをリード線が形成された上にラミネートする必要がある。その場合、リード線上にめっきバンプのマスクをラミネートする際に先に形成した高さのあるリード線が障害となり、マスクと樹脂テープ基材およびリード線とのラミネート性が、リード線が無い状態に比較して悪化する要因となる。 ラミネート性が悪化した場合、バンプのめっき形状の出来ばえ例えばバンプ高さ、幅および奥行きに悪影響を与える。   However, when bumps are formed on the lead wires formed on the resin tape base material, after forming the lead wires, the bumps are piled up again, but the bump forming mask is formed on the lead wires. Need to laminate. In that case, when the mask of the plating bump is laminated on the lead wire, the lead wire with the height previously formed becomes an obstacle, and the laminating property between the mask, the resin tape base material and the lead wire is such that there is no lead wire. It becomes a factor which gets worse in comparison. When the laminating property deteriorates, the finish of the bump plating shape, for example, the bump height, width and depth is adversely affected.

このように、リード線による凹凸の大きなところで如何にマスクの密着性を上げるかが課題となる。   Thus, the problem is how to improve the adhesion of the mask where the unevenness caused by the lead wire is large.

具体的に説明すると、図6に示すように樹脂テープ基材23上のリード線22上に更に金属バンプを形成しようとする場合、先にめっき付けされたリード線22上に再度めっき用レジスト21をラミネートしなければならない。当然、一度めっきがなされリード線22の高さ分だけ樹脂テープ基材面内には高低差(段差)が生じている。したがって、これまでの方法でめっき用レジスト21をラミネートした場合、リード高さが有る上に新たにめっき用レジストをラミネートしなければならず、これは樹脂テープ基材23およびリード線22と新たにラミネートしたレジスト21との間に隙間24が生じ易くなる。その結果、レジストのマスキング精度が悪く、めっきが所望のサイズ、形状からずれるといった不具合が生じる。また、先述の樹脂テープ基材23およびリード線22とバンプめっき用レジスト21の間に隙間24があった場合には、その隙間24にめっき液が入り込み、全く予期しない部分でめっきが生長する事が予想される。そのため、これらの不具合を防ぐためにはめっき用のレジスト21を隙間無くラミネートする必要が有る。   Specifically, as shown in FIG. 6, when further metal bumps are to be formed on the lead wires 22 on the resin tape substrate 23, the plating resist 21 is again formed on the lead wires 22 previously plated. Must be laminated. Naturally, once the plating is performed, a height difference (step) is generated in the surface of the resin tape substrate by the height of the lead wire 22. Therefore, when the plating resist 21 is laminated by the conventional method, the lead height has to be laminated, and the plating resist has to be newly laminated, which is newly added to the resin tape base material 23 and the lead wire 22. A gap 24 is easily generated between the laminated resist 21 and the resist 21. As a result, the masking accuracy of the resist is poor, and there arises a problem that the plating deviates from a desired size and shape. Further, if there is a gap 24 between the resin tape base material 23 and the lead wire 22 and the bump plating resist 21, the plating solution enters the gap 24, and the plating grows at an unexpected part. Is expected. Therefore, in order to prevent these problems, it is necessary to laminate the plating resist 21 without a gap.

したがって、この発明の目的は、樹脂テープ基材に形成されたリード線上に接合用バンプを形成し、接合用バンプを介して半導体チップをリード線に接合する構造の半導体装置において、ラミネート性悪化の問題を解決し、最初のリード線のめっき後に生じる段差(リード高さ)により2度目のめっきのためのレジストのラミネートに影響を及ぼさず、すなわち隙間が発生せず密着性を改善でき、その結果必要な寸法および形状にめっきされたバンプを形成することができる半導体装置およびその製造方法を提供することである。   Therefore, an object of the present invention is to form a bonding bump on a lead wire formed on a resin tape substrate, and in a semiconductor device having a structure in which a semiconductor chip is bonded to the lead wire via the bonding bump, the laminating property is deteriorated. The problem is solved and the step (lead height) after the first lead wire plating does not affect the resist lamination for the second plating, that is, there is no gap, and the adhesion can be improved. To provide a semiconductor device capable of forming bumps plated to a required size and shape and a method for manufacturing the same.

この発明の半導体装置は、表面にリード線が形成された樹脂テープ基材と、樹脂テープ基材上のリード線間に充填された感光性ポリイミドを含む充填材と、リード線および充填材上にラミネートするレジストを用いてリード線上に形成されたバンプと、バンプに電極が接合された半導体チップとを備えたものである。 Semi conductor arrangement of this invention, a resin tape base which leads are formed on the surface, the filler comprising a photosensitive polyimide which is filled between the leads on the resin tape base material, a lead wire and fillers on A bump is formed on a lead wire using a resist to be laminated on a semiconductor chip, and a semiconductor chip having an electrode bonded to the bump.

この発明の半導体装置の製造方法は、樹脂テープ基材の表面にリード線を形成する工程と、リード線間に感光性ポリイミドを含む充填材を充填する工程と、充填材の充填された状態でリード線上にレジストを貼り付ける工程と、レジストをマスクとしてリード線上に、半導体チップの電極と接合するためのバンプを形成する工程と、バンプに半導体チップを接合する工程とを含むものである。 State method for manufacturing a semi-conductor device, a step of forming a lead wire to the surface of the resin tape base material, a step of filling a filler comprising a photosensitive polyimide between the leads, which is filled in the filling material of the present invention The method includes a step of attaching a resist on the lead wire, a step of forming a bump on the lead wire for bonding to the electrode of the semiconductor chip, and a step of bonding the semiconductor chip to the bump using the resist as a mask.

この発明によれば、リード線間に感光性ポリイミドを含む充填材を充填することによりリード線と充填材との高さの差が樹脂テープ基材との高さの差よりも少なくなるので、レジストの密着性を向上でき、しかもリード線間に充填材を残しておくことができ除去する必要がない。 According to this invention, since the difference in height between the lead wire and the filler is less than the difference in height between the resin tape base material by filling the filler containing the photosensitive polyimide between the lead wires, The adhesiveness of the resist can be improved, and the filler can be left between the lead wires, and there is no need to remove it.

1の参考の形態を図1により説明する。すなわち、リード線32を形成した例えばポリイミドの樹脂テープ基材33上に粘度の高い液状またはゲル状の充填物質34が置かれ、その上にめっき用のレジスト例えばめっき用ドライフィルムレジスト31をラミネートし、その後レジスト31をマスクとしてリード線32上にバンプをめっきにより形成する。 A first reference embodiment will be described with reference to FIG. That is, a high-viscosity liquid or gel filling material 34 is placed on, for example, a polyimide resin tape base material 33 on which the lead wires 32 are formed, and a plating resist, for example, a plating dry film resist 31 is laminated thereon. Thereafter, bumps are formed on the lead wires 32 by plating using the resist 31 as a mask.

先述の充填物質34によってレジスト31は隙間をつくること無くリード線32に密着させることができる。   The filling material 34 described above allows the resist 31 to be in close contact with the lead wire 32 without forming a gap.

このように、この参考の形態は、リード線32と樹脂テープ基材(例えば基板)33の表面との段差を少なくするために、リード線32の相互間を粘度の高い液状またはゲル状の充填物質34例えばポリイミドなどで埋める方法である。高粘度液状またはゲル状物質34のテープ基材33上への塗布方法および残留方法は特定しない。この高粘度液状またはゲル状の物質34は、レジスト31との密着性の良い材料を選ぶ必要がある。そして、バンプ形成後、先述の液状物質またはゲル状物質34をレジスト31の除去の後、取り除く。 Thus, in this reference form, in order to reduce the level difference between the lead wire 32 and the surface of the resin tape base material (for example, the substrate) 33, a high-viscosity liquid or gel filling is provided between the lead wires 32. In this method, the material 34 is filled with polyimide or the like. The method for applying the high-viscosity liquid or gel substance 34 onto the tape base material 33 and the method for remaining it are not specified. For the high-viscosity liquid or gel substance 34, a material having good adhesion to the resist 31 needs to be selected. Then, after the bumps are formed, the liquid substance or gel substance 34 is removed after the resist 31 is removed.

2の参考の形態を図2により説明する。すなわち、樹脂テープ基材43に形成したリード線42上にレジストたとえばめっき用ドライフィルムレジスト41を載せた後に、レジスト41とテープ基材43との間を真空引きして減圧し、レジスト41とリード線42およびテープ基材43との密着性を上げる。その他、バンプの形成等は第1の参考の形態と同様である。 A second reference embodiment will be described with reference to FIG. That is, after a resist, for example, a dry film resist 41 for plating is placed on the lead wire 42 formed on the resin tape base material 43, the resist 41 and the tape base material 43 are evacuated to reduce the pressure. The adhesion between the wire 42 and the tape substrate 43 is increased. In addition, the formation of bumps and the like are the same as in the first reference embodiment.

3の参考の形態を図3により説明する。すなわち、レジストたとえばめっき用ドライフィルムレジスト51とテープ基材53との間に隙間を作る原因となるリード線52の高さ54を、レジスト51とテープ基材53との密着性に影響を及ぼさない程度までに下げるものである。リード線52の高さはリード線形成時に所定の高さに設定するか、あるいはリード線を一旦形成した後に減厚する。 A third embodiment will be described with reference to FIG. That is, the height 54 of the lead wire 52 that causes a gap between the resist, for example, the dry film resist 51 for plating and the tape base 53 does not affect the adhesion between the resist 51 and the tape base 53. It is lowered to the extent. The height of the lead wire 52 is set to a predetermined height when the lead wire is formed, or is reduced after the lead wire is once formed.

このように、リード線52の厚みを薄くすることで、リード線52の上面とテープ基材53との段差を少なくすることにより、レジスト51とテープ基材53の密着性を上げることができる。リード線52の高さは15μm以下であればレジスト51の密着性をよくすることができるが、好ましくは実績高さが凡そ8μmより8μm以下を目安とする。その他、バンプの形成等は第1の参考の形態と同様である。 Thus, by reducing the thickness of the lead wire 52 and reducing the level difference between the upper surface of the lead wire 52 and the tape base material 53, the adhesion between the resist 51 and the tape base material 53 can be improved. If the height of the lead wire 52 is 15 μm or less, the adhesion of the resist 51 can be improved. Preferably, the actual height is about 8 μm to 8 μm. In addition, the formation of bumps and the like are the same as in the first reference embodiment.

この発明の実施の形態を図4により説明する。すなわち、樹脂テープ基材64に形成したリード線62の相互間に感光性のポリイミド樹脂64を含む充填材を設け、リード62とテープ基材面高さとの段差を小さくする。これは第1の参考の形態の図1のリード線32の相互間に粘度の高い液状物質34を設けることでレジストたとえばめっき用ドライフィルムレジスト下に隙間を作らないようにする手法と同様の効果を狙っている。 The form of implementation of the invention will be described with reference to FIG. That is, a filler containing a photosensitive polyimide resin 64 is provided between the lead wires 62 formed on the resin tape substrate 64 to reduce the step between the lead 62 and the tape substrate surface height. This same effect as techniques to avoid creating gaps under the resist for example for plating a dry film resist by providing the first reference in the form of a high liquid material 34 viscosity therebetween leads 32 of FIG. 1 I am aiming.

この実施の形態によれば、リード線62とテープ基材63の段差を少なくするため、リード線62の相互間に感光性のポリイミド樹脂64を含む充填材を設ける方法である。感光性ポリイミド樹脂64のテープ基材63上への形成方法は特定しないが、第1の参考の形態との違いは充填材例えば感光性ポリイミド樹脂64は、金属バンプ形成後も感光性ポリイミド樹脂64の膜を除去しなくても良いことにある。従って感光性ポリイミド形成には、めっき用ドライフィルムレジスト61との密着性の良好な材料を選ぶ必要がある。 According to this embodiment, in order to reduce the level difference between the lead wire 62 and the tape base material 63, a filler including a photosensitive polyimide resin 64 is provided between the lead wires 62. Although the formation method of the photosensitive polyimide resin 64 on the tape base material 63 is not specified, the difference from the first reference embodiment is that the filler, for example, the photosensitive polyimide resin 64 is used even after the metal bumps are formed. This film is not required to be removed. Therefore, it is necessary to select a material having good adhesion to the plating dry film resist 61 for forming the photosensitive polyimide.

以上の実施の形態のように、リード線或はテープ基材とレジストとの間の密着性を高めることで、めっき液の侵入防止ができ、初期に想定した寸法外でバンプが形成されることは無く、結果的に各実施の形態は、バンプの寸法精度向上に寄与することが可能となる。 Thus the implementation of the form, by increasing the adhesion between the lead wire or a tape base material and the resist, it is anti-intrusion of the plating solution initially assumed dimensions outside the bumps are formed As a result, each embodiment can contribute to improvement of the dimensional accuracy of the bump.

本発明にかかる半導体装置およびその製造方法は、テープ樹脂基板に形成したリード線上に、これと対向する形で半導体用チップを接合するために形成するバンプのめっき用マスクのラミネートの密着性を向上させる等の効果を有し、半導体装置およびその製造方法等に有用である。   The semiconductor device and the manufacturing method thereof according to the present invention improve the adhesion of the laminate of the bump plating mask formed for bonding the semiconductor chip on the lead wire formed on the tape resin substrate so as to face the lead wire. It is useful for semiconductor devices and manufacturing methods thereof.

1の参考の形態の半導体装置の製造過程の概略断面図である。It is a schematic sectional drawing of the manufacturing process of the semiconductor device of the 1st reference form. 第2の参考の形態の半導体装置の製造過程の概略断面図である。It is a schematic sectional drawing of the manufacturing process of the semiconductor device of the 2nd reference form. 第3の参考の形態の半導体装置の製造過程の概略断面図である。It is a schematic sectional drawing of the manufacturing process of the semiconductor device of the 3rd reference form. この発明の実施の形態の半導体装置の製造過程の概略断面図である。It is a schematic sectional drawing of the manufacturing process of the semiconductor device of embodiment of this invention . 従来の半導体装置の製造過程の概略断面図である。It is a schematic sectional drawing of the manufacturing process of the conventional semiconductor device. 課題を説明するための半導体装置の製造過程の概略断面図である。It is a schematic sectional drawing of the manufacturing process of the semiconductor device for demonstrating a subject.

符号の説明Explanation of symbols

11 金属バンプ
12 チップ
13 封止樹脂
14 樹脂テープ基材
15 リード線
21 ドライフィルムレジスト
22 リード線
23 樹脂テープ基材
31 ドライフィルムレジスト
32 リード線
33 樹脂テープ基材
34 液状物質
41 ドライフィルムレジスト
42 リード線
43 樹脂テープ基材
51 ドライフィルムレジスト
52 リード線
53 樹脂テープ基材
54 リード線高さ
61 ドライフィルムレジスト
62 リード線
63 樹脂テープ基材
64 感光性ポリイミド樹脂
11 Metal bump 12 Chip 13 Sealing resin 14 Resin tape substrate 15 Lead wire 21 Dry film resist 22 Lead wire 23 Resin tape substrate 31 Dry film resist 32 Lead wire 33 Resin tape substrate 34 Liquid substance 41 Dry film resist 42 Lead Wire 43 Resin tape substrate 51 Dry film resist 52 Lead wire 53 Resin tape substrate 54 Lead wire height 61 Dry film resist 62 Lead wire 63 Resin tape substrate 64 Photosensitive polyimide resin

Claims (2)

表面にリード線が形成された樹脂テープ基材と、前記樹脂テープ基材上の前記リード線間に充填された感光性ポリイミドを含む充填材と、前記リード線および前記充填材上にラミネートするレジストを用いて前記リード線上に形成されたバンプと、前記バンプに電極が接合された半導体チップとを備えた半導体装置。Resin tape base material having a lead wire formed on the surface, a filler containing photosensitive polyimide filled between the lead wires on the resin tape base material, and a resist laminated on the lead wire and the filler A semiconductor device comprising: a bump formed on the lead wire using a semiconductor chip; and a semiconductor chip having an electrode bonded to the bump. 樹脂テープ基材の表面にリード線を形成する工程と、前記リード線間に感光性ポリイミドを含む充填材を充填する工程と、前記充填材の充填された状態で前記リード線上にレジストを貼り付ける工程と、前記レジストをマスクとして前記リード線上に、半導体チップの電極と接合するためのバンプを形成する工程と、前記バンプに半導体チップを接合する工程とを含む半導体装置の製造方法。 A step of forming a lead wire on the surface of the resin tape base, a step of filling a filler containing photosensitive polyimide between the lead wires, and affixing a resist on the lead wire in a state filled with the filler A method of manufacturing a semiconductor device, comprising: a step; forming a bump for bonding to an electrode of a semiconductor chip on the lead wire using the resist as a mask; and bonding a semiconductor chip to the bump .
JP2003398372A 2003-11-28 2003-11-28 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4286640B2 (en)

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