JP2865072B2 - Semiconductor bare chip mounting board - Google Patents
Semiconductor bare chip mounting boardInfo
- Publication number
- JP2865072B2 JP2865072B2 JP8242166A JP24216696A JP2865072B2 JP 2865072 B2 JP2865072 B2 JP 2865072B2 JP 8242166 A JP8242166 A JP 8242166A JP 24216696 A JP24216696 A JP 24216696A JP 2865072 B2 JP2865072 B2 JP 2865072B2
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- semiconductor bare
- board
- build
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体ベアチップ
をプリント基板の表面に実装，封止する半導体ベアチッ
プ実装基板に関し、特に、プリント基板の表面に半導体
ベアチップをフェースダウン実装するとともに、実装し
た半導体ベアチップをとり囲むようにビルドアップ層を
積層して凹部を形成した半導体ベアチップ実装基板に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor bare chip mounting board for mounting and sealing a semiconductor bare chip on a surface of a printed circuit board, and more particularly, to a semiconductor bare chip mounted face-down on a surface of a printed circuit board and mounted. The present invention relates to a semiconductor bare chip mounting substrate having a recess formed by laminating build-up layers so as to surround the substrate.
【０００２】[0002]
【従来の技術】近年、電子機器等のさらなる軽薄短小化
の要望が高まるとともに、高性能化に伴うパッケージＬ
ＳＩの大型化が進展し、これまでのプリント基板の表面
実装技術では、最近の超小型，薄型化した機器に対応し
きれなくなってきた。2. Description of the Related Art In recent years, there has been an increasing demand for further reductions in the size and weight of electronic devices and the like.
As the size of SI has increased, the surface mounting technology of printed circuit boards has become unable to cope with recent ultra-small and thin devices.
【０００３】このため、最近では、ＬＳＩのパッケージ
を省略した半導体ベアチップを、プリント基板の表面に
直接実装し、これを封止樹脂で封止する、いわゆるベア
チップ実装の技術が提案されている。For this reason, recently, a so-called bare chip mounting technique has been proposed, in which a semiconductor bare chip without an LSI package is directly mounted on the surface of a printed circuit board and this is sealed with a sealing resin.
【０００４】ここで、図５を参照して従来の半導体ベア
チップを実装するプリント基板について説明する。図５
は、従来の半導体ベアチップ実装基板を示すもので、
（ａ）は一部断面正面図で、（ｂ）は平面図である。同
図において、１１０は導体を形成したプリント基板であ
り、このプリント基板１１０の表面上に抵抗，コンデン
サ等の部品１５０とともに半導体ベアチップ１２０がベ
アチップ実装されている。Here, a printed circuit board on which a conventional semiconductor bare chip is mounted will be described with reference to FIG. FIG.
Indicates a conventional semiconductor bare chip mounting board,
(A) is a partial cross-sectional front view, and (b) is a plan view. In FIG. 1, reference numeral 110 denotes a printed circuit board on which a conductor is formed, and a semiconductor bare chip 120 is mounted on the surface of the printed circuit board 110 together with components 150 such as resistors and capacitors.
【０００５】ここでベアチップ実装とは、図５に示すよ
うに、裸の半導体ベアチップ１２０をプリント基板１１
０にダイボンディングするとともに、この半導体ベアチ
ップ１２０上の電極とプリント基板１１０上の電極とを
ワイヤ１２１を介してワイヤーボンディングして接続
し、さらに半導体ベアチップ１２０を封止樹脂１３０で
樹脂封止するものである。Here, the bare chip mounting means, as shown in FIG. 5, a bare semiconductor bare chip 120 is mounted on the printed circuit board 11.
0, the electrodes on the semiconductor bare chip 120 and the electrodes on the printed circuit board 110 are connected by wire bonding via wires 121, and the semiconductor bare chip 120 is resin-sealed with a sealing resin 130. It is.
【０００６】ところが、このような従来の半導体ベアチ
ップ実装基板では、半導体ベアチップ１２０を樹脂封止
する際に、封止樹脂１３０の流動性によって半導体ベア
チップ１２０の実装部分の周囲から広範囲にわたって封
止樹脂１３０が流れてしまい、樹脂のコントロール自体
が困難であることから、樹脂塗布領域が不必要に広くな
り過ぎ、プリント基板の高密度実装を阻害するという問
題があった。一方、このような封止樹脂の流出の防止や
コントロールは、チクソ性の高い樹脂を使用することに
よりある程度達成できるが、その結果、樹脂封止の作業
性が悪くなるという問題が生じた。However, in such a conventional semiconductor bare chip mounting board, when the semiconductor bare chip 120 is resin-sealed, the fluidity of the sealing resin 130 causes the sealing resin 130 to cover a wide area from the periphery of the semiconductor bare chip 120 mounting portion. Flow, and it is difficult to control the resin itself, so that the resin application area becomes unnecessarily large, which hinders high-density mounting of a printed circuit board. On the other hand, such prevention and control of the leakage of the sealing resin can be achieved to some extent by using a resin having a high thixotropy, but as a result, there has been a problem that the workability of the resin sealing deteriorates.
【０００７】さらに、このようなプリント基板では、図
５（ａ）の矢印で示すように、半導体ベアチップ１２０
上の電極とプリント基板１１０上の電極をワイヤボンデ
ィングしており、ボンディングワイヤ１２１とこれを封
止する樹脂１３０がプリント基板１１０の上面から高く
盛り上がってしまっていた。このため、このような盛り
上がりが、基板や装置の薄型化を阻害するとともに、例
えば半導体ベアチップの上方にパッケージ部品を追加実
装するような場合、樹脂封止部とパッケージ部品が干渉
してしまい、追加実装が行なえないという事態が生じ
た。Further, in such a printed circuit board, as shown by an arrow in FIG.
The upper electrode and the electrode on the printed circuit board 110 are wire-bonded, and the bonding wire 121 and the resin 130 for sealing the same have risen high from the upper surface of the printed circuit board 110. For this reason, such swelling hinders the thinning of the substrate and the device, and, for example, when a package component is additionally mounted above the semiconductor bare chip, the resin sealing portion and the package component interfere with each other, and the additional There was a situation where implementation was not possible.
【０００８】そこで、これまで、このような従来技術の
不都合を解消するため、図６に示すような半導体ベアチ
ップ実装基板が提案されている。図６は、封止樹脂の流
出を防止する半導体ベアチップ実装基板を示すものであ
り、（ａ）は一部断面正面図で、（ｂ）は平面図であ
る。この図６に示す半導体ベアチップ実装基板は、封止
樹脂２３０の塗布領域を一定に維持するため、プリント
基板２１０上に半導体ベアチップ２２０をとり囲むダム
２４０が形成してある。In order to solve such disadvantages of the prior art, a semiconductor bare chip mounting board as shown in FIG. 6 has been proposed. 6A and 6B show a semiconductor bare chip mounting substrate for preventing the outflow of the sealing resin. FIG. 6A is a partially sectional front view, and FIG. 6B is a plan view. In the semiconductor bare chip mounting board shown in FIG. 6, a dam 240 surrounding the semiconductor bare chip 220 is formed on a printed board 210 in order to keep a coating area of the sealing resin 230 constant.
【０００９】このような半導体ベアチップ実装基板にお
いては、プリント基板２１０上に環状のダム２４０を熱
圧着等により固着し、このダム２４０の内側に半導体ベ
アチップ２２０を配設し、ワイヤ２２１を介してワイヤ
ボンディングした後、ダム２４０内に樹脂２３０を注入
して硬化させるようにしてある。このような半導体ベア
チップ実装基板によれば、ダム２４０によって封止樹脂
２３０の流出が止められるので、樹脂２３０の塗布領域
をダム２４０内の一定範囲に維持することができた。In such a semiconductor bare chip mounting board, an annular dam 240 is fixed on a printed circuit board 210 by thermocompression bonding or the like, and a semiconductor bare chip 220 is provided inside the dam 240, and a wire 221 is connected through a wire 221. After bonding, the resin 230 is injected into the dam 240 and cured. According to such a semiconductor bare chip mounting board, since the outflow of the sealing resin 230 is stopped by the dam 240, the application area of the resin 230 can be maintained within a certain range in the dam 240.
【００１０】また、特開昭６３−２６８２６０号公報に
も、封止樹脂の流出を抑えて半導体ベアチップの樹脂封
止が可能な「混成微少素子回路」が提案されている。図
７は、この特開昭６３−２６８２６０号公報に記載され
た混成微少素子回路を示すものであり、（ａ）は全体斜
視図で、（ｂ）は一部断面正面図である。Japanese Unexamined Patent Publication (Kokai) No. 63-268260 also proposes a "hybrid microelement circuit" capable of suppressing the outflow of the sealing resin and sealing the semiconductor bare chip with resin. FIGS. 7A and 7B show a hybrid microelement circuit described in Japanese Patent Application Laid-Open No. Sho 63-268260. FIG. 7A is an overall perspective view, and FIG.
【００１１】この図７に示すように、この特開昭６３−
２６８２６０号公報に記載された混成微少素子回路は、
部品搭載用の主基板３１１の四方各辺に部品搭載用の副
基板３１２を電気的，機械的に隣接するようほぼ直角に
配設したプリント基板３１０からなり、この主基板３１
１と副基板３１２によって形成される箱状の空間内に封
止樹脂３３０を注入して、主基板３１１に実装された半
導体ベアチップ３２０を封止するものである。[0011] As shown in FIG.
The hybrid microelement circuit described in Japanese Patent Publication No.
A printed circuit board 310 is provided in which sub-boards 312 for component mounting are arranged substantially at right angles so as to be electrically and mechanically adjacent to each side of the main board 311 for mounting components.
The sealing resin 330 is injected into a box-shaped space formed by the substrate 1 and the sub-board 312 to seal the semiconductor bare chip 320 mounted on the main board 311.
【００１２】主基板３１１と副基板３１２の電気的・機
械的接続はフレキシブル基板３１３で行なわれていお
り、部品実装後、主基板３１１に対して四方の副基板３
１２を直角に折曲げて接着剤で貼り合わせて組み立て
る。そして、半導体ベアチップ３２０をワイヤ３２１で
ワイヤボンディングするとともにその他の部品３５０を
実装し、その後、主基板３１１と副基板３１２で形成さ
れた空間に樹脂３３０を流し込むことによって、半導体
ベアチップ３１１や耐湿性の要求される他の部品３５０
を樹脂封止する。The electrical and mechanical connection between the main board 311 and the sub-board 312 is made by a flexible board 313. After mounting the components, the sub-board 3
12 is bent at a right angle and bonded with an adhesive to assemble. Then, the semiconductor bare chip 320 is wire-bonded with the wires 321 and the other components 350 are mounted. Thereafter, the resin 330 is poured into the space formed by the main substrate 311 and the sub-substrate 312, thereby forming the semiconductor bare chip 311 and the moisture-resistant material. Other parts required 350
Is sealed with a resin.
【００１３】このような混成微少素子回路によれば、主
基板３１１と副基板３１２により箱状の空間を形成しそ
の中に封止樹脂３３０を注入するので、封止樹脂３３０
が流出するこなく半導体ベアチップ３２０をプリント基
板３１０の任意の箇所に実装，封止することができる。According to such a hybrid microelement circuit, a box-shaped space is formed by the main substrate 311 and the sub-substrate 312, and the sealing resin 330 is injected into the box-shaped space.
The semiconductor bare chip 320 can be mounted and sealed at an arbitrary position on the printed circuit board 310 without flowing out.
【００１４】[0014]
【発明が解決しようとする課題】しかしながら、このよ
うな従来の半導体ベアチップの封止技術には、以下のよ
うな問題点があった。すなわち、まず図６に示した従来
の半導体ベアチップ実装基板では、樹脂流出防止用のダ
ムをあらかじめプリント基板とは別体に製造しておかな
ければならず、また、そのダムをプリント基板に接着す
る作業が必要となるため、プリント基板の製造に手間や
コストがかかるという問題があった。However, such a conventional semiconductor bare chip sealing technique has the following problems. That is, in the conventional semiconductor bare chip mounting board shown in FIG. 6, a dam for preventing resin outflow must be manufactured separately from the printed board in advance, and the dam is bonded to the printed board. Since work is required, there is a problem that it takes time and cost to manufacture a printed circuit board.
【００１５】また、このような樹脂流出用のダムの小型
化には一定の限界があったため、半導体ベアチップの実
装密度を高くするのも限界があり、特に、半導体ベアチ
ップの面積が小さいような場合、ダムの存在のみで高密
度実装が大きく損なわれるという問題も生じてしまって
いた。Further, since there is a certain limit to the miniaturization of such a resin outflow dam, there is also a limit to increasing the mounting density of the semiconductor bare chips, particularly when the area of the semiconductor bare chips is small. However, the problem that the high-density mounting is greatly impaired by the existence of the dam alone has also arisen.
【００１６】さらに、このようにダムを設ける半導体ベ
アチップ実装基板においても、図６（ａ）の矢印に示す
ように、封止部分はダムの高さまでは盛り上がってしま
うこととなり、図５に示した従来技術が有していた樹脂
が基板面から高く盛り上がるという問題を解消すること
はできなかった。Further, in the semiconductor bare chip mounting board provided with the dam as described above, the sealing portion rises up to the height of the dam as shown by the arrow in FIG. It was not possible to solve the problem that the resin of the prior art rises high from the substrate surface.
【００１７】一方、特開昭６３−２６８２６０号公報記
載の混成微少素子回路では、通常のプリント基板とは異
る四辺が折り畳み式の複雑な構造をとるため、プリント
基板自体の製造コストや組立作業の手間がかかるという
問題があった。さらに、主基板と副基板で作られる箱状
の空間全体に封止樹脂を流し込むため、封止樹脂を必要
以上に使用することとなり、コスト及び重量がさらに増
加するという問題点もあった。On the other hand, in the hybrid micro-element circuit described in Japanese Patent Application Laid-Open No. 63-268260, the four sides different from the ordinary printed circuit board have a complicated structure in which the four sides are folded. There is a problem that it takes time and effort. Furthermore, since the sealing resin is poured into the entire box-shaped space formed by the main substrate and the sub-substrate, the sealing resin is used more than necessary, and the cost and the weight are further increased.
【００１８】なお、このような従来の半導体ベアチップ
実装基板に加えて、図８に示すように、プリント基板４
１０の絶縁層４１１に、ルーターなどによる機械的切削
加工によって凹部４４０を形成し、この凹部４４０に半
導体ベアチップ４２０を配設して接着剤等により固定す
るとともに、プリント基板４１０の配線回路導体４１２
と半導体ベアチップ４２０とをワイヤ４２１によりワイ
ヤボンディングして接続し、最後に、凹部４４０に封止
樹脂４３０を注入して半導体ベアチップ４２０を封止し
て実装するという半導体ベアチップ実装基板も提案され
ている。In addition to the conventional semiconductor bare chip mounting board, as shown in FIG.
A concave portion 440 is formed in the insulating layer 411 of FIG. 10 by mechanical cutting using a router or the like, and a semiconductor bare chip 420 is disposed in the concave portion 440 and fixed with an adhesive or the like.
And a semiconductor bare chip 420 are connected by wire bonding with a wire 421, and finally, a sealing resin 430 is injected into the concave portion 440 to seal and mount the semiconductor bare chip 420. .
【００１９】このような図８に示すプリント基板によれ
ば、切削形成した凹部４４０に半導体ベアチップ４２０
を実装することにより、凹部４４０が封止樹脂４３０の
流れ止めとなるので、従来のような流れ止め用のダム等
を設けることなく、単純な構成のみによって、半導体ベ
アチップ４２０を樹脂封止することが可能であった。According to the printed circuit board shown in FIG. 8, the semiconductor bare chip 420 is formed in the recess 440 formed by cutting.
Is mounted, the concave portion 440 serves as a stopper for the sealing resin 430. Therefore, the semiconductor bare chip 420 can be resin-sealed only with a simple configuration without providing a dam for stopping the flow as in the related art. Was possible.
【００２０】しかし、このプリント基板に凹部を切削形
成するベアチップ実装の技術は、凹部の形成をルーター
などによる機械的切削加工により行なっていため、半導
体ベアチップを接続するプリント基板の内層の配線回路
導体についても機械的に削り出されることとなってい
た。However, in this bare chip mounting technique of forming a concave portion on a printed board, the concave portion is formed by mechanical cutting using a router or the like, so that the wiring circuit conductor in the inner layer of the printed board connecting the semiconductor bare chip is formed. Was also mechanically cut off.
【００２１】一般に、多層プリント基板に配線される配
線回路導体は、厚さ数十ミクロンの銅箔等が用いられて
いる。このため、ルーターなどによる機械的切削では積
層厚みのばらつきや、切削ツールの精密制御の問題等に
より、プリント基板の精度，歩留まりがきわめて悪く、
結果として非常にコストの高いプリント基板となってし
まっていた。Generally, a copper foil or the like having a thickness of several tens of microns is used as a wiring circuit conductor wired on a multilayer printed circuit board. For this reason, the precision and yield of printed circuit boards are extremely poor due to variations in lamination thickness and problems with precision control of cutting tools in mechanical cutting with a router, etc.
The end result was a very expensive printed circuit board.
【００２２】また、このようなプリント基板によって
も、ボンディングワイヤは半導体ベアチップの上方に突
出していたため、図８の矢印に示すように、他の従来技
術と同様、封止樹脂が基板面より高く盛り上がってはみ
だしてしまい、凹部の上方にパッケージ部品を追加実装
した場合、封止部とパッケージ部品が干渉してしまうと
いう事態が依然として生じていた。Also, in such a printed circuit board, since the bonding wires protrude above the semiconductor bare chip, the sealing resin rises higher than the substrate surface as shown in the arrow of FIG. When the package component was additionally mounted above the concave portion, the sealing portion and the package component still interfered with each other.
【００２３】この場合、凹部をさらに深く切削すること
により、封止部とパッケージ部品の接触を回避すること
もできるが、そのようにすると、削り出しによる製品精
度の悪化が進むこととなり、結果として、パッケージ部
品を追加実装するためには、凹部を形成している絶縁層
をより厚くするしかなく、これでは、プリント基板の薄
型化をかえって阻害するという矛盾が生じた。In this case, it is possible to avoid the contact between the sealing portion and the package component by cutting the concave portion further deeply. However, in such a case, the precision of the product is deteriorated due to the cutting, and as a result, However, in order to additionally mount a package component, it is necessary to increase the thickness of the insulating layer forming the concave portion. This causes a contradiction that the thickness of the printed circuit board is hindered.
【００２４】本発明は、このような従来の技術が有する
問題を解決するために提案されたものであり、半導体ベ
アチップをプリント基板の表面に実装，封止する半導体
ベアチップ実装基板において、プリント基板の表面に半
導体ベアチップをフェースダウン実装するとともに、実
装した半導体ベアチップをとり囲むようにビルドアップ
層を積層して凹部を形成することにより、きわめて単純
な構成のみによって簡単に封止樹脂の流出と盛り上がり
を抑制しつつ、プリント基板の精度を維持して信頼度の
高い製品を低コストで確保し、基板の薄型化を図ること
ができる半導体ベアチップ実装基板の提供を目的とす
る。The present invention has been proposed in order to solve such problems of the prior art. In a semiconductor bare chip mounting board for mounting and sealing a semiconductor bare chip on the surface of a printed board, the present invention relates to a printed circuit board. By mounting the semiconductor bare chip face down on the surface and laminating a build-up layer so as to surround the mounted semiconductor bare chip, a recess is formed. It is an object of the present invention to provide a semiconductor bare chip mounting substrate capable of securing a highly reliable product at a low cost while maintaining the precision of a printed circuit board while suppressing the thickness and reducing the thickness of the substrate.
【００２５】[0025]
【課題を解決するための手段】上記目的を達成するため
本発明の請求項１記載の半導体ベアチップ実装基板は、
プリント基板の表面上に形成された凹部と、この凹部内
にフェースダウン実装されて封止樹脂で封止される半導
体ベアチップと、を備え、前記凹部が、実装される前記
半導体ベアチップの周囲を取り囲むように、ビルドアッ
プ工法により積層されたビルドアップ層により形成さ
れ、このビルドアップ工法により形成された凹部に、前
記半導体ベアチップがフェースダウン実装される構成と
してある。In order to achieve the above object, a semiconductor bare chip mounting board according to claim 1 of the present invention comprises:
A recess formed on the surface of the printed circuit board and the inside of the recess
Semiconductor mounted face down on the board and sealed with sealing resin
Body bear chip, wherein the recess is mounted
Build up around the bare semiconductor chip.
Formed by the build-up layer laminated by the
And the recess formed by this build-up method
The semiconductor bare chip is face-down mounted .
【００２６】また、請求項２記載の半導体ベアチップ実
装基板は、前記ビルドアップ層による凹部を前記半導体
ベアチップの高さより高く形成した構成としてある。The semiconductor bare chip mounting board according to the second aspect of the present invention has a configuration in which a recess formed by the build-up layer is formed higher than the height of the semiconductor bare chip.
【００２７】また、請求項３記載の半導体ベアチップ実
装基板は、前記凹部を構成するビルドアップ層を前記プ
リント基板表面に複数積層して形成した構成としてあ
る。Further, the semiconductor bare chip mounting board according to a third aspect of the present invention is configured such that a plurality of build-up layers constituting the concave portion are laminated on the surface of the printed board.
【００２８】さらに、請求項４記載の半導体ベアチップ
実装基板は、前記複数のビルドアップ層のうち上層が下
層より広く上面に開口し、複数のビルドアップ層が段部
を形成する構成としてある。Further, in the semiconductor bare chip mounting board according to a fourth aspect of the present invention, an upper layer of the plurality of build-up layers is opened to the upper surface wider than a lower layer, and the plurality of build-up layers form a step.
【００２９】このような構成からなる本発明の半導体ベ
アチップ実装基板によれば、ビルドアップ基板のビルド
アップ層の厚みを利用して封止樹脂の流出を防止してい
るので、封止樹脂の流出防止用のダムを別体で形成し基
板上に取り付ける作業が一切不要となる上、ダムの実装
面積も不要となり、半導体ベアチップの実装面積を縮小
することが可能となる。According to the semiconductor bare chip mounting board of the present invention having such a configuration, the outflow of the sealing resin is prevented by utilizing the thickness of the build-up layer of the build-up board. There is no need to separately form a dam for prevention and mount it on a substrate. Further, the mounting area of the dam is not required, and the mounting area of the semiconductor bare chip can be reduced.
【００３０】また、半導体ベアチップはプリント基板の
ビルドアップ層にとり囲まれた凹部にフェースダウン実
装してあるので、半導体ベアチップとプリント基板の電
極は半導体ベアチップの底面側において直接接続され、
封止樹脂もこの半導体ベアチップの底面部のみに注入す
れば足りるので、従来のように半導体ベアチップの上面
側にボンディングワイヤや封止樹脂が盛り上がることも
ない。Since the semiconductor bare chip is face-down mounted in a recess surrounded by a build-up layer of the printed board, the semiconductor bare chip and the electrodes of the printed board are directly connected on the bottom side of the semiconductor bare chip,
Since it is sufficient to inject the sealing resin only into the bottom portion of the semiconductor bare chip, the bonding wire and the sealing resin do not swell on the upper surface side of the semiconductor bare chip as in the related art.
【００３１】従って、これによって封止樹脂の高さをプ
リント基板の上面と同一面とすることができ、封止樹脂
がプリント基板の上方に配設される部品等と干渉するこ
とがなくなり、例えば、従来は困難であった半導体ベア
チップの実装部上方に他のパッケージ部品を追加実装す
るようなことも可能となる。Accordingly, the height of the sealing resin can be made flush with the upper surface of the printed circuit board, so that the sealing resin does not interfere with components disposed above the printed circuit board. In addition, it becomes possible to additionally mount another package component above the mounting portion of the semiconductor bare chip, which has been difficult in the past.
【００３２】さらに、本発明の半導体ベアチップ実装基
板によれば、半導体ベアチップをとり囲む凹部を構成す
るビルドアップ層をフォトエッチング技術を用いたビル
ドアップ法により形成してあるので、凹部やプリント基
板の導体形成は非常に簡易かつ確実に行なうことがで
き、プリント基板の製品精度がきわめて高く、歩留まり
の良いプリント基板を得ることができる。Further, according to the semiconductor bare chip mounting substrate of the present invention, since the build-up layer constituting the concave portion surrounding the semiconductor bare chip is formed by the build-up method using the photo-etching technique, the concave portion and the printed board are not formed. Conductor formation can be performed very easily and reliably, and a printed circuit board with extremely high product accuracy and a high yield can be obtained.
【００３３】[0033]
【発明の実施の形態】以下、本発明の半導体ベアチップ
実装基板の一実施形態について、図面を参照して説明す
る。図１〜図４は、それぞれ本発明の半導体ベアチップ
実装基板の一実施形態を示す要部断面正面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor bare chip mounting board according to the present invention will be described below with reference to the drawings. 1 to 4 are cross-sectional front views of an essential part showing one embodiment of a semiconductor bare chip mounting board of the present invention.
【００３４】これらの図に示すように、本実施形態にお
ける半導体ベアチップ実装基板は、プリント基板１０の
表面上に半導体ベアチップ２０を実装し、封止樹脂３０
で封止する半導体ベアチップ実装基板であり、半導体ベ
アチップ２０を基板１０の表面にフェースダウン実装す
るとともに、このフェースダウン実装した半導体ベアチ
ップ２０の周囲をとり囲むように、基板１０の表面にビ
ルドアップ層を積層して凹部４０を形成した構成として
ある。As shown in these figures, the semiconductor bare chip mounting board according to the present embodiment has a semiconductor bare chip 20 mounted on the surface of a printed circuit board 10 and a sealing resin 30.
A semiconductor bare chip mounting substrate sealed with a semiconductor bare chip 20 face-down mounted on the surface of the substrate 10, and a build-up layer on the surface of the substrate 10 so as to surround the periphery of the face-down mounted semiconductor bare chip 20. Are laminated to form a concave portion 40.
【００３５】すなわち、本実施形態の半導体ベアチップ
実装基板１０は、基材となるガラスエポキシ積層板など
の合成樹脂系の硬質性基板１０ａの片面又は両面に、絶
縁層１１と配線回路導体層１２を交互に任意の層だけ積
層した多層プリント基板であり、図１に示す本実施形態
のプリント基板１０は、片面積層の場合である。That is, the semiconductor bare chip mounting board 10 of the present embodiment has an insulating layer 11 and a wiring circuit conductor layer 12 on one or both sides of a synthetic resin-based hard board 10a such as a glass epoxy laminated board as a base material. It is a multilayer printed board in which only arbitrary layers are alternately stacked, and the printed board 10 of the present embodiment shown in FIG. 1 is a single-area layer.
【００３６】そして、この絶縁層１１が、後述するよう
にフェースダウン実装した半導体ベアチップ２０の周囲
をとり囲むようにして基板１０の表面にビルドアップ層
として積層され、凹部４０が形成され、このビルドアッ
プ層により形成され凹部４０に、半導体ベアチップ２０
がフェースダウン実装されるようにしてある。 [0036] Then, the insulating layer 11 is laminated as a build-up layer on the surface of the substrate 10 so as to surrounding the periphery of the semiconductor bare chip 20 was face-down mounting, as described later, the recess 40 is formed, the Birudoa'
The semiconductor bare chip 20 is formed in the recess 40 formed by the semiconductor layer.
Is mounted face down.
【００３７】すなわち、本実施形態にかかる凹部４０
は、フォトエッチング技術を用いたビルドアップ工法に
より形成してある。 具体的には、本実施形態におけるプ
リント基板１０は、凹部４０を形成する絶縁層１１（１
１ａ，１１ｂ）を感光性樹脂により形成してあり、この
感光性樹脂にフォトエッチングを施すことにより凹部４
０を形成してある。 That is, the concave portion 40 according to the present embodiment
Is, in the build-up method using a photo-etching technology
Is formed. Specifically, the printed circuit board 10 according to the present embodiment includes the insulating layer 11 (1
1a and 11b) are formed of a photosensitive resin.
0 is formed.
【００３８】一般に、多層プリント基板は、絶縁層と配
線回路導体とを複数積層して加熱プレスにより一体化
し、その後ツイストドリルを用いてスルーホールを形成
することにより製作されているが、絶縁層を感光性樹脂
により形成するとともに、フォトエッチング法を用いる
ことにより、より高密度，高精度の多層プリント基板を
形成することができる。In general, a multilayer printed board is manufactured by laminating a plurality of insulating layers and wiring circuit conductors, integrating them by a heat press, and then forming through holes using a twist drill. By using a photosensitive resin and using a photo-etching method, a multi-layer printed board with higher density and higher precision can be formed.
【００３９】ここで、感光性樹脂及びフォトエッチング
を用いたビルドアップ工法による本実施形態のプリント
基板１０及び凹部４０の製造方法について説明する。 まず、基材となるガラスエポキシ積層板などの合成樹
脂系の硬質性基板１０ａの全面に、銅箔等の金属箔を接
着した積層基板に、フォトエッチングを施して不要な銅
箔を溶解除去して配線回路導体１２を形成する。 つぎに、この配線回路導体１２を形成した基板面の全
体に絶縁層１１として紫外線硬化型エポキシ樹脂等の感
光性樹脂を被覆し、この感光性樹脂からなる絶縁層１１
に、必要に応じてフォトエッチングにより微小径のスル
ーホール（ビアホール）を形成する。 その後、絶縁層１１を粗面化し、その絶縁層１１の表
面を活性化処理した後、無電解銅メッキ又は電解銅メッ
キ法を併用して金属化するとともに、フォトエッチング
によって配線回路導体１２を形成する。 そして、スルーホールを導通化して上下層の配線回路
導体１２を電気的に接続する。以上の手順を繰り返すこ
とにより、任意の多層を形成したプリント基板１０を製
造することができる。 最後に、プリント基板１０の最上層（又はその下層）
の絶縁層１１にフォトエッチングを施して絶縁層１１の
一部を除去し、所望の凹部４０を形成する。このとき、
凹部４０の底面には、絶縁層１１が除去されたことによ
り、当該絶縁層１１の下層に積層されている配線回路導
体１２が露出する。Here, a method of manufacturing the printed circuit board 10 and the concave portion 40 of this embodiment by a build-up method using a photosensitive resin and photoetching will be described. First, a laminate substrate in which a metal foil such as a copper foil is adhered to the entire surface of a synthetic resin-based hard substrate 10a such as a glass epoxy laminate as a base material is subjected to photoetching to dissolve and remove unnecessary copper foil. To form the wiring circuit conductor 12. Next, a photosensitive resin such as an ultraviolet curable epoxy resin is coated as an insulating layer 11 on the entire surface of the substrate on which the wiring circuit conductor 12 is formed, and the insulating layer 11 made of the photosensitive resin is coated.
Then, through holes (via holes) having a small diameter are formed by photoetching as necessary. After that, the insulating layer 11 is roughened, the surface of the insulating layer 11 is activated, then metallized by using electroless copper plating or electrolytic copper plating together, and the wiring circuit conductor 12 is formed by photoetching. I do. Then, the through holes are made conductive to electrically connect the upper and lower wiring circuit conductors 12. By repeating the above procedure, it is possible to manufacture the printed board 10 on which an arbitrary multilayer is formed. Finally, the uppermost layer (or lower layer) of the printed circuit board 10
Photo-etching is performed on the insulating layer 11 to remove a part of the insulating layer 11 to form a desired concave portion 40. At this time,
By removing the insulating layer 11, the wiring circuit conductor 12 laminated below the insulating layer 11 is exposed on the bottom surface of the concave portion 40.
【００４０】このような方法によりプリント基板１０及
び凹部４０を形成することにより、従来機械的切削加工
により行なっていた、絶縁層１１及び配線回路導体１２
の削り出し作業が一切不要となり、フォトエッチングに
より、簡易かつ高精度に凹部４０の形成が行なえる。こ
れにより、従来問題となっていたプリント基板１０の製
品精度を向上させることができ、歩留まりのよいプリン
ト基板１０を製造することができる。By forming the printed board 10 and the concave portion 40 by such a method, the insulating layer 11 and the wiring circuit conductor 12 which have conventionally been formed by mechanical cutting are used.
No shaving work is required at all, and the concave portion 40 can be formed easily and accurately by photoetching. As a result, it is possible to improve the product accuracy of the printed circuit board 10, which has conventionally been a problem, and to manufacture the printed circuit board 10 with a high yield.
【００４１】なお、この凹部４０は、プリント基板１０
を構成する絶縁層１１のうち、少なくとも最上層に形成
するようにしてあり、本実施形態においては、図１に示
すように、最上層１１ｂのみに凹部４０を形成する場合
の他、図２に示すように、最上層１１ｃ及びその下層１
１ｂの二層にわたって凹部４０を形成することもでき
る。このように複数の絶縁層１１にわたって凹部４０を
形成することにより、凹部の深さを実装される半導体ベ
アチップ１の高さより深くなるように形成することが可
能となる。Note that the recess 40 is
In the present embodiment, as shown in FIG. 1, in addition to the case where the concave portion 40 is formed only in the uppermost layer 11b, FIG. As shown, the uppermost layer 11c and the lower layer 1
The recess 40 may be formed over two layers 1b. By forming the recesses 40 over the plurality of insulating layers 11 in this manner, the recesses can be formed to have a depth greater than the height of the semiconductor bare chip 1 to be mounted.
【００４２】また、凹部４０の形状としては図１〜２に
示すような無段形状とすることもできるが、これ以外に
も、フォトエッチングにより絶縁層１１を自由に除去す
ることで、任意の形状とすることができる。例えば、図
３に示すように、凹部４０が形成された複数の絶縁層１
１のうち、上層の絶縁層１１ｃを下層の絶縁層１１ｂよ
り広く除去することにより、凹部４０に段部を形成する
こともできる。The shape of the concave portion 40 may be a stepless shape as shown in FIGS. 1 and 2. Alternatively, the arbitrary shape may be obtained by freely removing the insulating layer 11 by photoetching. It can be shaped. For example, as shown in FIG.
By removing the upper insulating layer 11c more widely than the lower insulating layer 11b, a step can be formed in the recess 40.
【００４３】そして、本実施形態のプリント基板では、
このようにビルドアップ層でとり囲まれた凹部４０を形
成した後に、この凹部４０内に、半導体ベアチップ２０
をフェースダウン実装するようにしてある。フェースダ
ウン実装とは、ワイヤレスボンディング方式の一つで、
半導体チップ２０の電極部にバンプ２１やビーム状のリ
ードを形成しておき、この面を下側にしてプリント基板
１０の導体層１２に直接面接続する方法であり、代表的
のものにフリップチップ方式がある。[0043] Then, the printed board of the present embodiment,
Thus, the recess 40 surrounded by the build-up layer is formed.
After the formation , the semiconductor bare chip 20 is
The are to be face-down mounting. Face-down mounting is one of the wireless bonding methods.
In this method, bumps 21 and beam-shaped leads are formed on the electrode portion of the semiconductor chip 20 and the surface is turned downward, and the surface is directly connected to the conductor layer 12 of the printed circuit board 10. There is a method.
【００４４】このフェースダウン方式によれば、通常の
ワイヤ方式と異なり、電極数に関係なく一度に強固なボ
ンディングができるとともに、封止樹脂３０も半導体ベ
アチップ２０の底面部のみに注入すれば足りるので、凹
部４０に封止樹脂３０を注入しても、従来のように上方
にワイヤや樹脂封止が盛り上がることがなくなる。According to the face-down method, unlike the ordinary wire method, strong bonding can be performed at once regardless of the number of electrodes, and it is sufficient to inject the sealing resin 30 only into the bottom portion of the semiconductor bare chip 20. Even if the sealing resin 30 is injected into the recess 40, the wires and the resin sealing do not swell upward as in the conventional case.
【００４５】これによって、例えば図４に示すように、
凹部４０に実装された半導体ベアチップ１の封止樹脂４
は、封止部分がプリント基板１０から盛り上がらずプリ
ント基板１０の上面と同一平面かそれ以下になるので、
従来は困難であった封止された凹部４０を跨いだ状態で
の、パッケージＬＳＩ５０などの他の部品をプリント基
板１０に追加して表面実装することができる。Thus, for example, as shown in FIG.
Sealing resin 4 of semiconductor bare chip 1 mounted in recess 40
Since the sealing portion does not rise from the printed circuit board 10 and is flush with the upper surface of the printed circuit board 10 or less,
Other components such as the package LSI 50 can be added to the printed circuit board 10 and surface-mounted while straddling the sealed recess 40, which has been difficult in the past.
【００４６】このように本実施形態の半導体ベアチップ
実装基板によれば、ビルドアップ基板のビルドアップ層
の厚みを利用して封止樹脂の流出を防止しているので、
封止樹脂の流出防止ダムを別体で形成し基板上に取り付
ける作業が一切不要となる上、ダムの実装面積も不要で
あるため、半導体ベアチップの実装面積を縮小すること
が可能となる。As described above, according to the semiconductor bare chip mounting board of the present embodiment, the outflow of the sealing resin is prevented by utilizing the thickness of the build-up layer of the build-up board.
The work of forming the sealing resin outflow prevention dam as a separate body and attaching it to the substrate is not required at all, and the mounting area of the dam is not required. Therefore, the mounting area of the semiconductor bare chip can be reduced.
【００４７】また、半導体ベアチップをプリント基板の
ビルドアップ層にとり囲まれた面にフェースダウン実装
してあるので、半導体ベアチップとプリント基板の電極
はベアチップ底面側で直接接続され、封止樹脂もベアチ
ップ底面部のみに注入すれば足りるので、従来のように
ベアチップ上面にボンディングワイヤや封止樹脂が、盛
り上がることもない。Also, since the semiconductor bare chip is mounted face down on the surface of the printed circuit board surrounded by the build-up layer, the semiconductor bare chip and the electrodes of the printed circuit board are directly connected on the bare chip bottom side, and the sealing resin is also formed on the bare chip bottom surface. Since it suffices to inject into only the portion, the bonding wire and the sealing resin do not swell on the upper surface of the bare chip as in the related art.
【００４８】これによって、封止樹脂の高さをプリント
基板の上面と同一面とすることができ、封止樹脂がプリ
ント基板の上方に配設される物と干渉することがなくな
り、例えば、従来は困難であった半導体ベアチップの実
装部上方に他のパッケージ部品を追加実装することも可
能となる。As a result, the height of the sealing resin can be made flush with the upper surface of the printed circuit board, so that the sealing resin does not interfere with objects disposed above the printed circuit board. It becomes possible to additionally mount another package component above the mounting portion of the semiconductor bare chip, which has been difficult.
【００４９】さらに、本発明の半導体ベアチップ実装基
板によれば、半導体ベアチップをとり囲む凹部を構成す
るビルドアップ層をフォトエッチングによるビルドアッ
プ法により形成してあるので、凹部やプリント基板の導
体形成を簡易かつ確実に行なうことができ、プリント基
板の製品精度がきわめて高く、歩留まりの良いプリント
基板を得ることができる。Further, according to the semiconductor bare chip mounting board of the present invention, since the build-up layer constituting the recess surrounding the semiconductor bare chip is formed by the photo-etching build-up method, the formation of the recess and the conductor of the printed board is not required. This can be performed simply and reliably, and a printed circuit board with extremely high product accuracy and a high yield can be obtained.
【００５０】[0050]
【発明の効果】以上説明したように本発明の半導体ベア
チップ実装基板によれば、半導体ベアチップをプリント
基板の表面に実装，封止する半導体ベアチップ実装基板
において、プリント基板の表面に半導体ベアチップをフ
ェースダウン実装するとともに、実装した半導体ベアチ
ップをとり囲むようにビルドアップ層を積層して凹部を
形成することで、樹脂封止の流出を防止するダム部を簡
易かつ確実に形成することができ、製品精度を高く維持
することができると同時に、フェースダウン実装によっ
て樹脂封止の盛り上がりも防止することができ基板全体
の薄型化を図ることも可能となり、これによって、例え
ば半導体ベアチップの上方にも自由にパッケージ部品を
追加実装するようなこともできる。As described above, according to the semiconductor bare chip mounting board of the present invention, in a semiconductor bare chip mounting board for mounting and sealing a semiconductor bare chip on the surface of a printed circuit board, the semiconductor bare chip is face down on the surface of the printed circuit board. By mounting and building up the build-up layer so as to surround the mounted semiconductor bare chip to form a recess, it is possible to easily and reliably form a dam part that prevents leakage of resin encapsulation. At the same time, it is also possible to prevent swelling of resin encapsulation by face-down mounting and to reduce the thickness of the entire substrate, thereby enabling free packaging, for example, above the semiconductor bare chip. It is also possible to mount additional components.
【図１】本発明の半導体ベアチップ実装基板の一実施形
態を示す要部断面正面図である。FIG. 1 is a cross-sectional front view of an essential part showing one embodiment of a semiconductor bare chip mounting board of the present invention.
【図２】本発明の半導体ベアチップ実装基板の一実施形
態を示す要部断面正面図である。FIG. 2 is a cross-sectional front view of an essential part showing one embodiment of a semiconductor bare chip mounting board of the present invention.
【図３】本発明の半導体ベアチップ実装基板の一実施形
態を示す要部断面正面図である。FIG. 3 is a cross-sectional front view of an essential part showing one embodiment of a semiconductor bare chip mounting board of the present invention.
【図４】本発明の半導体ベアチップ実装基板の一実施形
態を示す要部断面正面図である。FIG. 4 is a cross-sectional front view of a main part showing one embodiment of a semiconductor bare chip mounting board of the present invention.
【図５】従来の半導体ベアチップ実装基板を示すもの
で、（ａ）は一部断面正面図で、（ｂ）は平面図であ
る。5A and 5B show a conventional semiconductor bare chip mounting board, in which FIG. 5A is a partially sectional front view, and FIG. 5B is a plan view.
【図６】従来の他の半導体ベアチップ実装基板を示すも
ので、（ａ）は一部断面正面図で、（ｂ）は平面図であ
る。6A and 6B show another conventional semiconductor bare chip mounting substrate, in which FIG. 6A is a partial cross-sectional front view, and FIG. 6B is a plan view.
【図７】従来の他の半導体ベアチップ実装基板を示すも
ので、（ａ）は全体斜視図で、（ｂ）は一部断面正面図
である。7A and 7B show another conventional semiconductor bare chip mounting board, in which FIG. 7A is an overall perspective view, and FIG. 7B is a partial cross-sectional front view.
【図８】従来の他の半導体ベアチップ実装基板を示す一
部断面正面図である。FIG. 8 is a partial cross-sectional front view showing another conventional semiconductor bare chip mounting substrate.
【符号の説明】 １０ プリント基板 ２０ 半導体ベアチップ ３０ 封止樹脂 ４０ 凹部[Description of Signs] 10 Printed circuit board 20 Semiconductor bare chip 30 Sealing resin 40 Depression
Claims (4)
と、 この凹部内にフェースダウン実装されて封止樹脂で封止
される半導体ベアチップと、を備え、 前記凹部が、実装される前記半導体ベアチップの周囲を
取り囲むように、ビルドアップ工法により積層されたビ
ルドアップ層により形成され、 このビルドアップ工法により形成された凹部に、前記半
導体ベアチップがフェースダウン実装されることを特徴
とする半導体ベアチップ実装基板。 1. A recess formed on a surface of a printed circuit board.
And mounted face down in this recess and sealed with sealing resin
A semiconductor bare chip to be mounted, wherein the concave portion is provided around the semiconductor bare chip to be mounted.
Enclosed via-building method to surround
Formed by a build-up layer, and into the recess formed by the build-up method,
It is characterized in that the conductor bare chip is mounted face down
Semiconductor bare chip mounting board.
導体ベアチップの高さより高く形成した請求項１記載の
半導体ベアチップ実装基板。2. The semiconductor bare chip mounting substrate according to claim 1, wherein a recess formed by said build-up layer is formed higher than a height of said semiconductor bare chip.
記プリント基板表面に複数積層して形成した請求項１又
は２記載の半導体ベアチップ実装基板。3. The semiconductor bare chip mounting board according to claim 1, wherein a plurality of build-up layers constituting said recess are laminated on the surface of said printed board.
下層より広く上面に開口し、複数のビルドアップ層が段
部を形成する請求項３記載の半導体ベアチップ実装基
板。4. The semiconductor bare chip mounting board according to claim 3, wherein an upper layer of the plurality of build-up layers has an opening on an upper surface wider than a lower layer, and the plurality of build-up layers form a step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8242166A JP2865072B2 (en) | 1996-09-12 | 1996-09-12 | Semiconductor bare chip mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8242166A JP2865072B2 (en) | 1996-09-12 | 1996-09-12 | Semiconductor bare chip mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1092968A JPH1092968A (en) | 1998-04-10 |
| JP2865072B2 true JP2865072B2 (en) | 1999-03-08 |
Family
ID=17085320
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8242166A Expired - Fee Related JP2865072B2 (en) | 1996-09-12 | 1996-09-12 | Semiconductor bare chip mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2865072B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6442043B1 (en) | 1999-08-11 | 2002-08-27 | Fujikura Limited | Chip assembly module of bump connection type using a multi-layer printed circuit substrate |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3560599B2 (en) | 2002-04-26 | 2004-09-02 | 松下電器産業株式会社 | Electronic circuit device |
| JP4437014B2 (en) * | 2003-04-25 | 2010-03-24 | パナソニック株式会社 | Electronic circuit equipment |
| CN1767406B (en) * | 2004-10-28 | 2010-06-16 | Tdk株式会社 | High frequency module |
| JP5210839B2 (en) * | 2008-12-10 | 2013-06-12 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
-
1996
- 1996-09-12 JP JP8242166A patent/JP2865072B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6442043B1 (en) | 1999-08-11 | 2002-08-27 | Fujikura Limited | Chip assembly module of bump connection type using a multi-layer printed circuit substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1092968A (en) | 1998-04-10 |
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