JP4388834B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a stacked semiconductor package in which a plurality of semiconductor chips are three-dimensionally mounted on a wiring board.

  In order to improve the mounting density of semiconductor packages, various stacked packages in which a plurality of semiconductor chips are three-dimensionally mounted on a wiring board have been proposed. For example, a semiconductor package in which a system is configured by mounting a memory chip and a microcomputer chip on a wiring board is also referred to as a system in package (SiP).

  System-in-packages include memory chips such as DRAM (Dynamic Random Access Memory) and non-volatile memory (flash memory) and a high-speed microprocessor (MPU: Micro Processing Unit) in a single resin package. It is sealed and has a higher function than a memory module in which a memory chip is sealed with resin, and is in great demand.

  In particular, in a mobile communication device such as a mobile phone, a multi-function and downsizing of a semiconductor device is required. Therefore, the system in package is suitable for such a device.

For example, Patent Document 1 discloses a semiconductor device in which a microcomputer chip (2C) in which a high-speed microprocessor is formed is stacked on two memory chips, a chip in which a DRAM is formed and a chip in which a flash memory is formed. ing.
International Publication Number WO 02/103793 A1 (FIG. 2)

  A system-in-package used for small communication mobile devices such as mobile phones has been a challenge to meet the conflicting demands of high functionality and miniaturization. In order to meet such demands, it is necessary to reduce the size of the wiring board on which the semiconductor chip is mounted and to increase the density of the wiring and through-hole pitch. It has been.

  The build-up substrate is formed by using a multilayer wiring substrate manufactured by a subtractive method or the like as a core layer and alternately laminating insulating films and conductive films above and below the core layer. For example, a polyimide resin film is formed as an insulating film on the core layer, and vias (connection holes) are formed in the polyimide resin film on the wiring formed in the core layer using a photolithography technique or a laser. Then, for example, a copper film is formed as a conductor layer on the polyimide resin film including the inside of the via by using a plating method or the like, and then the copper film is processed to form a wiring. Alternatively, a wiring groove may be formed in advance, and a copper film may be formed therein by plating or the like to form a wiring.

  The build-up substrate manufactured in this way can form fine vias and forms a conductor layer at a fine pitch compared to an existing multilayer wiring substrate manufactured by a subtractive method or the like. There is an advantage that you can.

  However, the manufacturing process of the build-up substrate is complicated compared to an existing manufacturing method such as a subtractive method, so that the manufacturing cost becomes high, and a system-in-package using the manufacturing process becomes expensive.

  An object of the present invention is to provide a small and highly functional semiconductor package at low cost.

  Another object of the present invention is to improve the reliability and manufacturing yield of a semiconductor package using a wiring board having a higher wiring and through-hole pitch.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device of the present invention includes a multilayer wiring board in which a plurality of leads formed on the main surface and a plurality of ball lands formed on the back surface are electrically connected via a plurality of through-through holes, and the main surface A semiconductor chip mounted on and electrically connected to the plurality of leads via wires; and external connection terminals connected to the plurality of ball lands; and a pattern of the plurality of leads The plurality of ball land patterns are arranged so as to overlap each other.

  The semiconductor device of the present invention is laminated between a first outer layer substrate on which a plurality of leads are formed, a second outer layer substrate on which a plurality of ball lands are formed, and the first outer layer substrate and the second outer layer substrate. And the plurality of leads and the plurality of ball lands are electrically connected via a plurality of through-holes penetrating the first outer layer substrate, the inner layer substrate, and the second outer layer substrate. A multilayer wiring board, a semiconductor chip mounted on the first outer layer board and electrically connected to the plurality of leads via wires, and external connection terminals connected to the plurality of ball lands. Among the plurality of through holes formed in the multilayer wiring board, a through hole disposed in an outermost peripheral portion of the multilayer wiring board is a wiring formed in the first outer layer substrate or the second Outside Connect seen electrically the formed ball lands, said inner layer substrate formed inner wiring is obtained by so as not to electrically connect.

  The semiconductor device of the present invention includes a multilayer wiring board in which a plurality of leads formed on the main surface and a plurality of ball lands formed on the back surface are electrically connected via a plurality of through-through holes, and the main surface A plurality of semiconductor chips mounted on the semiconductor chip and electrically connected to the plurality of leads via wires; external connection terminals connected to the plurality of ball lands; and the plurality of leads formed on the main surface. A plurality of wirings electrically connected to each of the wirings, and a solder resist covering the surfaces of the plurality of wirings and having the surfaces of the plurality of leads opened, and orthogonal to the extending direction of the wires. The angle between the direction and the opening end of the solder resist in the region intersecting with the wire is smaller than the angle between one side of the semiconductor chip and the opening end.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Even without using an expensive build-up board, it is possible to increase the density of conductor layer patterns and through-holes on the wiring board. Therefore, semiconductor devices that are small and require high functionality, such as system-in-package, can be used. It can be provided at low cost.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is a plan view of a main part of the semiconductor device of the present embodiment, FIG. 2 is a cross-sectional view of the main part of the semiconductor device shown in FIG. 1, and FIG. 3 is a main part of the back surface of the semiconductor device shown in FIG. It is a top view. In FIG. 1, some members (mold resin, solder resist, bonding wire, etc.) are not shown in order to make it easier to see the pattern of the conductor layer formed on the wiring board. Similarly, in FIG. 3, illustration of a part of the member (solder resist) is omitted.

  The semiconductor device according to the present embodiment is a semiconductor package in which two semiconductor chips 2A and 2B are mounted on the main surface of the wiring substrate 1 and these semiconductor chips 2A and 2B are sealed with a mold resin 3. The semiconductor chip 2A is mounted on the main surface of the wiring substrate 1 via an adhesive 4, and the semiconductor chip 2B is stacked on the main surface of the semiconductor chip 2A via the adhesive 4. A plurality of bonding pads BP are formed on the main surfaces of the semiconductor chips 2A and 2B. The leads 5 and bonding pads BP formed on the main surface of the wiring board 1 are connected via Au (gold) wires 6. Are electrically connected. The lead 5 is formed integrally with the wiring 7 and constitutes a part of the wiring 7. The wiring 7 is electrically connected to the ball land 9 or the wiring 7 on the back surface of the wiring board 1 through a through hole 8 penetrating the wiring board 1. Solder bumps 13 constituting external connection terminals of the semiconductor device are connected to the surface of the ball land 9.

  As shown in FIG. 2, the main surface of the wiring board 1 is covered with a solder resist 10 except for the region where the leads 5 are formed. Similarly, the back surface of the wiring board 1 is also covered with the solder resist 10 except for the region where the ball lands 9 are formed. An inner layer wiring 11 is formed inside the wiring substrate 1, and a plating layer 12 made of Cu (copper) or the like is formed inside the through hole 8.

  Of the two semiconductor chips 2A and 2B, the semiconductor chip 2A is a silicon chip on which a DRAM (Dynamic Random Access Memory) which is a kind of memory LSI is formed, and the semiconductor chip 2B is formed on the semiconductor chip 2A. This is a silicon chip on which a microcomputer (microcomputer) for controlling the DRAM is formed. Such a semiconductor package in which a system is configured by mounting a memory chip and a microcomputer chip for controlling the memory chip on one wiring board 1 is called a system in package (SiP).

  In the semiconductor device of the present embodiment, the wiring board 1 is composed of a four-layer board shown in FIGS. 4 is a main part plan view of the first outer layer substrate 1A constituting the uppermost layer of the wiring board 1, and FIG. 5 is a main part plan view of the first inner layer substrate 1B located under the first outer layer board 1A. 6 is a plan view of the main part of the second inner layer substrate 1C located below the first inner layer substrate 1B. FIG. 7 is a second outer layer substrate constituting the lower layer of the second inner layer substrate 1C, that is, the lowermost layer of the wiring substrate 1. It is a principal part top view of 1D.

  On the surface of the first outer layer substrate 1A shown in FIG. 4, that is, on the main surface of the wiring substrate 1, the above-described lead 5, wiring 7, and solder resist 10 (not shown) are formed. Inner layer wirings 11 are formed on the surface of the first inner layer substrate 1B shown in FIG. 5 and the surface of the second inner layer substrate 1C shown in FIG. On the front surface of the second outer layer substrate 1D shown in FIG. 7, that is, on the back surface of the wiring substrate 1, the above-described ball land 9, the wiring 7, and the solder resist 10 (not shown) are formed. The through holes 8 formed in the wiring board 1 all pass through four layers of substrates (first outer layer substrate 1A, first inner layer substrate 1B, second inner layer substrate 1C, second outer layer substrate 1D). A plating layer 12 not shown in FIG. 4 to FIG.

  The wiring substrate 1 according to the present embodiment configured by the four layers of the substrates (the first outer layer substrate 1A, the first inner layer substrate 1B, the second inner layer substrate 1C, and the second outer layer substrate 1D) is obtained by a known subtractive method. It was produced. In order to produce the wiring board 1 by the subtractive method, for example, a laminated board (copper-clad laminated board) made of a general-purpose resin such as a glass epoxy resin with a Cu foil attached to the surface is prepared, and the Cu foil is first etched. By forming conductor layer patterns (lead 5, wiring 7, ball land 9, internal wiring 11, etc.), four types of substrates (first outer layer substrate 1A, first inner layer substrate 1B, second layer) having different conductor layer patterns are formed. An inner layer substrate 1C and a second outer layer substrate 1D) are produced. Next, after laminating these substrates and fixing them with an adhesive, a drill is used to form through-holes 8 that penetrate the four-layer substrate, and then an electroless Cu plating layer is formed inside the through-holes 8. To do. Next, after forming an electrolytic Au plating layer on the surface of each of the lead 5 and the wiring 7 formed on the first outer layer substrate 1A and the ball land 9 and the wiring 7 formed on the second outer layer substrate 1D, the lead 5 The solder resist 10 is formed on the surface of the first outer layer substrate 1A excluding the region where the ball land 9 is formed and on the surface of the second outer layer substrate 1B excluding the region where the ball land 9 is formed. The subtractive method is a method that has been used for manufacturing a wiring board for a long time, and has an advantage that the wiring board can be manufactured at low cost.

  8 shows the arrangement of the leads 5 formed on the main surface of the wiring substrate 1 (the surface of the first outer layer substrate 1A) and the ball land 9 formed on the back surface of the wiring substrate 1 (the surface of the second outer layer substrate 1D). It is the top view which showed arrangement | positioning superimposed. Here, in order to make it easy to see the arrangement of both, the illustration of the wiring 7 formed on the main surface of the wiring substrate 1 is omitted, and the lead 5 is shown in black.

  As shown in FIG. 8 and FIG. 2, the wiring board 1 of the present embodiment is arranged so that the leads 5 and the ball lands 9 overlap each other. Thus, by arranging the ball land 9 almost directly below the lead 5, the signal path from the lead 5 on the main surface of the wiring board 1 to the ball land 9 on the back surface through the through hole 8 can be minimized. . This makes it possible to minimize the length and number of wirings 7 formed on the main surface and the back surface of the wiring board 1, thereby reducing the pitch of the through holes 8 and reducing the external dimensions of the wiring board 1. Can do.

  As shown in FIGS. 5 and 6, the wiring substrate 1 according to the present embodiment includes the wiring substrate 1 (first outer layer substrate 1A, first inner layer substrate 1B, second inner layer substrate 1C, second outer layer substrate 1D. ) Of the through-holes 8 that pass through the inner-layer wiring 11 formed on the first inner-layer substrate 1B and the inner-layer wiring formed on the second inner-layer substrate 1C. 11 is not electrically connected. That is, the through hole 8 arranged in the outermost peripheral portion of the wiring substrate 1 is connected only to the conductor layers (wiring 7 and ball land 9) of the first outer layer substrate 1A and the second outer layer substrate 1D.

  As described above, when the wiring substrate 1 is manufactured by the subtractive method, the four-layer substrates (the first outer layer substrate 1A, the first inner layer substrate 1B, the second inner layer substrate 1C, and the like) on which different conductor layer patterns are formed. A second outer layer substrate 1D) is laminated, and a through hole 8 penetrating these substrates is formed using a drill. At this time, since the conductor layer (wiring 7 and ball land 9) formed on the first outer layer substrate 1A and the second outer layer substrate 1D can be visually recognized from the outside, the conductor layer (wiring 7 and ball land 9) and the through hole 8 Alignment is easy. On the other hand, since the conductor layer (inner layer wiring 11) formed on the first inner layer substrate 1B and the second inner layer substrate 1C cannot be visually recognized from the outside, alignment with the through hole 8 is difficult.

  Therefore, in order to prevent positional displacement between the inner layer wiring 11 and the through hole 8, the inner layer wiring 11a connected to the through hole 8 (the portion of the inner layer wiring 11 surrounding the through hole 8; see FIGS. 5 and 6). The diameter needs to be large enough. That is, the diameter of the inner layer wiring 11a in the portion connected to the through hole 8 needs to be larger than the conductive layer pattern in the portion connected to the through hole 8 of the conductor layer of the first outer layer substrate 1A or the second outer layer substrate 1D. There is. For example, in the wiring substrate 1 of the present embodiment, the diameter of the inner layer wiring 11a is 350 μm, whereas the diameter of the conductive layer pattern surrounding the through hole 8 not connected to the inner layer wiring 11 is 280 μm.

  Therefore, for example, when an alignment margin between the outermost through hole 8 and the outer peripheral edge of the wiring board 1 is required to be 150 μm, the conductor layer pattern having a diameter of 280 μm (radius 140 μm) is centered from the outer peripheral edge of the wiring board 1. 150 + 140 = 290 μm must be placed inside. On the other hand, in the case of the inner layer wiring 11 a having a diameter of 350 μm (radius 175 μm), the center thereof must be arranged inside the outer peripheral end of the wiring board 1 by 175 + 140 = 315 μm. In other words, when viewed from the distance from the center of the wiring substrate 1 to the outermost through hole 8, the inner layer wiring 11a having a diameter of 350 μm (radius 175 μm) is connected to the conductor having a diameter of 280 μm (radius 140 μm) not connected to the inner layer wiring 11. If an attempt is made to arrange at the same position as the layer pattern, in order to secure an alignment margin between the through hole 8 and the outer peripheral edge of the wiring board 1 of 150 μm, the distance from the center of the wiring board 1 to the outer peripheral edge is 315−290 = It must be increased by 25 μm.

  In this way, by arranging a conductor layer pattern having a small diameter that is not connected to the inner layer wiring 11 on the outermost peripheral portion of the wiring substrate 1, the wiring substrate 1 can be reduced in size.

  FIG. 9 is a principal plan view showing the opening shape of the solder resist 10 formed on the main surface of the wiring board 1, and FIG. 10 is a partial enlarged view of FIG. In FIG. 9, illustration of the Au wire 6 is omitted.

  The solder resist 10 is formed to insulate and protect the wiring 7 formed on the main surface of the wiring substrate 1, but the surface of the lead 5 to which one end of the Au wire 6 is bonded needs to be removed. is there. At this time, if a part of the lead 5 is covered with the solder resist 10 due to misalignment between the lead 5 and the opening end 10 </ b> A of the solder resist 10, the exposed area of the lead 5 becomes small and bonding of the Au wire 6 becomes difficult. . Accordingly, the opening end 10A of the solder resist 10 needs to be separated from the lead 5 by an amount corresponding to at least the misalignment amount. However, when the opening end 10A of the solder resist 10 is separated from the lead 5, the end of the wiring 7 connected to the lead 5 is exposed. Therefore, as the distance from the opening end 10A to the lead 5 increases, the end of the wiring 7 increases. As a result, the exposed area of the Au wire 6 bonded to the lead 5 comes into contact with the end of the wiring 7 and the risk of short-circuiting increases.

  Therefore, in the present embodiment, as shown in the drawing, the direction of the opening end 10A in the region intersecting with the Au wire 6 in the opening end 10A of the solder resist 10 is set to the one side of the lead 5 intersecting with the Au wire 6. Make it almost parallel to the direction. Thereby, since the exposed area of the edge part of the wiring 7 can be kept to the minimum, generation | occurrence | production of the defect which the Au wire 6 and the wiring 7 short-circuit can be suppressed. On the other hand, for example, as shown in FIG. 11, the direction of the opening end 10A of the solder resist 10 in the region intersecting with the Au wire 6 is made substantially parallel to the direction of one side of the wiring board 1 (or one side of the semiconductor chip 2B). In this case, since the exposed area of the end portion of the wiring 7 is increased, there is a high risk that the Au wire 6 and the wiring 7 are short-circuited.

  It should be noted that since the height from the surface of the wiring 7 to the Au wire 6 is sufficiently high in a region away from the lead 5 to some extent, it does not come into contact with the Au wire 6 even if the wiring 7 is exposed. On the other hand, in the region where the wiring 7 is closest to the lead 5, that is, at the end portion of the wiring 7, the height from the surface of the wiring 7 to the Au wire 6 is low, so there is a high risk that both of them are short-circuited. That is, in order to suppress short-circuit defects between the Au wire 6 and the wiring 7, the exposed end area of the wiring 7 can be minimized by forming the opening end 10A of the solder resist 10 as described above. It is valid.

  The direction of the opening end 10A of the solder resist 10 in the region intersecting with the Au wire 6 does not necessarily have to be parallel to the direction of one side of the lead 5 intersecting with the Au wire 6, but the end of the wiring 7 is closer to parallel. The exposed area can be reduced. Then, at least the angle formed between the direction orthogonal to the extending direction of the Au wire 6 and the opening end 10A of the solder resist 10 is made smaller than the angle between one side of the semiconductor chip 2B and the opening end, or at least the Au wire. It is desirable that an angle formed between one side of the lead 5 intersecting with 6 and the opening end 10A of the solder resist 10 facing the one side is smaller than an angle between one side of the semiconductor chip 2B and the opening end.

  As described above, the lead 5 on the main surface of the wiring board 1 and the ball land 9 on the back surface are arranged so as to overlap each other, and the through hole 8 arranged on the outermost periphery of the wiring board 1 is electrically connected to the inner layer wiring 11. By avoiding connection, it is possible to increase the pattern density of the conductor layer and the through hole 8 formed on the wiring board 1 and reduce the outer dimensions of the wiring board 1 without using an expensive build-up board. Therefore, a small and highly functional system in package can be provided at low cost.

  Further, according to the present embodiment, it is possible to suppress a short-circuit defect between the Au wire and the wiring, thereby improving the reliability of the system-in-package and the manufacturing yield.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the inner substrate is a two-layer wiring substrate, but the inner substrate can be applied to a wiring substrate having one layer or three or more layers.

  The semiconductor device of the present invention is particularly useful when applied to miniaturization of system-in-package.

It is a principal part top view which shows the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device shown in FIG. 1. FIG. 2 is a main part plan view showing a back surface of the semiconductor device shown in FIG. 1. FIG. 2 is a plan view of a principal part showing a first outer layer substrate of the wiring substrate shown in FIG. 1. FIG. 2 is a plan view of a principal part showing a first inner layer substrate of the wiring board shown in FIG. 1. FIG. 3 is a plan view of a principal part showing a second inner layer substrate of the wiring substrate shown in FIG. 1. It is a principal part top view which shows the 2nd outer layer board | substrate of the wiring board shown in FIG. FIG. 2 is a plan view of a principal part showing an arrangement of leads and ball lands formed on the wiring board shown in FIG. 1. FIG. 2 is a plan view of a principal part showing an opening shape of a solder resist formed on the main surface of the wiring board shown in FIG. 1. FIG. 10 is a partially enlarged plan view of FIG. 9. It is a partial enlarged plan view which shows the comparative example of the opening shape of a soldering resist.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board | substrate 1A 1st outer layer board | substrate 1B 1st inner layer board | substrate 1C 2nd inner layer board | substrate 1D 2nd outer layer board | substrate 2A, 2B Semiconductor chip 3 Mold resin 4 Adhesive 5 Lead 6 Au wire 7 Wiring 8 Through hole 9 Ball land 10 Solder resist 10A Open end 11, 11a Inner layer wiring 12 Plating layer 13 Solder bump BP Bonding pad

Claims (7)

(A) major surface, a first semiconductor chip having a second bonding pad formed on the first bonding pads formed on the main surface, and said major surface,
(B) a main provided with a first lead, a first main surface wiring electrically connected to the first lead, a second lead, and a second main surface wiring electrically connected to the second lead; A surface-side substrate, a first ball land corresponding to the first lead, a first back surface wiring electrically connected to the first ball land and formed to overlap the first main surface wiring; A second ball land corresponding to the second lead, and a second back surface wiring electrically connected to the second ball land, and a back side substrate located on the opposite side of the main surface side substrate; corresponding to the second lead, the second main surface interconnection and the first inner layer wiring formed at a position planarly overlapping, and being the first inner wiring electrically connected, corresponding to the second ball lands, A second inner layer formed at a position overlapping the second back surface wiring in a planar manner Line is provided, and the inner layer side substrate located between the rear substrate and the main surface side substrate, a first through hole provided between the first back surface wiring and the first main surface interconnect a second through hole provided between the front Stories second main surface line and the first inner wiring, and a third through hole provided between the second back side wiring and the second inner wiring and the multilayer wiring substrate having a,
(C) a first wire connecting the first bonding pad of the first semiconductor chip and the first lead of the multilayer wiring board; and the second bonding pad of the first semiconductor chip and the second lead of the multilayer wiring board. A second wire connecting the
(D) a mold resin for sealing the first semiconductor chip, the first wire, and the second wire;
(E) a first external connection terminal provided on the first ball land of the multilayer wiring board, and a second external connection terminal provided on the second ball land of the multilayer wiring board;
Including
The first semiconductor chip is mounted on the main surface side substrate of the multilayer wiring board,
The diameters of the first inner layer wiring and the second inner layer wiring are larger than the respective diameters of the first main surface wiring , the first back surface wiring , the second main surface wiring, and the second back surface wiring. The
The diameter of the second through hole is smaller than the diameter of the first inner layer wiring,
The diameter of the third through hole, wherein a smaller Ikoto than the diameter of said second inner wiring.   The semiconductor device according to claim 1, wherein the multilayer wiring board is formed by a subtractive method.   2. The semiconductor device according to claim 1, wherein a second semiconductor chip having a larger number of bonding pads than that of the first semiconductor chip is mounted on a main surface of the first semiconductor chip. A third through hole is provided between the second back surface wiring and the second inner layer wiring;
2. The semiconductor device according to claim 1, wherein the diameter of the second inner layer wiring is larger than the diameter of each of the first main surface wiring and the first back surface wiring.   4. The semiconductor device according to claim 3, wherein the first semiconductor chip is a semiconductor chip on which a memory LSI is formed, and the second semiconductor chip is a semiconductor chip on which a microcomputer is formed. The first ball land is provided at a position overlapping the first lead in a plane.
2. The semiconductor device according to claim 1, wherein the second ball land is provided at a position overlapping the second lead in a planar manner. (A) a first semiconductor chip having a main surface and a first bonding pad formed on the main surface;
(B) a first lead, a main surface side substrate provided with a first main surface wiring electrically connected to the first lead, a first ball land corresponding to the first lead, and the first ball land. A first back surface wiring that is electrically connected to the first main surface wiring, and is provided on the opposite side of the main surface side substrate; the first lead; and Corresponding to the first ball land, electrically connected to the first inner layer wiring and the first inner layer wiring formed in a position overlapping with the first main surface wiring, and corresponding to the second ball land. A second inner layer wiring formed at a position overlapping with the first back surface wiring in a plane, an inner layer side substrate positioned between the main surface side substrate and the back surface side substrate, and the first main surface A first through hole provided between a wiring and the first inner layer wiring; and And the multilayer wiring substrate having a second through-hole provided between the two inner wiring first backside interconnect,
(C) a first wire connecting the first bonding pad of the first semiconductor chip and the first lead of the multilayer wiring board;
(D) a mold resin for sealing the first semiconductor chip and the first wire;
(E) a first external connection terminal provided on the first ball land of the multilayer wiring board;
Including
The first semiconductor chip is mounted on the main surface side substrate of the multilayer wiring board,
The diameters of the first inner layer wiring and the second inner layer wiring are larger than the diameters of the first main surface wiring and the first back surface wiring,
The diameter of the first through hole is smaller than the diameter of the first inner layer wiring,
A diameter of the second through hole is smaller than a diameter of the second inner layer wiring.