JP5400094B2 - Semiconductor package and mounting method thereof - Google Patents

Semiconductor package and mounting method thereof Download PDF

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JP5400094B2
JP5400094B2 JP2011124482A JP2011124482A JP5400094B2 JP 5400094 B2 JP5400094 B2 JP 5400094B2 JP 2011124482 A JP2011124482 A JP 2011124482A JP 2011124482 A JP2011124482 A JP 2011124482A JP 5400094 B2 JP5400094 B2 JP 5400094B2
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electromagnetic shielding
shielding layer
substrate
alignment mark
mother substrate
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JP2012253190A (en
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守謙 徐
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力成科技股▲分▼有限公司
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    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/3025—Electromagnetic shielding

Description

本発明は、半導体パッケージ及びその実装方法に関する。   The present invention relates to a semiconductor package and a mounting method thereof.

半導体チップは微小型電子部品であり、実装されても電磁干渉（ＥＭＩ）に起因し、チップ演算異常や電気機能劣化を招くおそれが有り、特にチップの演算頻度が高くなればなるほどＥＭＩの影響を受け易い。従来のＥＭＩから保護する１つの技術は、チップを密封する封止体の外表面に電磁遮蔽層（若しくはＲＦ遮蔽層と呼ばれる）の被覆を与える。しかしながら、良好な遮蔽効率に達するため電磁遮蔽層は有効に接地連結されなければいけない。また、封止体は電気絶縁性材料であるので、電磁遮蔽層の接地連結は基板の特殊接地構造と特殊実装プロセスを利用してなされることで、実装コストがあがる。   A semiconductor chip is a small electronic component, and even if it is mounted, it may be caused by electromagnetic interference (EMI), leading to abnormal chip calculation or deterioration of electrical function. Especially, the higher the calculation frequency of the chip, the more the influence of EMI. Easy to receive. One technique for protecting against conventional EMI provides a coating of an electromagnetic shielding layer (or called an RF shielding layer) on the outer surface of the encapsulant that seals the chip. However, the electromagnetic shielding layer must be effectively grounded to reach good shielding efficiency. Further, since the sealing body is made of an electrically insulating material, the grounding connection of the electromagnetic shielding layer is performed using a special grounding structure of the substrate and a special mounting process, thereby increasing the mounting cost.

米国特許第７３４２３０３Ｂ１号明細書（特許文献１）に電磁遮蔽層を接地連結させる半導体技術を開示し、実装工程ではマルチライン半切断操作が必要であり、基板の分割ライン位置に半切断可能のメッキスルーホールを予め製造することも必須である。図１に示した従来の方法により製造し得た半導体パッケージは、特殊接地構造と厚み増加の基板ユニット１１３を含む。基板ユニット１１３の側辺に露出する半切断可能なメッキスルーホール１１７を形成し、基板ユニット１１３の上にチップ１２０を設置し、ボンディングワイヤ１２２を介してチップ１２０を基板ユニット１１３に電気接続し、さらに封止体１３０でチップ１２０を密封する。封止体１３０の表面に電磁遮蔽層１５２として導電塗布層が形成され、基板ユニット１１３の下方に複数のボンディングボール１６０を形成する。   U.S. Pat. No. 7,342,303 B1 (Patent Document 1) discloses a semiconductor technology in which an electromagnetic shielding layer is connected to the ground, and a multi-line semi-cutting operation is required in the mounting process, and plating that can be semi-cut at the division line position of the substrate. It is also essential to manufacture the through holes in advance. The semiconductor package manufactured by the conventional method shown in FIG. 1 includes a special ground structure and a substrate unit 113 having an increased thickness. A semi-cuttable plated through hole 117 exposed on the side of the substrate unit 113 is formed, the chip 120 is placed on the substrate unit 113, and the chip 120 is electrically connected to the substrate unit 113 via the bonding wires 122. Further, the chip 120 is sealed with the sealing body 130. A conductive coating layer is formed as an electromagnetic shielding layer 152 on the surface of the sealing body 130, and a plurality of bonding balls 160 are formed below the substrate unit 113.

図２に示すように、個片化分割前の実装過程において、複数の基板ユニット１１３は１つのマザー基板１１０内に構成される。電磁遮蔽層１５２形成前、半切断ステップを実施しなければいけない。それは分割ラインを沿って上方からメッキスルーホール１１７の一部を除去するまで封止体１３０を切り、形成した半切断溝１４０の深さは封止体１３０の厚みより大きく、全体厚みの三分の二以上であり、かつマザー基板１１０の一部が切り捨てられるため、マザー基板１１０の搭載能力が足りなくなる。また、マザー基板１１０の厚みを封止体１３０の厚みより大きくするべき、即ちメッキスルーホール１１７の十分な半切断露出面積を提供し、そうでなければ、メッキスルーホール１１７は順調に電磁遮蔽層１５２に被覆連結されることができない。よって、従来の電磁遮蔽層１５２は片面被覆形態であり、かつマザー基板において特殊接地連結構造及び半切断後に十分な支持強度が提供できる厚みを有することが必須である。   As shown in FIG. 2, the plurality of board units 113 are configured in one mother board 110 in the mounting process before dividing into individual pieces. Before the electromagnetic shielding layer 152 is formed, a half-cutting step must be performed. That is, the sealing body 130 is cut from above along the dividing line until a part of the plated through hole 117 is removed, and the depth of the formed semi-cut groove 140 is larger than the thickness of the sealing body 130, which is one third of the total thickness. And a part of the mother board 110 is cut off, so that the mounting capacity of the mother board 110 becomes insufficient. In addition, the thickness of the mother substrate 110 should be larger than the thickness of the sealing body 130, that is, a sufficient half-cut exposed area of the plated through hole 117 is provided. Otherwise, the plated through hole 117 can smoothly perform the electromagnetic shielding layer. 152 cannot be sheathed. Therefore, it is essential that the conventional electromagnetic shielding layer 152 has a single-sided coating form and has a thickness that can provide sufficient support strength after the special ground connection structure and half-cutting in the mother substrate.

米国特許第７３４２３０３Ｂ１号明細書US Pat. No. 7,342,303 B1

上記問題を解決するため、本発明の主な目的は、マザー基板の接地連結構造と厚みを変える必要が無い半導体パッケージ及びその実装方法を提供することである。   In order to solve the above problems, a main object of the present invention is to provide a semiconductor package that does not require a change in thickness and thickness of a ground connection structure of a mother board, and a mounting method thereof.

本発明のもう１つの目的は、より優れる側面電磁遮蔽効果を有し、両面電磁遮蔽層を形成した半導体パッケージ及びその実装方法を提供することである。   Another object of the present invention is to provide a semiconductor package having a better side electromagnetic shielding effect and having a double-sided electromagnetic shielding layer and a mounting method thereof.

上述目的を達するため、本発明による半導体実装方法は、以下のステップを含む。上表面および下表面を有し、複数の基板ユニットおよび複数の基板ユニットの間における複数の分割ラインを備えるマザー基板を提供し、下表面に位置する基板ユニットの角隅に接地連結の位置合わせマークを形成するステップ。基板ユニットの上に複数のチップを設置するステップ。マザー基板の上表面に封止体を形成して複数の基板ユニットと複数の分割ラインとを連続被覆するステップ。マザー基板の下表面に、複数の分割ラインに沿って、少なくともマザー基板を貫通する複数の半切断溝を形成するステップ。位置合わせマークを被覆連結するように、マザー基板の下表面と半切断溝とに第一電磁遮蔽層をパターン化形成するステップ。複数の分割ラインに沿って封止体を個片化分割して複数の基板ユニットを複数の半導体パッケージに分離するステップ。個片化分離した半導体パッケージの封止体の頂面と複数の分割側面とに、第一電磁遮蔽層と連結する第二電磁遮蔽層を形成するステップ。
本発明はさらに上述実装方法により製造し得た半導体パッケージを開示する。 In order to achieve the above object, a semiconductor mounting method according to the present invention includes the following steps. A mother board having an upper surface and a lower surface and having a plurality of substrate units and a plurality of dividing lines between the plurality of substrate units is provided, and a ground connection alignment mark is provided at a corner of the substrate unit located on the lower surface Forming steps. Installing a plurality of chips on the substrate unit; Forming a sealing body on the upper surface of the mother substrate to continuously cover the plurality of substrate units and the plurality of dividing lines; Forming a plurality of semi-cut grooves that penetrate at least the mother substrate along a plurality of dividing lines on a lower surface of the mother substrate; Patterning the first electromagnetic shielding layer on the lower surface of the mother substrate and the half-cut groove so as to cover and connect the alignment marks; Separating the plurality of substrate units into a plurality of semiconductor packages by dividing the sealing body into pieces along a plurality of dividing lines. Forming a second electromagnetic shielding layer connected to the first electromagnetic shielding layer on a top surface and a plurality of divided side surfaces of the sealed package of the semiconductor package separated into pieces;
The present invention further discloses a semiconductor package manufactured by the mounting method described above.

上述半導体実装方法において、位置合わせマークは、三角形であり、一つの基板ユニットに一つのみが形成される。
上述半導体実装方法において、第一電磁遮蔽層は、位置合わせマークを完全に被覆し、位置合わせマークに一致する形状でマザー基板の下表面に形成される。 In the semiconductor mounting method described above, the alignment mark is triangular, and only one is formed on one substrate unit.
In the semiconductor mounting method described above, the first electromagnetic shielding layer completely covers the alignment mark and is formed on the lower surface of the mother substrate in a shape that matches the alignment mark.

上述半導体実装方法において、マザー基板の下表面に複数の外接パッドを設置する。複数の外接パッドは第一電磁遮蔽層に被覆されない。半導体実装方法は、上述第一電磁遮蔽層のパターン化形成ステップの後かつ上述封止体の個片化分割ステップの前、複数の外接パッドに複数のボンディングボールを設置するステップを含んでよい。   In the semiconductor mounting method described above, a plurality of circumscribed pads are installed on the lower surface of the mother substrate. The plurality of circumscribed pads are not covered with the first electromagnetic shielding layer. The semiconductor mounting method may include a step of installing a plurality of bonding balls on a plurality of circumscribed pads after the patterning and forming step of the first electromagnetic shielding layer and before the dividing and dividing step of the sealing body.

上述半導体実装方法において、上述封止体個片化分割の切断間隙は、対応する半切断溝の幅から第一電磁遮蔽層の二倍の厚みを引いた値より小さく、即ち半切断溝の側辺に位置する第一電磁遮蔽層を保留する。   In the above-described semiconductor mounting method, the cutting gap of the above-mentioned sealing body singulation division is smaller than a value obtained by subtracting twice the thickness of the first electromagnetic shielding layer from the width of the corresponding half-cut groove, that is, on the side of the half-cut groove The first electromagnetic shielding layer located on the side is reserved.

上述半導体実装方法において、半切断溝の深さはマザー基板の厚みと同じまたはマザー基板の厚みより大きく、封止体の厚みより小さい。
上述技術により、本発明による半導体パッケージ及びその実装方法は以下の利点と効果とを有する。 In the semiconductor mounting method described above, the depth of the half-cut groove is the same as the thickness of the mother substrate or larger than the thickness of the mother substrate and smaller than the thickness of the sealing body.
With the above technique, the semiconductor package and the mounting method thereof according to the present invention have the following advantages and effects.

一、本発明による半導体パッケージは、マザー基板の下表面に形成された半切断溝、半切断溝内で連結される第一電磁遮蔽層と第二電磁遮蔽層、および第一電磁遮蔽層に被覆されるマザー基板の位置合わせマークを備える。これにより、マザー基板の接地連結構造と厚みを変える必要が無い。   1. The semiconductor package according to the present invention covers a semi-cut groove formed on a lower surface of a mother substrate, a first electromagnetic shielding layer and a second electromagnetic shielding layer connected in the half-cut groove, and a first electromagnetic shielding layer. A mother board alignment mark is provided. This eliminates the need to change the ground connection structure and thickness of the mother board.

二、マザー基板の下表面に形成された半切断溝、及び両面形成した第一電磁遮蔽層と第二電磁遮蔽層とは半切断溝内で連結することにより、より優れる側面電磁遮蔽効果を有する。   Second, the semi-cut groove formed on the lower surface of the mother substrate, and the first electromagnetic shielding layer and the second electromagnetic shielding layer formed on both sides have a better side electromagnetic shielding effect by connecting in the half-cut groove. .

従来の半導体パッケージを示す断面図である。It is sectional drawing which shows the conventional semiconductor package. 従来の半導体パッケージを示す断面図である。It is sectional drawing which shows the conventional semiconductor package. 本発明の第一実施例による半導体実装方法において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting method by the 1st Example of this invention. 本発明の第一実施例による半導体実装方法において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting method by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装過程において、各ステップを示す断面図である。It is sectional drawing which shows each step in the semiconductor mounting process by the 1st Example of this invention. 本発明の第一実施例による半導体実装方法において、マザー基板の下表面を示す図である。In the semiconductor mounting method by the 1st Example of this invention, it is a figure which shows the lower surface of a mother board | substrate. 本発明の第一実施例による半導体実装方法により製造し得た半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package manufactured by the semiconductor mounting method by the 1st Example of this invention. 図５の半導体パッケージを示す斜視図である。FIG. 6 is a perspective view showing the semiconductor package of FIG. 5. 本発明の第二実施例による半導体実装方法により製造した半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package manufactured by the semiconductor mounting method by the 2nd Example of this invention.

以下、本発明による半導体パッケージ及びその実装方法を図面に基づいて説明する。
しかしながら、図面においては、本発明の基本構成や実施方法を示す概略図であり、本発明に係る要素と構成だけを示し、実際に実施する部材の数、外形、寸法を一定の比率で記載するものではなく、説明の便宜及び明確性のために簡略または誇張されておる。一方、実際に使われる数、外形、寸法は様々な設計に応じ、部材の配置はより複雑になる可能性がある。 Hereinafter, a semiconductor package and a mounting method thereof according to the present invention will be described with reference to the drawings.
However, in the drawings, it is a schematic diagram showing the basic configuration and implementation method of the present invention, showing only the elements and configuration according to the present invention, and describing the number, outline, and dimensions of members actually implemented at a certain ratio. Rather, they are simplified or exaggerated for convenience and clarity of explanation. On the other hand, the number, shape, and dimensions actually used depend on various designs, and the arrangement of members may be more complicated.

（第一実施例）
本発明の第一実施例による半導体パッケージ及びその実装方法を、例を挙げて図３Ａ〜３Ｉに示す各ステップを示す断面図で説明し、各ステップについては以下に詳細に説明する。 (First Example)
The semiconductor package and its mounting method according to the first embodiment of the present invention will be described with reference to cross-sectional views showing the steps shown in FIGS. 3A to 3I by way of examples, and each step will be described in detail below.

先ず、図３Ａと図４に示すように、マザー基板２１０を提供し、マザー基板２１０は上表面２１１と下表面２１２とを有する。マザー基板２１０は、棒状印刷回路基板または棒状軟性回路基板であり、内部には単層または多層の線路構造を有する。上表面２１１はチップ設置に用いられ、下表面２１２は半導体パッケージの外接表面マウンティングの表面である。下表面２１２にマトリクス状に配列される複数の外接パッド２１６を設置する。マザー基板２１０は、複数の基板ユニット２１３および複数の基板ユニット２１３の間における複数の分割ライン２１４を備える。基板ユニット２１３は半導体パッケージのチップキャリアとして使用され、個片化分割工程において分割ライン２１４は所定除去区域である。下表面２１２に位置する基板ユニット２１３の角隅に接地連結の位置合わせマーク２１５を形成し、位置合わせマーク２１５は表面マウンティング時に外接パッド２１６の位置確認または修正として使用される。   First, as shown in FIGS. 3A and 4, a mother substrate 210 is provided, and the mother substrate 210 has an upper surface 211 and a lower surface 212. The mother board 210 is a bar-shaped printed circuit board or a bar-shaped flexible circuit board, and has a single-layer or multilayer line structure inside. The upper surface 211 is used for chip placement, and the lower surface 212 is the surface of the circumscribing surface mounting of the semiconductor package. A plurality of circumscribed pads 216 arranged in a matrix are installed on the lower surface 212. The mother substrate 210 includes a plurality of substrate units 213 and a plurality of dividing lines 214 between the plurality of substrate units 213. The substrate unit 213 is used as a chip carrier of the semiconductor package, and the dividing line 214 is a predetermined removal area in the dividing and dividing step. Grounding-connected alignment marks 215 are formed at corners of the substrate unit 213 positioned on the lower surface 212, and the alignment marks 215 are used as position confirmation or correction of the circumscribed pad 216 during surface mounting.

製造上において、位置合わせマーク２１５と外接パッド２１６とは同一線路層に形成される。位置合わせマーク２１５の接地連結は、一般の基板設計によりメッキ線或は/又は基板ユニット内部の既存スルーホールを介して基板内部の接地層または接地パッドに連結し、かつ位置合わせマーク２１５の表面上にメッキ層、例えばＮｉ／Ａｕ（図示せず）層を形成する。図４に示すように、位置合わせマーク２１５は、三角形であればより好ましい、一つの基板ユニット２１３に一つのみが形成される。即ち各基板ユニット２１３は一つの位置合わせマーク２１５のみを有し、かつ位置合わせマーク２１５の位置が固定される。よって、位置合わせマーク２１５は、テストまたは表面マウンティング過程において第一端子（Ｐｉｎ １）の位置合わせに使用され、外接パッド２１６（或は外接端子）の配列順序と表面マウンティング方向とを確定することができる。   In manufacturing, the alignment mark 215 and the circumscribed pad 216 are formed in the same line layer. A ground connection of the alignment mark 215 is connected to a ground layer or a ground pad inside the substrate through a plated wire and / or an existing through hole inside the substrate unit according to a general substrate design, and on the surface of the alignment mark 215. A plating layer, for example, a Ni / Au (not shown) layer is formed on the substrate. As shown in FIG. 4, only one alignment mark 215 is preferably formed on one substrate unit 213, which is more preferably a triangle. That is, each substrate unit 213 has only one alignment mark 215 and the position of the alignment mark 215 is fixed. Therefore, the alignment mark 215 is used for the alignment of the first terminal (Pin 1) in the test or surface mounting process, and can determine the arrangement order and the surface mounting direction of the circumscribed pad 216 (or circumscribed terminal). it can.

そして、チップ設置ステップを実施する。図３Ｂに示すように、基板ユニット２１３の上に複数のチップ２２０を設置し、ダイアタッチ材を利用してチップ２２０をマザー基板２１０の上表面２１１に貼り付ける。本実施例において、チップ２２０と基板ユニット２１３とをワイヤボンディングで電気接続し、チップ設置ステップの後にワイヤボンディングで形成した複数のボンディングワイヤ２２２を利用してチップ２２０に位置するボンディングパッド２２１と基板ユニット２１３とを接続する。他の実施例において、チップと基板ユニットとの間の電気接続は、フリップチップ接続またはシリコンスルーホールの導電柱接続であってもよく、チップ設置ステップの過程において、チップ２２０の突起または導電柱を基板ユニット２１３に結合させる。また、チップ２２０は半導体ウエハーから個片化分割されたものであり、内部には様々な集積回路或は光主動素子、例えばＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ Ｓｐｅｃｉｆｉｃ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）、メモリ或はロジック素子を有する。また、各基板ユニット２１３の上に一つのチップを設置すると限らず、機能、サイズが同様または異なる複数のチップを設置し、マルチチップ実装またはシステム実装をしてもよい。   And a chip | tip installation step is implemented. As shown in FIG. 3B, a plurality of chips 220 are installed on the substrate unit 213, and the chips 220 are attached to the upper surface 211 of the mother substrate 210 using a die attach material. In this embodiment, the chip 220 and the substrate unit 213 are electrically connected by wire bonding, and the bonding pad 221 and the substrate unit located on the chip 220 are utilized by using a plurality of bonding wires 222 formed by wire bonding after the chip installation step. 213 is connected. In other embodiments, the electrical connection between the chip and the substrate unit may be a flip chip connection or a silicon through-hole conductive column connection, and during the chip installation step, the protrusions or conductive columns of the chip 220 are connected. The substrate unit 213 is coupled. The chip 220 is divided into individual pieces from a semiconductor wafer, and has various integrated circuits or optical main driving elements such as an ASIC (Application Specific Integrated Circuit), a memory, or a logic element. In addition, a single chip is not necessarily installed on each substrate unit 213, and a plurality of chips having the same or different functions and sizes may be installed to perform multichip mounting or system mounting.

そして、封止ステップを実施する。図３Ｃに示すように、マザー基板２１０の上表面２１１に封止体２３０を形成して基板ユニット２１３と分割ライン２１４とを連続被覆する。封止体２３０は、モールド成形からなるものであり、例えば移送成形モールド或は圧縮成形モールドにより形成される。封止ステップはいわゆるモールドアレイプロセス（Ｍｏｌｄ Ａｒｒａｙ Ｐｒｏｃｅｓｓ、 ＭＡＰ）である。封止体２３０の材質は、無機充填材と顔料を含む電気絶縁性熱硬化樹脂であり、一般にモールド成形の封止体のＥＭＣ（Ｅｐｏｘｙ Ｍｏｌｄｉｎｇ Ｃｏｍｐｏｕｎｄ）である。印刷または他の方式に比べ、モールド成形した封止体２３０は平坦度が比較的高い頂面２３１を有する。   Then, a sealing step is performed. As shown in FIG. 3C, a sealing body 230 is formed on the upper surface 211 of the mother substrate 210 to continuously cover the substrate unit 213 and the dividing line 214. The sealing body 230 is formed by molding, and is formed by, for example, a transfer molding mold or a compression molding mold. The sealing step is a so-called mold array process (MAP). The material of the sealing body 230 is an electrically insulating thermosetting resin containing an inorganic filler and a pigment, and is generally EMC (Epoxy Molding Compound) of a molded sealing body. Compared with printing or other methods, the molded sealing body 230 has a top surface 231 having a relatively high flatness.

そして、封止体２３０成形した後に半切断ステップを実施する。切り深さは封止体２３０とマザー基板２１０との合計厚みの二分の一を超えない。図３Ｄに示すように、ダイシング工具２７１を利用しマザー基板２１０の下表面２１２から複数の半切断溝２４０を形成する。半切断溝２４０は、分割ライン２１４に沿って形成され、かつ少なくともマザー基板２１０を貫通する。半切断溝２４０の深さは、マザー基板２１０の厚みより小さくならなくてよく、封止体２３０の厚みより小さく、封止体２３０とマザー基板２１０との合計厚みの二分の一以下である。よって、上述半切断ステップの後から個片化分割ステップの前まで、チップ２２０は封止体２３０に密封されて分散しない。なお、半切断ステップにおいて形成された半切断溝２４０の幅Ｗは分割ライン２１４の幅より大きい。   Then, after the sealing body 230 is formed, a half-cutting step is performed. The cutting depth does not exceed one half of the total thickness of the sealing body 230 and the mother substrate 210. As shown in FIG. 3D, a plurality of half-cut grooves 240 are formed from the lower surface 212 of the mother substrate 210 using a dicing tool 271. The semi-cut groove 240 is formed along the dividing line 214 and penetrates at least the mother substrate 210. The depth of the semi-cut groove 240 does not have to be smaller than the thickness of the mother substrate 210, is smaller than the thickness of the sealing body 230, and is less than or equal to one-half of the total thickness of the sealing body 230 and the mother substrate 210. Therefore, the chip 220 is sealed in the sealing body 230 and is not dispersed from after the half-cutting step to before the singulation division step. Note that the width W of the half-cut groove 240 formed in the half-cut step is larger than the width of the dividing line 214.

そして、図３Ｅと３Ｆに示すように、位置合わせマーク２１５を被覆連結するようにマザー基板２１０の下表面２１２に第一電磁遮蔽層２５１をパターン化形成し、第一電磁遮蔽層２５１はさらに半切断溝２４０内に形成される。図３Ｅに示すように、フォトレジスト層２８０は、下表面２１２に予め形成され、露光と現像された後に下表面２１２の外接パッド２１６を被覆し、位置合わせマーク２１５を露出させる。或は、カバーで外接パッド２１６を被覆し、マザー基板２１０の下表面２１２に設置された外接パッド２１６が第一電磁遮蔽層２５１に被覆されないようにする。そして、図３Ｆに示すように、フォトレジスト層２８０またはカバーの被覆範囲以外の表面に、第一電磁遮蔽層２５１をパターン化形成し、その後、フォトレジスト層２８０またはカバーを除去する。第一電磁遮蔽層２５１は、耐ＥＭＩ金属であり、スパッタ、蒸着、化学メッキ、物理気相成長、印刷或はスプレーなどの方式を利用して形成されることができる。第一電磁遮蔽層２５１は、さらに伸びて半切断溝２４０の側辺２４１を被覆する。それにより、基板ユニット２１３の核心層が露出することを避け及び側方向の電磁遮蔽効果をあげることができる。   3E and 3F, the first electromagnetic shielding layer 251 is patterned and formed on the lower surface 212 of the mother substrate 210 so as to cover and connect the alignment mark 215. It is formed in the cutting groove 240. As shown in FIG. 3E, a photoresist layer 280 is pre-formed on the lower surface 212, and after exposure and development, covers the circumscribing pad 216 on the lower surface 212 to expose the alignment mark 215. Alternatively, the circumscribed pad 216 is covered with a cover so that the first electromagnetic shielding layer 251 does not cover the circumscribed pad 216 installed on the lower surface 212 of the mother substrate 210. Then, as shown in FIG. 3F, the first electromagnetic shielding layer 251 is formed by patterning on the surface outside the covered area of the photoresist layer 280 or the cover, and then the photoresist layer 280 or the cover is removed. The first electromagnetic shielding layer 251 is an EMI-resistant metal and can be formed using a method such as sputtering, vapor deposition, chemical plating, physical vapor deposition, printing, or spraying. The first electromagnetic shielding layer 251 further extends to cover the side 241 of the semi-cut groove 240. Thereby, it is possible to avoid exposing the core layer of the substrate unit 213 and to increase the side electromagnetic shielding effect.

図６に示すように、第一電磁遮蔽層２５１は、位置合わせマーク２１５を完全に被覆し、位置合わせマーク２１５に一致する形状で下表面２１２に形成されることが好ましい。これにより、位置合わせマーク２１５の位置合わせ効果を保留することができる。   As shown in FIG. 6, the first electromagnetic shielding layer 251 is preferably formed on the lower surface 212 in a shape that completely covers the alignment mark 215 and matches the alignment mark 215. Thereby, the alignment effect of the alignment mark 215 can be suspended.

本実施例において、上述第一電磁遮蔽層２５１のパターン化形成ステップの後かつ個片化分割ステップの前、実装方法はさらにボール設置ステップを含む。図３Ｇに示すように、外接パッド２１６に複数のボンディングボール２６０を設置し、ボールプレースメント（ｂａｌｌ ｐｌａｃｅｍｅｎｔ）法及びリフロー法、或は、ボンディング材印刷法及びリフロー法を利用しボンディングボール２６０を外接パッド２１６の上に結合させる。ボンディングボール２６０は、半導体パッケージが表面マウンティングする時の外接端子として使用される。   In this embodiment, the mounting method further includes a ball installation step after the patterning and forming step of the first electromagnetic shielding layer 251 and before the dividing and dividing step. As shown in FIG. 3G, a plurality of bonding balls 260 are installed on the circumscribed pad 216, and the bonding balls 260 are circumscribed by using a ball placement method and a reflow method, or a bonding material printing method and a reflow method. Bond on pad 216. The bonding ball 260 is used as an external terminal when the semiconductor package is surface-mounted.

そして、個片化分割ステップを実施する。図３Ｇと３Ｈに示すように、ダイシング工具２７２を利用して分割ライン２１４を沿って封止体２３０を個片化分割し、基板ユニット２１３を複数の半導体パッケージに分離させる。ここで、切断幅はダイシング工具２７２の切り幅より小さく、分割ライン２１４の幅に等しい。より好ましい場合、図３Ｈ、３Ｅおよび３Ｆを参照し、上述個片化分割された封止体の切断間隙Ｓは、対応する半切断溝２４０の幅Ｗから第一電磁遮蔽層２５１二倍の厚み２Ｔを引いた値より小さい。これにより、半切断溝２４０の側辺２４１に位置する第一電磁遮蔽層２５１を保留することができる。本ステップにおいて、分割された封止体２３０は複数の分割側面２３２を有する。   Then, the singulation division step is performed. As shown in FIGS. 3G and 3H, the dicing tool 272 is used to divide the sealing body 230 into pieces along the dividing line 214, thereby separating the substrate unit 213 into a plurality of semiconductor packages. Here, the cutting width is smaller than the cutting width of the dicing tool 272 and equal to the width of the dividing line 214. In a more preferable case, referring to FIGS. 3H, 3E, and 3F, the cutting gap S of the sealing body divided into pieces as described above is twice the thickness of the first electromagnetic shielding layer 251 from the width W of the corresponding half-cut groove 240. It is smaller than the value obtained by subtracting 2T. Thereby, the 1st electromagnetic shielding layer 251 located in the side 241 of the semi-cut groove 240 can be suspended. In this step, the divided sealing body 230 has a plurality of divided side surfaces 232.

最後に、図３Ｉに示すように、分割された半導体パッケージの封止体２３０の頂面２３１と分割側面２３２とに第二電磁遮蔽層２５２を形成し、第二電磁遮蔽層２５２はさらに半切断溝２４０の側辺２４１で第一電磁遮蔽層２５１と連結する。第二電磁遮蔽層２５２は、第一電磁遮蔽層２５１と同様な材質及び形成方法で形成され、第一電磁遮蔽層２５１を経由して位置合わせマーク２１５に連結され、接地連結する。第一電磁遮蔽層２５１と第二電磁遮蔽層２５２との組合は、チップ２２０により優れる電磁遮蔽効果を提供することができる。マザー基板２１０の接地連結構造と厚みを特別設計する或は変える必要が無く、実装過程において図３Ｄに示す半切断ステップから図３Ｈに示す個片化分割ステップまで、封止体２３０は依然有効にチップを搭載することができる。   Finally, as shown in FIG. 3I, a second electromagnetic shielding layer 252 is formed on the top surface 231 and the divided side surface 232 of the divided semiconductor package sealing body 230, and the second electromagnetic shielding layer 252 is further semi-cut. The side 241 of the groove 240 is connected to the first electromagnetic shielding layer 251. The second electromagnetic shielding layer 252 is formed of the same material and forming method as the first electromagnetic shielding layer 251, is connected to the alignment mark 215 via the first electromagnetic shielding layer 251, and is grounded. The combination of the first electromagnetic shielding layer 251 and the second electromagnetic shielding layer 252 can provide a better electromagnetic shielding effect with the chip 220. There is no need to specially design or change the ground connection structure and thickness of the mother board 210, and the sealing body 230 is still effective from the half-cutting step shown in FIG. 3D to the individual dividing step shown in FIG. 3H in the mounting process. A chip can be mounted.

図５と図６に示すように、上述半導体実装方法により製造し得た半導体パッケージは、主に基板ユニット２１３、チップ２２０、封止体２３０、第一電磁遮蔽層２５１及び第二電磁遮蔽層２５２を備える。チップ２２０は基板ユニット２１３の上に設置され、封止体２３０はマザー基板２１０の上表面２１１に形成されて基板ユニット２１３を被覆し、半切断溝２４０の側辺２４１は下表面２１２の側辺からなる。位置合わせマーク２１５を被覆連結するように下表面２１２に第一電磁遮蔽層２５１をパターン化形成し、第一電磁遮蔽層２５１はさらに半切断溝２４０の側辺２４１に形成される。第二電磁遮蔽層２５２は封止体２３０の頂面２３１と分割側面２３２とに形成され、さらに第一電磁遮蔽層２５１に連結する。より好ましい場合、第一電磁遮蔽層２５１は位置合わせマーク２１５を完全に被覆し、位置合わせマーク２１５に一致する形状で下表面２１２に形成される。よって、半導体パッケージは優れる側面電磁遮蔽効果を得る。   As shown in FIGS. 5 and 6, the semiconductor package manufactured by the semiconductor mounting method described above mainly includes the substrate unit 213, the chip 220, the sealing body 230, the first electromagnetic shielding layer 251, and the second electromagnetic shielding layer 252. Is provided. The chip 220 is installed on the substrate unit 213, the sealing body 230 is formed on the upper surface 211 of the mother substrate 210 to cover the substrate unit 213, and the side 241 of the semi-cut groove 240 is the side of the lower surface 212. Consists of. A first electromagnetic shielding layer 251 is patterned on the lower surface 212 so as to cover and connect the alignment mark 215, and the first electromagnetic shielding layer 251 is further formed on the side 241 of the semi-cut groove 240. The second electromagnetic shielding layer 252 is formed on the top surface 231 and the divided side surface 232 of the sealing body 230 and further connected to the first electromagnetic shielding layer 251. More preferably, the first electromagnetic shielding layer 251 is formed on the lower surface 212 in a shape that completely covers the alignment mark 215 and matches the alignment mark 215. Therefore, the semiconductor package has an excellent side electromagnetic shielding effect.

（第二実施例）
本発明の第二実施例において、もう一種の半導体パッケージを開示し、これは第一実施例と同様なステップ、方法で製造し得たものである。図７に示すように、第二実施例による半導体パッケージは、主に基板ユニット２１３、チップ２２０、封止体２３０、第一電磁遮蔽層２５１及び第二電磁遮蔽層２５２を備える。上記素子は大体第一実施例と同様であり、同一符号の素子についてその繰り返しの説明は省略する。第二電磁遮蔽層２５２はさらに伸びて第一電磁遮蔽層２５１が半切断溝２４０の側辺２４１に位置する部位までを被覆すればより好ましく、優れる連結と保護効果を有する。よって、第一電磁遮蔽層２５１としては、電磁遮蔽効果を考慮する必要がなく、第二電磁遮蔽層２５２と異なってより安い金属を採用することができる。 (Second embodiment)
In the second embodiment of the present invention, another type of semiconductor package is disclosed, which can be manufactured by the same steps and methods as the first embodiment. As shown in FIG. 7, the semiconductor package according to the second embodiment mainly includes a substrate unit 213, a chip 220, a sealing body 230, a first electromagnetic shielding layer 251 and a second electromagnetic shielding layer 252. The above elements are generally the same as those in the first embodiment, and repeated description of elements with the same reference numerals will be omitted. It is more preferable that the second electromagnetic shielding layer 252 further extends to cover the portion where the first electromagnetic shielding layer 251 is located on the side 241 of the semi-cut groove 240, and has excellent connection and protection effects. Therefore, it is not necessary to consider the electromagnetic shielding effect as the first electromagnetic shielding layer 251, and a cheaper metal can be adopted unlike the second electromagnetic shielding layer 252.

本実施例において、下表面２１２のパターン化形成区域における第一電磁遮蔽層２５１は、位置合わせマーク２１５を被覆することだけではなく、さらに下表面２１２における基板ユニット２１３の位置合わせマーク２１５が無い角隅を被覆する。即ち下表面２１２における基板ユニット２１３の全ての角隅は、第一電磁遮蔽層２５１に被覆される。ここで、位置合わせマーク２１５が無い角隅と位置合わせマーク２１５を有する角隅を被覆した第一電磁遮蔽層２５１の形状はそれぞれ異なり、例えば、位置合わせマークを有する角隅を被覆する第一電磁遮蔽層２５１は三角形であり、位置合わせマークが無い角隅を被覆する第一電磁遮蔽層２５１は方形または円形である。   In this embodiment, the first electromagnetic shielding layer 251 in the patterning formation area of the lower surface 212 not only covers the alignment mark 215 but also has a corner where the alignment mark 215 of the substrate unit 213 on the lower surface 212 is absent. Cover the corners. That is, all corners of the substrate unit 213 on the lower surface 212 are covered with the first electromagnetic shielding layer 251. Here, the shape of the first electromagnetic shielding layer 251 covering the corner corner without the alignment mark 215 and the corner corner having the alignment mark 215 is different, for example, the first electromagnetic shielding layer covering the corner corner with the alignment mark 215. The shielding layer 251 has a triangular shape, and the first electromagnetic shielding layer 251 covering the corners without the alignment mark is square or circular.

これにより、優れる電磁遮蔽効果を得るとともに、表面マウンティング時に下表面２１２に設置されたボンディングボール２６０を外部印刷回路基板３１０のボールパッド３１１に接合させ、角隅ボンディング材３２０を利用して第一電磁遮蔽層２５１を外部印刷回路基板３１０の接地パッド３１２またはダミパッドに接合することができる。このようにして位置合わせマーク２１５を接地連結させることができ、より多い外部印刷回路基板３１０に接地連結するルートを提供し、かつボンディングボール２６０にかかる応力を分散させることができ、より安定な表面接合性を有する。   As a result, an excellent electromagnetic shielding effect is obtained, and the bonding ball 260 installed on the lower surface 212 is bonded to the ball pad 311 of the external printed circuit board 310 during the surface mounting, and the first electromagnetic wave is obtained using the corner corner bonding material 320. The shielding layer 251 can be bonded to the ground pad 312 or the dummy pad of the external printed circuit board 310. In this way, the alignment marks 215 can be grounded, a route for grounding more external printed circuit boards 310 can be provided, and stress applied to the bonding balls 260 can be dispersed, resulting in a more stable surface. Has bondability.

以上、本発明はこのような実施形態に限定されるものではなく、発明の趣旨を逸脱しない範囲において、種々の形態で実施することができる。   As mentioned above, this invention is not limited to such embodiment, In the range which does not deviate from the meaning of invention, it can implement with a various form.

２１０ マザー基板
２１１ 上表面
２１２ 下表面
２１３ 基板ユニット
２１４ 分割ライン
２１５ 位置合わせマーク
２１６ 外接パッド
２２０ チップ
２２１ ボンディングパッド
２２２ ボンディングワイヤ
２３０ 封止体
２３１ 頂面
２３２ 分割側面
２４０ 半切断溝
２４１ 側辺
２５１ 第一電磁遮蔽層
２５２ 第二電磁遮蔽層
２６０ ボンディングボール
２７１ ダイシング工具
２７２ ダイシング工具
２８０ フォトレジスト層
３１０ 外部印刷回路基板
３１１ ボールパッド
３１２ 接地パッド
３２０ 角隅ボンディング材
Ｓ 封止体の切断間隙
Ｗ 半切断溝の幅
Ｔ 第一電磁遮蔽層の厚み
１１０ マザー基板
１１３ 基板ユニット
１１４ 分割ライン
１１７ メッキスルーホール
１２０ チップ
１２２ ボンディングワイヤ
１３０ 封止材
１３１ 頂面
１３２ 分割側面
１４０ 半切断溝
１４１ 側辺
１５２ 電磁遮蔽層
１６０ ボンディングボール 210 Mother board 211 Upper surface 212 Lower surface 213 Substrate unit 214 Dividing line 215 Alignment mark 216 External pad 220 Chip 221 Bonding pad 222 Bonding wire 230 Sealing body 231 Top surface 232 Dividing side surface 240 Semi-cut groove 241 Side 251 First Electromagnetic shielding layer 252 Second electromagnetic shielding layer 260 Bonding ball 271 Dicing tool 272 Dicing tool 280 Photoresist layer 310 External printed circuit board 311 Ball pad 312 Ground pad 320 Corner corner bonding material S Cutting gap of sealing body W Half-cut groove Width T Thickness of the first electromagnetic shielding layer 110 Mother substrate 113 Substrate unit 114 Dividing line 117 Plating through hole 120 Chip 122 Bonding wire 130 Sealing material 131 Top surface 132 Dividing side surface 140 Half-cut groove 141 Side 152 Magnetic shielding layer 160 Bonding ball

Claims (10)

上表面および下表面を有し、複数の基板ユニットおよび前記複数の基板ユニットの間にある複数の分割ラインを備えるマザー基板を提供するステップ、
前記複数の基板ユニットの上に複数のチップを設置するステップ、
前記マザー基板の上表面に、前記複数の基板ユニットおよび前記複数の分割ラインを連続被覆する封止体を形成するステップ、
前記マザー基板の下表面に、前記複数の分割ラインに沿って、少なくとも前記マザー基板を貫通する複数の半切断溝を形成するステップ、
前記マザー基板の下表面と前記半切断溝とに第一電磁遮蔽層をパターン化形成するステップ、
前記複数の分割ラインに沿って前記封止体を個片化分割し、前記複数の基板ユニットを複数の半導体パッケージに分離するステップ、
及び、
前記複数の半導体パッケージの封止体の頂面と複数の分割側面とに第二電磁遮蔽層を形成するステップ
を含み、
前記マザー基板を提供するステップにおいて、前記マザー基板の下表面に位置する基板ユニットの角隅に接地連結の位置合わせマークを形成し、
前記第一電磁遮蔽層は、前記位置合わせマークを被覆連結し、
前記第二電磁遮蔽層は前記第一電磁遮蔽層と連結することを特徴とする半導体実装方法。 Providing a mother substrate having an upper surface and a lower surface and comprising a plurality of substrate units and a plurality of dividing lines between the plurality of substrate units;
Installing a plurality of chips on the plurality of substrate units;
Forming a sealing body continuously covering the plurality of substrate units and the plurality of division lines on an upper surface of the mother substrate;
Forming a plurality of semi-cut grooves that penetrate at least the mother substrate along the plurality of dividing lines on the lower surface of the mother substrate;
Patterning a first electromagnetic shielding layer on a lower surface of the mother substrate and the half-cut groove;
Dividing the sealing body into pieces along the plurality of dividing lines, and separating the plurality of substrate units into a plurality of semiconductor packages;
as well as,
Forming a second electromagnetic shielding layer on a top surface and a plurality of divided side surfaces of the sealing body of the plurality of semiconductor packages,
In the step of providing the mother board, a ground connection alignment mark is formed at a corner of the board unit located on the lower surface of the mother board.
The first electromagnetic shielding layer covers and connects the alignment mark;
The semiconductor mounting method, wherein the second electromagnetic shielding layer is connected to the first electromagnetic shielding layer. 前記位置合わせマークは、三角形であり、一つの基板ユニットに一つのみが形成されることを特徴とする請求項１記載の半導体実装方法。   The semiconductor mounting method according to claim 1, wherein the alignment mark is triangular, and only one is formed on one substrate unit. 前記第一電磁遮蔽層は、前記位置合わせマークを完全に被覆し、前記位置合わせマークに一致する形状で前記マザー基板の下表面に形成されることを特徴とする請求項１記載の半導体実装方法。   2. The semiconductor mounting method according to claim 1, wherein the first electromagnetic shielding layer completely covers the alignment mark and is formed on a lower surface of the mother substrate in a shape matching the alignment mark. . 前記第一電磁遮蔽層のパターン化形成ステップの後かつ前記封止体の個片化分割ステップの前、前記マザー基板の下表面に前記第一電磁遮蔽層に被覆されない複数の外接パッドを設置し、前記複数の外接パッドに複数のボンディングボールを設置することを特徴とする請求項１記載の半導体実装方法。
After the patterning and forming step of the first electromagnetic shielding layer and before the dividing and dividing step of the sealing body, a plurality of circumscribed pads not covered with the first electromagnetic shielding layer are installed on the lower surface of the mother substrate. The semiconductor mounting method according to claim 1, wherein a plurality of bonding balls are installed on the plurality of circumscribed pads.
前記半切断溝群の側辺に位置する前記第一電磁遮蔽層を保留するように、前記封止体が個片化分割される切断間隙を対応する半切断溝の幅から前記第一電磁遮蔽層の二倍の厚みを引いた値より小さくすることを特徴とする請求項１〜４いずれか一項に記載の半導体実装方法。   The first electromagnetic shielding is determined from the width of the corresponding half-cutting groove so that the sealing body is divided into pieces so as to hold the first electromagnetic shielding layer located on the side of the half-cutting groove group. The semiconductor mounting method according to claim 1, wherein the semiconductor mounting method is smaller than a value obtained by subtracting twice the thickness of the layer. 前記半切断溝群の深さは、前記マザー基板の厚みと同じまたは前記マザー基板の厚みより大きく、前記封止体の厚みより小さいことを特徴とする請求項５記載の半導体実装方法。   6. The semiconductor mounting method according to claim 5, wherein a depth of the half-cut groove group is equal to or larger than a thickness of the mother substrate and smaller than a thickness of the sealing body. 上表面および下表面を有し、複数の基板ユニットを備えるマザー基板と、
前記基板ユニットの上に設置されるチップと、
前記マザー基板の上表面に形成され、前記基板ユニットを被覆する封止体と、
前記マザー基板の下表面に位置する基板ユニットの角隅に形成される接地連結の位置合わせマークを被覆連結するように、前記マザー基板の下表面にパターン化形成される第一電磁遮蔽層と、
前記封止体の頂面と複数の分割側面とに形成され、前記第一電磁遮蔽層に連結される第二電磁遮蔽層と、
を備え、
前記マザー基板の下表面の側辺は、半切断溝の側辺であり、
前記第一電磁遮蔽層は、前記半切断溝の側辺に形成されることを特徴とする半導体パッケージ。 A mother board having an upper surface and a lower surface and comprising a plurality of board units;
A chip installed on the substrate unit;
A sealing body that is formed on the upper surface of the mother substrate and covers the substrate unit;
A first electromagnetic shielding layer patterned on the lower surface of the mother substrate so as to cover and connect a ground connection alignment mark formed at a corner of the substrate unit located on the lower surface of the mother substrate;
A second electromagnetic shielding layer formed on the top surface and a plurality of divided side surfaces of the sealing body and connected to the first electromagnetic shielding layer;
With
The side of the lower surface of the mother substrate is the side of the half-cut groove,
The semiconductor package according to claim 1, wherein the first electromagnetic shielding layer is formed on a side of the half-cut groove. 前記位置合わせマークは、三角形であり、一つの基板ユニットに一つのみが形成されることを特徴とする請求項７記載の半導体パッケージ。   8. The semiconductor package according to claim 7, wherein the alignment mark has a triangular shape, and only one alignment mark is formed on one substrate unit. 前記第一電磁遮蔽層は、前記位置合わせマークを完全に被覆し、前記位置合わせマークに一致する形状で前記マザー基板の下表面に形成されることを特徴とする請求項７記載の半導体パッケージ。   The semiconductor package according to claim 7, wherein the first electromagnetic shielding layer completely covers the alignment mark and is formed on a lower surface of the mother substrate in a shape matching the alignment mark. 前記マザー基板の下表面に、前記第一電磁遮蔽層に被覆されない複数の外接パッドが設置され、
前記複数の外接パッドに複数のボンディングボールが設置されることを特徴とする請求項７〜９いずれか一項に記載の半導体パッケージ。 A plurality of circumscribed pads not covered with the first electromagnetic shielding layer are installed on the lower surface of the mother substrate,
The semiconductor package according to claim 7, wherein a plurality of bonding balls are installed on the plurality of circumscribed pads.
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