JP2002076193A - Semiconductor element storing package and package mounting board - Google Patents
Semiconductor element storing package and package mounting boardInfo
- Publication number
- JP2002076193A JP2002076193A JP2000261835A JP2000261835A JP2002076193A JP 2002076193 A JP2002076193 A JP 2002076193A JP 2000261835 A JP2000261835 A JP 2000261835A JP 2000261835 A JP2000261835 A JP 2000261835A JP 2002076193 A JP2002076193 A JP 2002076193A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor element
- insulating substrate
- ceramic insulating
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体素子を搭載
した半導体素子収納用パッケージと、これを接続導体を
介して外部回路基板に接続したパッケージ実装基板に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for housing a semiconductor element on which a semiconductor element is mounted, and a package mounting board in which the semiconductor element is connected to an external circuit board via a connection conductor.
【0002】[0002]
【従来技術】従来、配線基板は、絶縁基板の表面および
/または内部にメタライズ配線層が配設された構造から
なるが、この配線基板の代表的な例として、半導体素
子、特にLSI(大規模集積回路)等の半導体集積回路
素子を収納するための半導体素子収納用パッケージがあ
り、この半導体素子収納用パッケージは、一般にアルミ
ナセラミックスからなる絶縁基板の表面に半導体素子搭
載部が形成され、また絶縁基板の表面および内部には、
タングステン、モリブデン等の高融点金属粉末から成る
複数個のメタライズ配線層が配設されて構成され、搭載
される半導体素子と電気的に接続されている。また、絶
縁基板の下面または側面には、外部回路基板と電気的に
接続するためのメタライズランド部が備えられ、このメ
タライズランド部はメタライズ配線層と電気的に接続さ
れている。2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is disposed on the surface and / or inside of an insulating substrate. As a typical example of this wiring board, a semiconductor element, particularly an LSI (large scale LSI), is used. There is a package for accommodating a semiconductor integrated circuit element such as an integrated circuit). The package for accommodating a semiconductor element generally has a semiconductor element mounting portion formed on the surface of an insulating substrate made of alumina ceramics. On the surface and inside of the board,
A plurality of metallized wiring layers made of a refractory metal powder such as tungsten and molybdenum are provided and electrically connected to a semiconductor element to be mounted. Further, a metallized land portion for electrically connecting to the external circuit board is provided on the lower surface or side surface of the insulating substrate, and the metallized land portion is electrically connected to the metallized wiring layer.
【0003】そして、かかる半導体素子収納用パッケー
ジは、セラミック絶縁基板下面に設けられたメタライズ
ランド部と、外部回路基板表面に形成されたランド部と
を、半田等からなる接続導体により電気的に接続するこ
とにより外部回路基板に実装される。In such a package for housing a semiconductor element, a metallized land provided on the lower surface of the ceramic insulating substrate and a land formed on the surface of the external circuit board are electrically connected by a connecting conductor made of solder or the like. By doing so, it is mounted on an external circuit board.
【0004】このようなパッケージとしては、絶縁基板
の下面に半田からなる球状端子(接続導体)により構成
したボールグリッドアレイ(BGA)等の表面実装型の
パッケージが知られている。[0004] As such a package, a surface mount type package such as a ball grid array (BGA) having a spherical terminal (connection conductor) made of solder on the lower surface of an insulating substrate is known.
【0005】さらに年々、パッケージ小型化への要求が
高まっており、最近ではボールグリッドアレイ(BG
A)型パッケージの中でも、パッケージサイズがチップ
サイズに近いチップスケールパッケージ(CSP)への
移行が進んでいる。[0005] The demand for smaller packages has been increasing year by year. Recently, ball grid arrays (BGs)
A) Among the type packages, the shift to a chip scale package (CSP) whose package size is close to the chip size is progressing.
【0006】また、ボールグリッドアレイ(BGA)型
パッケージが半田ボールを介して外部回路基板と接続さ
れるのに対して、半田ボールを介さずに、半田ペースト
の印刷のみで接続するランドグリッドアレイ(LGA)
型パッケージがある。ランドグリッドアレイ(LGA)
型パッケージは、半田ボールを搭載する工程を省くこと
ができるため、コストを削減することが可能である。ま
た、絶縁基板と外部回路基板とを接続する半田等の接続
導体の厚みが小さいため、パッケージ全体の低背化が可
能であるという利点もある。しかし、その一方で、接続
導体の厚みが小さいがゆえに、絶縁基板と外部回路基板
の熱膨張差に起因して接続導体に生じる熱応力が高く、
長期にわたり安定な接続を維持できないという問題があ
る。A ball grid array (BGA) type package is connected to an external circuit board via solder balls, while a land grid array (BGA) package is connected only by printing a solder paste without using solder balls. LGA)
There is a mold package. Land grid array (LGA)
In the mold package, the step of mounting the solder balls can be omitted, so that the cost can be reduced. Further, since the thickness of the connection conductor such as solder for connecting the insulating substrate and the external circuit board is small, there is an advantage that the height of the entire package can be reduced. However, on the other hand, since the thickness of the connection conductor is small, thermal stress generated in the connection conductor due to a difference in thermal expansion between the insulating substrate and the external circuit board is high,
There is a problem that a stable connection cannot be maintained for a long time.
【0007】ボールグリッドアレイ(BGA)やチップ
スケールパッケージ(CSP)は、セラミック絶縁基板
のメタライズランド部に、半田などのロウ材からなる球
状端子(接続導体)をロウ付けし、この球状端子を外部
回路基板のランド部上に載置当接させ、しかる後、前記
球状端子を150〜400℃の温度で加熱溶融し、球状
端子をランド部に接合させることによって、セラミック
絶縁基板を外部回路基板上に実装させることが行われて
いる。このような実装構造により、半導体素子収納用パ
ッケージの内部に収容されている半導体素子は、その各
電極がメタライズランド部及び接続導体を介して外部回
路基板に電気的に接続される。In a ball grid array (BGA) or a chip scale package (CSP), a spherical terminal (connection conductor) made of a brazing material such as solder is brazed to a metallized land portion of a ceramic insulating substrate, and the spherical terminal is externally mounted. The ceramic insulating substrate is placed on and abutted on the external circuit board by placing and abutting on the land portion of the circuit board, and then heating and melting the spherical terminal at a temperature of 150 to 400 ° C. and joining the spherical terminal to the land portion. Has been implemented. With such a mounting structure, each electrode of the semiconductor element housed in the semiconductor element housing package is electrically connected to the external circuit board via the metallized land portion and the connection conductor.
【0008】なお、上記したパッケージにおける半導体
素子の実装は、半導体素子に形成された接続用電極と、
パッケージ側の素子搭載部周辺に形成されたメタライズ
配線層とをワイヤでつなぐワイヤボンディング方式が従
来より広く使われている。このワイヤボンディング方式
の半導体素子の固定方法は、半導体素子の周りにエポキ
シ樹脂等の熱硬化性樹脂を塗布し、硬化接着して固定さ
れる。[0008] The mounting of the semiconductor element in the above-described package includes connecting electrodes formed on the semiconductor element,
A wire bonding method of connecting a metallized wiring layer formed around the element mounting portion on the package side with a wire has been more widely used than before. In this method of fixing a semiconductor element by the wire bonding method, a thermosetting resin such as an epoxy resin is applied around the semiconductor element, and the semiconductor element is fixed by hardening and bonding.
【0009】上記以外の実装方法としては、パッケージ
側に形成されたメタライズ配線層上に半導体素子を搭載
し、半導体素子に形成された接続用端子とメタライズ配
線層とを直接接続することにより実装する、いわゆるフ
リップチップ型の実装も知られている。As a mounting method other than the above, a semiconductor element is mounted on a metallized wiring layer formed on the package side, and mounting is performed by directly connecting a connection terminal formed on the semiconductor element to the metallized wiring layer. A so-called flip-chip type mounting is also known.
【0010】また、半導体素子収納用パッケージにおけ
る絶縁基板としては、最近では、低温焼成化、低誘電率
化および高電気伝導性の銅配線が可能なことから、絶縁
基板をガラスセラミックス焼結体により構成することも
提案されている。In recent years, as an insulating substrate in a package for accommodating a semiconductor element, a low-temperature sintering, a low dielectric constant and a high electric conductivity copper wiring are possible. Configurations have also been proposed.
【0011】[0011]
【発明が解決しようとする課題】上記のパッケージにお
ける絶縁基板として従来より使用されているアルミナ、
ムライトなどのセラミックスは、200MPa以上の高
強度を有し、しかもメタライズ配線層などとの多層化技
術として信頼性の高い点で多用されているが、熱膨張係
数が−40〜125℃における熱膨張係数が8ppm/
℃未満と低い。Alumina conventionally used as an insulating substrate in the above package,
Ceramics such as mullite have a high strength of 200 MPa or more, and are often used because of their high reliability as a multi-layered technology with a metallized wiring layer. However, the thermal expansion coefficient at -40 to 125 ° C. The coefficient is 8 ppm /
Low when less than ° C.
【0012】そのため、絶縁基板をガラスーエポキシ樹
脂複合材料、ガラスーポリイミド樹脂複合材料などの有
機樹脂を含むプリント基板などの外部回路基板(一般に
熱膨張係数は14ppm/℃以上である)に表面実装し
た場合、即ち、セラミック絶縁基板の裏面に被着形成さ
れたメタライズランド部を、上記有機樹脂を主成分とす
る外部回路基板のランド部と接続導体を介して接続した
場合、半導体素子の作動時に発する熱がセラミック絶縁
基板と外部回路基板の両方に繰り返し印加され、外部回
路基板と絶縁基板との熱膨張係数差が生じる。Therefore, the insulating substrate is surface-mounted on an external circuit board such as a printed board containing an organic resin such as a glass-epoxy resin composite material or a glass-polyimide resin composite material (generally, the thermal expansion coefficient is 14 ppm / ° C. or more). In other words, when the metallized land portion formed on the back surface of the ceramic insulating substrate is connected to the land portion of the external circuit board containing the organic resin as a main component via a connection conductor, The generated heat is repeatedly applied to both the ceramic insulating substrate and the external circuit substrate, and a difference in thermal expansion coefficient between the external circuit substrate and the insulating substrate occurs.
【0013】この熱膨張差はパッケージ中心(セラミッ
ク絶縁基板)からの距離に依存するため、中心から最も
距離の遠いメタライズランド部において、最大の熱応力
が生じる。半導体素子の作動・停止によってこの熱応力
が繰り返し印可されると、セラミック絶縁基板と外部回
路基板を接続している接続導体は疲労し、最終的に破断
に至る。特に上記傾向は、前記BGA、LGA等の表面
実装型のパッケージにおいて顕著である。Since this difference in thermal expansion depends on the distance from the center of the package (ceramic insulating substrate), the maximum thermal stress occurs in the metallized land farthest from the center. When this thermal stress is repeatedly applied by the operation / stop of the semiconductor element, the connection conductor connecting the ceramic insulating substrate and the external circuit board becomes fatigued and eventually breaks. In particular, the above tendency is remarkable in the surface mount type packages such as the BGA and LGA.
【0014】一方、この接続導体に生じる熱応力を低減
するために、パッケージの絶縁基板に高熱膨張のガラス
セラミックスを使用して、絶縁基板と外部回路基板との
熱膨張差を低減し、熱応力を低減する試みがなされてい
る。しかしながら、熱膨張係数が8〜18ppm/℃で
ある高熱膨張ガラスセラミックスを使用した場合には、
絶縁基板と外部回路基板との熱膨張差は小さくなるもの
の、半導体素子(熱膨張係数が3ppm/℃程度)と絶
縁基板との熱膨張差が大きくなる。On the other hand, in order to reduce the thermal stress generated in the connecting conductor, a high thermal expansion glass ceramic is used for the insulating substrate of the package to reduce the difference in thermal expansion between the insulating substrate and the external circuit board, thereby reducing the thermal stress. Attempts have been made to reduce However, when a high thermal expansion glass ceramic having a thermal expansion coefficient of 8 to 18 ppm / ° C. is used,
Although the difference in thermal expansion between the insulating substrate and the external circuit board is small, the difference in thermal expansion between the semiconductor element (having a coefficient of thermal expansion of about 3 ppm / ° C.) and the insulating substrate is large.
【0015】そのため、高熱膨張ガラスセラミックスを
用いた半導体素子収納用パッケージにおいては、半導体
素子とセラミック絶縁基板との熱膨張係数差による熱応
力を低減すべく、半導体素子の外周部における絶縁基板
を上方に変形させるような熱応力が生じ、パッケージ中
心から最も距離の遠い接続導体ではなく、半導体素子の
外周部の下方に位置する接続導体において熱応力が大き
く、長期にわたり安定に電気的接続を維持できないとい
う問題があった。Therefore, in a package for housing a semiconductor element using a high thermal expansion glass ceramic, the insulating substrate at the outer peripheral portion of the semiconductor element is raised to reduce thermal stress due to a difference in thermal expansion coefficient between the semiconductor element and the ceramic insulating substrate. Thermal stress is generated in the connection conductor located below the outer peripheral portion of the semiconductor element, not in the connection conductor furthest from the package center, and the electrical connection cannot be stably maintained for a long time. There was a problem.
【0016】したがって、本発明は、外部回路基板と長
期にわたり強固で安定な接続状態を維持できる半導体素
子収納用パッケージおよびパッケージ実装基板を提供す
ることを目的とする。Accordingly, it is an object of the present invention to provide a package for housing a semiconductor element and a package mounting board capable of maintaining a strong and stable connection with an external circuit board for a long period of time.
【0017】[0017]
【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、表面に半導体素子が搭載されるセラミ
ック絶縁基板と、該セラミック絶縁基板の裏面に形成さ
れ、且つ有機樹脂を主成分とする外部回路基板のランド
部と接続導体を介して接続される複数のメタライズラン
ド部とを具備する半導体素子収納用パッケージであっ
て、前記セラミック絶縁基板の−40〜125℃におけ
る熱膨張係数が8〜18ppm/℃、ヤング率が50〜
150GPaであるとともに、前記セラミック絶縁基板
表面に、前記半導体素子が載置される凸部が形成されて
いるものである。A package for accommodating a semiconductor device according to the present invention has a ceramic insulating substrate on which a semiconductor element is mounted on a front surface, and is formed on the back surface of the ceramic insulating substrate and contains an organic resin as a main component. What is claimed is: 1. A semiconductor device housing package comprising a land portion of an external circuit board and a plurality of metallized land portions connected via connection conductors, wherein said ceramic insulating substrate has a thermal expansion coefficient at -40 to 125 ° C. of 8 to 8. 18 ppm / ° C, Young's modulus is 50 ~
150 GPa, and a projection on which the semiconductor element is mounted is formed on the surface of the ceramic insulating substrate.
【0018】このような半導体素子収納用パッケージで
は、セラミック絶縁基板の−40〜125℃における熱
膨張係数が8〜18ppm/℃であるため、半導体素子
収納用パッケージを、有機樹脂を主成分とする外部回路
基板(−40〜125℃における熱膨張係数が14pp
m/℃以上)に実装し、半導体素子を繰り返し作動させ
たとしても、パッケージのセラミック絶縁基板と外部回
路基板との熱膨張差が小さいため、パッケージのメタラ
イズランド部と外部回路基板のランド部を電気的に接続
している接続導体に作用する熱応力を小さくでき、接続
導体の破断を抑制でき、セラミック絶縁基板と外部回路
基板との接続を長期間維持できる。In such a package for housing a semiconductor element, the thermal expansion coefficient of the ceramic insulating substrate at -40 to 125.degree. C. is 8 to 18 ppm / .degree. External circuit board (Coefficient of thermal expansion at -40 to 125 ° C is 14pp
m / ° C or more) and the semiconductor element is operated repeatedly, the difference in thermal expansion between the ceramic insulating substrate of the package and the external circuit board is small. Thermal stress acting on the electrically connected connection conductor can be reduced, breakage of the connection conductor can be suppressed, and the connection between the ceramic insulating substrate and the external circuit board can be maintained for a long time.
【0019】また、セラミック絶縁基板のヤング率を、
従来のアルミナよりも小さい150GPa以下としたの
で、パッケージのメタライズランド部と外部回路基板の
ランド部を電気的に接続している接続導体であって、パ
ッケージ中心から最も距離の遠い接続導体に最大の熱応
力が生じるが、この熱応力を、パッケージのセラミック
絶縁基板の反り(撓み)変形によって緩和することがで
きるので、最も外側の接続導体に作用する熱応力をより
一層低減できる。Further, the Young's modulus of the ceramic insulating substrate is
Since it is 150 GPa or less, which is smaller than the conventional alumina, the connection conductor electrically connecting the metallized land portion of the package and the land portion of the external circuit board, and is the largest in the connection conductor farthest from the package center. Although a thermal stress is generated, the thermal stress can be reduced by warping (bending) deformation of the ceramic insulating substrate of the package, so that the thermal stress acting on the outermost connection conductor can be further reduced.
【0020】一方、セラミック絶縁基板として、高熱膨
張、低ヤング率材料を用いると、半導体素子(−40〜
125℃における熱膨張係数が3ppm/℃程度)との
熱膨張差により、半導体素子とパッケージのセラミック
絶縁基板との熱膨張差を緩和するために、半導体素子外
周部が局所的に反り易くなるが、セラミック絶縁基板表
面に、セラミック絶縁基板に凸部を形成し、この凸部に
半導体素子を搭載したので、セラミック絶縁基板の凸部
部分の剛性を向上でき、半導体素子外周部の局所的な反
りを防止でき、半導体素子外周部の下方の接続導体に作
用する熱応力を小さくでき、接続導体の破断を抑制で
き、セラミック絶縁基板と外部回路基板との接続を長期
間維持できる。On the other hand, when a high thermal expansion and low Young's modulus material is used as the ceramic insulating substrate, the semiconductor element (-40 to 40) can be used.
(The thermal expansion coefficient at 125 ° C. is about 3 ppm / ° C.). In order to reduce the thermal expansion difference between the semiconductor element and the ceramic insulating substrate of the package, the outer peripheral portion of the semiconductor element is easily warped locally. Since a convex portion is formed on the ceramic insulating substrate on the surface of the ceramic insulating substrate, and the semiconductor element is mounted on the convex portion, the rigidity of the convex portion of the ceramic insulating substrate can be improved, and the local warpage of the outer peripheral portion of the semiconductor element can be improved. Can be prevented, the thermal stress acting on the connection conductor below the outer peripheral portion of the semiconductor element can be reduced, the breakage of the connection conductor can be suppressed, and the connection between the ceramic insulating substrate and the external circuit board can be maintained for a long time.
【0021】また、セラミック絶縁基板表面に形成され
た凸部の高さが0.1〜0.3mmであることが望まし
い。このような高さに設定することにより、ワイヤボン
ディングが容易であり、半導体素子を封止するための樹
脂量を最小限に抑制でき、さらに低背化を促進できる。Further, it is desirable that the height of the projection formed on the surface of the ceramic insulating substrate is 0.1 to 0.3 mm. By setting such a height, wire bonding is easy, the amount of resin for sealing the semiconductor element can be suppressed to a minimum, and further reduction in height can be promoted.
【0022】さらに、セラミック絶縁基板がガラスセラ
ミックス焼結体からなることが望ましい。Furthermore, it is desirable that the ceramic insulating substrate is made of a glass ceramic sintered body.
【0023】本発明のパッケージ実装基板では、上記半
導体素子収納用パッケージを、有機樹脂を主成分とする
外部回路基板に載置し、前記半導体素子収納用パッケー
ジのメタライズランド部を、前記外部回路基板のランド
部に厚みが0.3mm以下の接続導体を介して接合して
なるものである。In the package mounting board according to the present invention, the semiconductor element housing package is mounted on an external circuit board mainly composed of an organic resin, and the metallized land portion of the semiconductor element housing package is connected to the external circuit board. Are connected to each other via a connection conductor having a thickness of 0.3 mm or less.
【0024】このようなパッケージ実装基板では、上記
したように、半導体素子収納用パッケージのメタライズ
ランド部と外部回路基板のランド部との間の接続導体の
熱応力を最小限に抑制できるため、厚みが0.3mm以
下の接続導体を用いたとしても、接続導体の破断を抑制
でき、セラミック絶縁基板と外部回路基板との接続を長
期間維持できるとともに、厚みが0.3mm以下の接続
導体を用いるため、より低背化できる。In such a package mounting substrate, as described above, the thermal stress of the connection conductor between the metallized land portion of the package for housing the semiconductor element and the land portion of the external circuit board can be suppressed to a minimum. Even if a connection conductor having a thickness of 0.3 mm or less is used, breakage of the connection conductor can be suppressed, the connection between the ceramic insulating substrate and the external circuit board can be maintained for a long time, and a connection conductor with a thickness of 0.3 mm or less is used. Therefore, the height can be further reduced.
【0025】[0025]
【発明の実施の形態】以下、本発明のパッケージを図1
に基づき詳細に説明する。図1は本発明の一例を示すも
ので、セラミックス絶縁基板の表面あるいは内部にメタ
ライズ配線層が配設された、いわゆる配線基板を基礎的
構造とするもので、AはBGA型パッケージ、Bは外部
回路基板である。FIG. 1 is a perspective view of a package according to the present invention.
This will be described in detail based on FIG. FIG. 1 shows an example of the present invention, which has a basic structure of a so-called wiring board in which a metallized wiring layer is disposed on the surface or inside of a ceramic insulating substrate. It is a circuit board.
【0026】パッケージAはセラミック絶縁基板1とメ
タライズ配線層2と多数のメタライズランド部3及びパ
ッケージAに搭載される半導体素子4より構成されてい
る。半導体素子4をセラミック絶縁基板1上に載置する
方法はいくつかあり、図1(a)は半導体素子4とセラ
ミック絶縁基板1に配設されたメタライズ配線層2とを
微小な半田などの導体6を介して接続し、樹脂からなる
アンダーフィル5によって封止する、いわゆるフリップ
チップ型の接合である。The package A includes a ceramic insulating substrate 1, a metallized wiring layer 2, a number of metallized land portions 3, and a semiconductor element 4 mounted on the package A. There are several methods for mounting the semiconductor element 4 on the ceramic insulating substrate 1. FIG. 1A shows that the semiconductor element 4 and the metallized wiring layer 2 provided on the ceramic insulating substrate 1 are connected by a conductor such as a fine solder. This is a so-called flip-chip type connection, which is connected via the through hole 6 and sealed with an underfill 5 made of resin.
【0027】図1(b)及び図1(c)は半導体素子4
とセラミック絶縁基板1に配設されたメタライズ配線層
2とをAl、Auなどのワイヤ7で接続するワイヤボン
ディング型の接合であり、この場合には、図1(b)の
ように封止樹脂8で気密封止する場合と、図1(c)の
ように蓋体9で気密封止する場合がある。FIGS. 1B and 1C show the semiconductor device 4.
And a metallized wiring layer 2 provided on the ceramic insulating substrate 1 by wire bonding of a wire 7 made of Al, Au, or the like. In this case, as shown in FIG. 8 and a case where the cover 9 is hermetically sealed as shown in FIG.
【0028】上記いずれの場合においても、セラミック
絶縁基板1の下面にはメタライズランド部3が形成さ
れ、絶縁基板1の表面および内部に配設されたメタライ
ズ配線層2と電気的に接続されている。In any of the above cases, a metallized land portion 3 is formed on the lower surface of the ceramic insulating substrate 1 and is electrically connected to the metallized wiring layer 2 disposed on the surface and inside of the insulating substrate 1. .
【0029】一方、外部回路基板Bはいわゆるプリント
基板からなり、ガラス?エポキシ樹脂、ガラス?ポリイミ
ド樹脂複合材料などの有機樹脂を含む材料からなる絶縁
体12の表面に、Cu、Au、Al、Ni、Sn−Pb
などの金属からなるランド部13が被着形成されたもの
であり、以下、単にプリント基板と称する場合もある。On the other hand, the external circuit board B is formed of a so-called printed board, and Cu, Au, Al, Ni, Ni is formed on the surface of the insulator 12 made of a material containing an organic resin such as a glass-epoxy resin or a glass-polyimide resin composite material. , Sn-Pb
And a land portion 13 made of metal such as a metal, and may be simply referred to as a printed circuit board.
【0030】上記BGA型パッケージAを上記外部回路
基板Bに実装するには、パッケージAの絶縁基板1下面
のメタライズランド部3を、半田などの接続導体11に
よって外部回路基板Bのランド部13上に接続されてい
る。To mount the BGA type package A on the external circuit board B, the metallized land 3 on the lower surface of the insulating substrate 1 of the package A is placed on the land 13 of the external circuit board B by connecting conductors 11 such as solder. It is connected to the.
【0031】そして、本発明のパッケージAでは、セラ
ミック絶縁基板1の−40〜125℃における熱膨張係
数が8〜18ppm/℃、ヤング率が50〜150GP
aであるとともに、セラミック絶縁基板1表面に、半導
体素子4が搭載され、セラミック絶縁基板1と同一材料
からなる凸部1aが一体に形成されている。セラミック
絶縁基板1表面に形成された凸部1aの高さは0.1〜
0.3mmであることが望ましい。In the package A of the present invention, the thermal expansion coefficient of the ceramic insulating substrate 1 at -40 to 125 ° C. is 8 to 18 ppm / ° C., and the Young's modulus is 50 to 150 GP.
a, a semiconductor element 4 is mounted on the surface of the ceramic insulating substrate 1, and a projection 1a made of the same material as the ceramic insulating substrate 1 is integrally formed. The height of the projection 1a formed on the surface of the ceramic insulating substrate 1 is 0.1 to
Desirably, it is 0.3 mm.
【0032】半導体素子4が載置される凸部1aは、セ
ラミック絶縁基板1とは別個に作製し、後付けしても良
い。凸部1aの大きさは、半導体素子4と同一寸法が望
ましいが、わずかに広くても良い。また、セラミック絶
縁基板1と異なる材料であってもよいが、同一材料から
なることが一体焼成という点から望ましい。The projection 1a on which the semiconductor element 4 is mounted may be manufactured separately from the ceramic insulating substrate 1 and may be attached later. The size of the convex portion 1a is desirably the same as that of the semiconductor element 4, but may be slightly larger. Further, the material may be different from that of the ceramic insulating substrate 1, but it is desirable that the material is the same from the viewpoint of integral firing.
【0033】このようなパッケージAでは、一般に、半
導体素子の繰り返し作動時において、パッケージA側の
メタライズランド部3と外部回路基板B側のランド部1
3を電気的に接続している接続導体11には、パッケー
ジAと外部回路基板Bとの熱膨張差により熱応力が生じ
る。In such a package A, generally, when the semiconductor element is repeatedly operated, the metallized land portion 3 on the package A side and the land portion 1 on the external circuit board B side are generally used.
Thermal stress is generated in the connection conductor 11 that electrically connects the third and third components 3 due to a difference in thermal expansion between the package A and the external circuit board B.
【0034】パッケージAと外部回路基板Bとの熱膨張
差はパッケージAの中心から離れる距離に伴い大きくな
るため、パッケージAの熱膨張係数が8ppm/℃未満
である場合には、アレイ上に並んだ多数の接続導体11
のうち、パッケージAの中心から最も遠い接続導体にお
いて最も高い熱応力が生じる。半導体素子4の作動・停
止により熱応力が繰り返し印加されると、パッケージA
の中心から最も遠い接続導体は疲労して破断し、電気的
な接続を保つことができなくなる。Since the difference in thermal expansion between the package A and the external circuit board B increases with the distance from the center of the package A, if the thermal expansion coefficient of the package A is less than 8 ppm / ° C., the package A is arranged on the array. Many connecting conductors 11
Among them, the highest thermal stress occurs in the connection conductor farthest from the center of the package A. When thermal stress is repeatedly applied by the operation / stop of the semiconductor element 4, the package A
The connection conductor furthest from the center of the wire breaks due to fatigue and cannot maintain an electrical connection.
【0035】本発明によれば、パッケージAのセラミッ
ク絶縁基板1に熱膨張係数が8〜18ppm/℃である
高熱膨張のセラミックスを用いることにより、外部回路
基板Bとの熱膨張差を小さくし、最も外側の接続導体1
1に生じる熱応力を低減することが出来る。セラミック
絶縁基板1の熱膨張係数は、特に10〜15ppm/℃
であることが、上記理由から望ましい。According to the present invention, by using a ceramic having a high thermal expansion having a thermal expansion coefficient of 8 to 18 ppm / ° C. for the ceramic insulating substrate 1 of the package A, the thermal expansion difference with the external circuit board B is reduced. Outermost connection conductor 1
1 can be reduced. The coefficient of thermal expansion of the ceramic insulating substrate 1 is particularly 10 to 15 ppm / ° C.
Is desirable for the above reason.
【0036】さらに、パッケージAのセラミック絶縁基
板1として、150GPa以下の低ヤング率のセラミッ
クスを使用することにより、パッケージAと外部回路基
板Bの熱膨張差をパッケージAの反り(撓み)変形によ
って緩和することができるので、最も外側の接続導体の
熱応力を、より一層低減できる。一方、パッケージAの
ヤング率が50GPa未満であると、封止樹脂8や、蓋
体9の影響により信頼性が低下するので、パッケージA
のセラミック絶縁基板1のヤング率は50〜150GP
aであることが望ましい。セラミック絶縁基板1のヤン
グ率は、特に80〜120GPaであることが望まし
い。Further, by using a ceramic having a low Young's modulus of 150 GPa or less as the ceramic insulating substrate 1 of the package A, a difference in thermal expansion between the package A and the external circuit board B is reduced by warpage (bending) deformation of the package A. Therefore, the thermal stress of the outermost connection conductor can be further reduced. On the other hand, if the Young's modulus of the package A is less than 50 GPa, the reliability is reduced due to the influence of the sealing resin 8 and the lid 9.
Young's modulus of the ceramic insulating substrate 1 is 50 to 150 GP.
a is desirable. It is desirable that the Young's modulus of the ceramic insulating substrate 1 is particularly 80 to 120 GPa.
【0037】一方、パッケージAのセラミック絶縁基板
1の熱膨張係数が大きい場合には、パッケージAと外部
回路基板Bとの熱膨張差は小さくなるものの、半導体素
子4とパッケージAのセラミック絶縁基板1の熱膨張差
は大きくなる。その結果、最も外側の接続導体11の熱
応力を低減できたとしても、半導体素子4の外周部の下
方に位置する接続導体11において高い応力が生じる。
これは、半導体素子4とパッケージAのセラミック絶縁
基板1との熱膨張差を緩和するために、半導体素子4外
周部が局所的に反るためである。On the other hand, when the thermal expansion coefficient of the ceramic insulating substrate 1 of the package A is large, the semiconductor element 4 and the ceramic insulating substrate 1 of the package A have a small thermal expansion difference between the package A and the external circuit board B. Has a large thermal expansion difference. As a result, even if the thermal stress of the outermost connection conductor 11 can be reduced, a high stress is generated in the connection conductor 11 located below the outer peripheral portion of the semiconductor element 4.
This is because the outer peripheral portion of the semiconductor element 4 is locally warped in order to reduce the difference in thermal expansion between the semiconductor element 4 and the ceramic insulating substrate 1 of the package A.
【0038】かかる観点から、パッケージAの中心から
最も遠い接続導体11と、半導体素子4外周部の下方に
位置する接続導体11の両方の熱応力を低減し、信頼性
の高い半導体素子収納用パッケージAを得るためには、
パッケージAの材料に高熱膨張で低ヤング率のセラミッ
クスを使用し、且つ、パッケージAの半導体素子4搭載
側に凸部1aを設けて剛性を上げることが必要であり、
凸部1aを設けることにより、半導体素子4とパッケー
ジAの熱膨張差に起因した反りを低減でき、長期にわた
り安定な接続構造を維持できる。From this viewpoint, the thermal stress of both the connection conductor 11 farthest from the center of the package A and the connection conductor 11 located below the outer periphery of the semiconductor element 4 is reduced, and a highly reliable semiconductor element storage package is provided. To get A,
It is necessary to use ceramics having a high thermal expansion and a low Young's modulus for the material of the package A, and to provide a convex portion 1a on the side of the package A on which the semiconductor element 4 is mounted to increase rigidity.
By providing the protrusion 1a, warpage due to a difference in thermal expansion between the semiconductor element 4 and the package A can be reduced, and a stable connection structure can be maintained for a long time.
【0039】即ち、剛性は厚みの3乗に比例するため、
凸部1aの高さは高いほど、半導体素子4の外周部の下
方に位置する接続導体11が受ける熱応力は小さくなる
が、高すぎると、1)ワイヤボンディングが困難とな
る、2)封止するために大量の樹脂を要する、3)パッ
ケージの高さが高くなるなどの問題が発生する。したが
って、凸部1aの高さとしては0.1〜0.3mが望ま
しい。That is, since the rigidity is proportional to the cube of the thickness,
The higher the height of the convex portion 1a, the smaller the thermal stress applied to the connection conductor 11 located below the outer peripheral portion of the semiconductor element 4, but if it is too high, 1) wire bonding becomes difficult, 2) sealing. Requires a large amount of resin, and 3) the height of the package is increased. Therefore, the height of the convex portion 1a is desirably 0.1 to 0.3 m.
【0040】また、本発明の半導体素子収納用パッケー
ジは高熱膨張であるため、最も外側の接続導体11であ
っても、生じる熱応力は極めて小さい。そのため、本発
明のパッケージAは、接続導体11の厚みhを0.3m
m以下としても、長期にわたり安定した接続構造を維持
することができ、なお且つ接続導体11の厚みが薄いた
め、実装構造全体を低背化できる。Further, since the semiconductor element housing package of the present invention has a high thermal expansion, even the outermost connection conductor 11 generates very little thermal stress. Therefore, in the package A of the present invention, the thickness h of the connection conductor 11 is set to 0.3 m.
m or less, a stable connection structure can be maintained for a long period of time, and the thickness of the connection conductor 11 is thin, so that the entire mounting structure can be reduced in height.
【0041】パッケージAのセラミック絶縁基板1材料
としては、例えば特開平10−167822号の明細書
中に記載されているようなリチウム珪酸ガラス、PbO
系ガラス、ZnO系ガラス、BaO系ガラス等のガラス
成分に対して、エンステタイト、フォルステライト、S
iO2系フィラー、MgO、ZrO2、ペタライト等の各
種セラミックスフィラーを混合し、ついで焼成したもの
が好適である。As the material of the ceramic insulating substrate 1 of the package A, for example, lithium silicate glass, PbO as described in the specification of JP-A-10-167822
For glass components such as base glass, ZnO base glass and BaO base glass, enstatite, forsterite, S
A mixture obtained by mixing various ceramic fillers such as an iO 2 filler, MgO, ZrO 2 , petalite, and the like and then firing is preferable.
【0042】例えば、上記ガラス20〜90体積%、上
記フィラー80〜10体積%の混合物に、適時有機バイ
ンダーを添加してスラリーを調製し、そのスラリーをシ
ート状に成形した後、そのシート状成形体の表面に、C
u、Au、Agなどの低抵抗金属を含む導体ペーストを
印刷塗布する。また、所望によりシート状成形体の所定
箇所にマイクロドリルやレーザー等によりスルーホール
を形成して、ホール内に前記導体ペーストを充填する。For example, a slurry is prepared by appropriately adding an organic binder to a mixture of 20 to 90% by volume of the glass and 80 to 10% by volume of the filler, and the slurry is formed into a sheet. C on the body surface
A conductive paste containing a low-resistance metal such as u, Au, or Ag is applied by printing. Further, if necessary, a through hole is formed at a predetermined position of the sheet-like molded body by a microdrill, a laser, or the like, and the hole is filled with the conductive paste.
【0043】そして、そのシート状成形体を複数積層圧
着して積層体を作製した後、これを窒素雰囲気、あるい
は水蒸気を含む窒素雰囲気中で脱脂後、800〜100
0℃の温度で焼成することにより、セラミック絶縁基板
1を作製することができる。Then, after laminating a plurality of the sheet-shaped compacts to form a laminate, the laminate is degreased in a nitrogen atmosphere or a nitrogen atmosphere containing water vapor, and then 800 to 100
By firing at a temperature of 0 ° C., the ceramic insulating substrate 1 can be manufactured.
【0044】以上のようにして構成されたパッケージで
は、パッケージAのセラミック絶縁基板1中心から最も
遠い接続導体11と、半導体素子4外周部の下方に位置
する接続導体11の両方の熱応力を低減し、接続導体1
1の破断を抑制でき、セラミック絶縁基板1と外部回路
基板Bとの接続を長期間維持でき、信頼性の高い半導体
素子収納用パッケージAを得ることができる。In the package configured as described above, the thermal stress of both the connection conductor 11 farthest from the center of the ceramic insulating substrate 1 of the package A and the connection conductor 11 located below the outer peripheral portion of the semiconductor element 4 is reduced. And connection conductor 1
1 can be suppressed, the connection between the ceramic insulating substrate 1 and the external circuit board B can be maintained for a long time, and a highly reliable semiconductor element housing package A can be obtained.
【0045】[0045]
【実施例】表1に示すガラスセラミック材料について、
5×4×40mmの形状の焼結体を作製した後、各焼結
体についてヤング率、および−40〜125℃における
熱膨張係数を測定し、表1に示した。EXAMPLE For the glass ceramic materials shown in Table 1,
After preparing a sintered body having a shape of 5 × 4 × 40 mm, the Young's modulus and the coefficient of thermal expansion at −40 to 125 ° C. of each sintered body were measured.
【0046】また、表1に示す各種ガラスセラミック材
料をセラミック絶縁基板として用いて、その表面に半導
体素子と接続されるメタライズ配線層、内部配線層及び
ビアホール導体、底面に接続導体を取りつけるための3
08個のメタライズランド部を銅ペーストを印刷し、9
00℃の温度で同時焼成してパッケージのセラミック絶
縁基板を作製した。セラミック絶縁基板サイズは縦15
mm×横15mm×厚み0.8mm、半導体素子サイズ
は縦9mm×横9mm×厚み0.27mm、凸部は縦9
mm×横9mm×厚み0.1mmとした。Further, using various glass ceramic materials shown in Table 1 as a ceramic insulating substrate, a metallized wiring layer, an internal wiring layer and a via hole conductor connected to a semiconductor element on the surface thereof, and a connecting conductor on a bottom surface for attaching a connecting conductor.
Print 08 metallized lands with copper paste
Simultaneous firing at a temperature of 00 ° C. produced a ceramic insulating substrate of the package. Ceramic insulating substrate size is 15 vertical
mm × width 15 mm × thickness 0.8 mm, semiconductor element size is height 9 mm × width 9 mm × thickness 0.27 mm, protrusion is length 9
mm × 9 mm × 0.1 mm
【0047】また、比較のために、絶縁材料として、表
1に示すようなアルミナセラミックス及びムライトセラ
ミックスを、前記各導体材料としてタングステンを用い
て1550℃で同時焼成して、上記と全く同じ大きさの
セラミック絶縁基板を作製した。For comparison, alumina ceramics and mullite ceramics as shown in Table 1 as insulating materials were simultaneously fired at 1550 ° C. using tungsten as the respective conductor materials, and the same size as above was obtained. Was manufactured.
【0048】そして上記基板のメタライズランド部に半
田(Sn63%−Pb37%)ペーストをスクリーン印
刷により塗布し、加熱溶融して半田層を形成した。Then, a solder (Sn 63% -Pb 37%) paste was applied to the metallized land portion of the substrate by screen printing, and was heated and melted to form a solder layer.
【0049】一方、外部回路基板として、ガラス?エポ
キシ基板からなり、−40〜125℃における熱膨張係
数が15ppm/℃の絶縁体の表面に銅箔からなるラン
ド部が形成されたプリント基板を準備した。On the other hand, as an external circuit board, a printed board made of a glass-epoxy board and having a land portion made of copper foil formed on the surface of an insulator having a thermal expansion coefficient of 15 ppm / ° C. at −40 to 125 ° C. is prepared. did.
【0050】そして、上記プリント基板のランド部に半
田(Sn63%−Pb37%)ペーストをスクリーン印
刷により塗布した後、上記のパッケージのメタライズラ
ンド部と上記プリント基板のランド部とを位置合わせ
し、加熱溶融させて、プリント基板のランド部にパッケ
ージのメタライズランド部を、表2に示す厚みの半田か
らなる接続導体により接合し、パッケージ実装基板を作
製した。Then, after solder (Sn 63% -Pb 37%) paste is applied to the land of the printed board by screen printing, the metallized land of the package and the land of the printed board are aligned with each other and heated. After being melted, a metallized land portion of the package was joined to a land portion of the printed circuit board by a connection conductor made of solder having a thickness shown in Table 2 to produce a package mounting board.
【0051】尚、半田からなる接続導体の厚みが0.1
mmのパッケージ実装基板を作製する際は、パッケージ
のセラミック絶縁基板側には半田ペーストの印刷は行わ
ず、プリント基板側のみ半田ペーストの印刷を行った。The thickness of the connection conductor made of solder is 0.1
When manufacturing a package mounting board of mm, solder paste was not printed on the ceramic insulating substrate side of the package, but solder paste was printed only on the printed board side.
【0052】次に、上記のようなパッケージ実装基板
を、大気雰囲気にて−40℃と125℃の各温度に制御
した恒温槽に試験サンプルをそれぞれ25分ずつ保持す
る工程を1サイクルとして最高1500サイクル繰り返
した。Next, the step of holding the test samples in the thermostat controlled at -40 ° C. and 125 ° C. in the air atmosphere for 25 minutes each for the package mounting board as described above is a maximum of 1500 cycles. The cycle was repeated.
【0053】そして、各サイクル毎にプリント基板とパ
ッケージ用基板との間の電気抵抗を測定し、電気抵抗に
変化が現れるまでのサイクル数を表2に示した。The electrical resistance between the printed circuit board and the package substrate was measured for each cycle. Table 2 shows the number of cycles until the electrical resistance changed.
【0054】[0054]
【表1】 [Table 1]
【0055】[0055]
【表2】 [Table 2]
【0056】表1、2より明らかなように、−40〜1
25℃における熱膨張係数が8〜18ppm/℃、ヤン
グ率が50〜150GPaである絶縁基板材料を用いた
半導体素子収納用パッケージは、たとえ接続導体の厚み
(半田高さ)が0.1mmであっても1500サイクル
まで抵抗変化は全く認められず、極めて安定で良好な電
気的接続状態を維持できた。しかし、上記範囲外である
パッケージでは、900サイクル以下の早い段階から抵
抗変化が検出され、実装後の信頼性に欠けることがわか
る。As is clear from Tables 1 and 2, -40 to -1
A package for semiconductor element storage using an insulating substrate material having a thermal expansion coefficient of 8 to 18 ppm / ° C. at 25 ° C. and a Young's modulus of 50 to 150 GPa has a connection conductor thickness (solder height) of 0.1 mm. However, no change in resistance was observed at all up to 1500 cycles, and an extremely stable and good electrical connection state could be maintained. However, in a package outside the above range, the resistance change is detected from an early stage of 900 cycles or less, which indicates that the reliability after mounting is lacking.
【0057】さらに、試料No.17(材料F、接続導
体厚み(半田高さ)0.3mm)の凸部高さを、表3に
示すように、0〜0.5mmまで変えて、上記と同じ条
件で信頼性試験を行なった。Further, the sample No. The reliability test was performed under the same conditions as above, with the height of the projections of 17 (material F, connection conductor thickness (solder height) 0.3 mm) being varied from 0 to 0.5 mm as shown in Table 3. Was.
【0058】[0058]
【表3】 [Table 3]
【0059】表3から明らかなように、凸部高さ0.1
〜0.3mmにおいて1500サイクルまでクリアする
ことができた。As is apparent from Table 3, the height of the convex portion is 0.1.
At ~ 0.3 mm, up to 1500 cycles could be cleared.
【0060】[0060]
【発明の効果】以上詳述したように、本発明の半導体素
子収納用パッケージは、パッケージの中心から最も遠い
接続導体と、半導体素子外周部の下方に位置する接続導
体の両方の熱応力を低減し、接続導体の厚みが小さくて
も、半導体素子収納用パッケージと外部回路基板とを、
長期間にわたり正確、かつ強固に電気的接続させること
が可能となる。As described in detail above, the semiconductor device housing package of the present invention reduces the thermal stress of both the connection conductor farthest from the center of the package and the connection conductor located below the outer periphery of the semiconductor device. And, even if the thickness of the connection conductor is small, the semiconductor element housing package and the external circuit board are
It is possible to make accurate and strong electrical connection over a long period of time.
【図1】本発明のパッケージ実装基板を説明するための
断面図であり、(a)はフリップチップ型、(b)は封
止樹脂で気密封止するワイヤボンディング型、(c)は
蓋体で気密封止するワイヤボンディング型を示すもので
ある。FIG. 1 is a cross-sectional view for explaining a package mounting board of the present invention, in which (a) is a flip chip type, (b) is a wire bonding type hermetically sealed with a sealing resin, and (c) is a lid. 1 shows a wire bonding type that is hermetically sealed.
【図2】図1のパッケージと外部回路基板の接続部分を
示す要部拡大断面図である。FIG. 2 is an enlarged sectional view of a main part showing a connection part between the package of FIG. 1 and an external circuit board.
1・・・セラミックス絶縁基板 1a・・・凸部 3・・・メタライズランド部 4・・・半導体素子 11・・・接続導体 13・・・外部回路基板のランド部 A・・・半導体素子収納用パッケージ B・・・外部回路基板 DESCRIPTION OF SYMBOLS 1 ... Ceramic insulating substrate 1a ... Convex part 3 ... Metallized land part 4 ... Semiconductor element 11 ... Connection conductor 13 ... Land part of external circuit board A ... For semiconductor element accommodation Package B: External circuit board
Claims (5)
絶縁基板と、該セラミック絶縁基板の裏面に形成され、
且つ有機樹脂を主成分とする外部回路基板のランド部と
接続導体を介して接続される複数のメタライズランド部
とを具備する半導体素子収納用パッケージであって、前
記セラミック絶縁基板の−40〜125℃における熱膨
張係数が8〜18ppm/℃、ヤング率が50〜150
GPaであるとともに、前記セラミック絶縁基板表面
に、前記半導体素子が載置される凸部が形成されている
ことを特徴とする半導体素子収納用パッケージ。1. A ceramic insulating substrate on which a semiconductor element is mounted on a front surface, and formed on a back surface of the ceramic insulating substrate,
A semiconductor element housing package comprising a land portion of an external circuit board mainly composed of an organic resin and a plurality of metallized land portions connected via connection conductors; The thermal expansion coefficient at 8 ° C. is 8 to 18 ppm / ° C., and the Young's modulus is 50 to 150.
A semiconductor element storage package, which is GPa and has a projection on which the semiconductor element is mounted on the surface of the ceramic insulating substrate.
らなり、該セラミック絶縁基板と一体に形成されている
ことを特徴とする請求項1記載の半導体素子収納用パッ
ケージ。2. The package for accommodating a semiconductor element according to claim 1, wherein the projection is made of the same material as the ceramic insulating substrate and is formed integrally with the ceramic insulating substrate.
の高さが0.1〜0.3mmであることを特徴とする請
求項1または2記載の半導体素子収納用パッケージ。3. The package for housing a semiconductor element according to claim 1, wherein the height of the projection formed on the surface of the ceramic insulating substrate is 0.1 to 0.3 mm.
焼結体からなることを特徴とする請求項1乃至3のうち
いずれかに記載の半導体素子収納用パッケージ。4. The package for housing a semiconductor element according to claim 1, wherein the ceramic insulating substrate is made of a glass ceramic sintered body.
導体素子収納用パッケージを、有機樹脂を主成分とする
外部回路基板に載置し、前記半導体素子収納用パッケー
ジのメタライズランド部を、前記外部回路基板のランド
部に厚みが0.3mm以下の接続導体を介して接合して
なることを特徴とするパッケージ実装基板。5. The package for storing a semiconductor element according to claim 1, wherein the package for mounting a semiconductor element is mounted on an external circuit board containing an organic resin as a main component. A package mounting board which is joined to a land portion of the external circuit board via a connecting conductor having a thickness of 0.3 mm or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000261835A JP2002076193A (en) | 2000-08-30 | 2000-08-30 | Semiconductor element storing package and package mounting board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000261835A JP2002076193A (en) | 2000-08-30 | 2000-08-30 | Semiconductor element storing package and package mounting board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002076193A true JP2002076193A (en) | 2002-03-15 |
Family
ID=18749614
Family Applications (1)
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---|---|---|---|
JP2000261835A Pending JP2002076193A (en) | 2000-08-30 | 2000-08-30 | Semiconductor element storing package and package mounting board |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005286331A (en) * | 2004-03-30 | 2005-10-13 | Internatl Business Mach Corp <Ibm> | Minute bump for improving lga interconnection |
JP2007095832A (en) * | 2005-09-27 | 2007-04-12 | Kyocera Corp | Electronic component and its mounting structure |
JP2007208243A (en) * | 2006-02-01 | 2007-08-16 | Samsung Electro Mech Co Ltd | Ltcc module, and method of fabricating same |
CN102610586A (en) * | 2011-01-19 | 2012-07-25 | 旭德科技股份有限公司 | Package carrier |
US9468100B2 (en) | 2012-01-27 | 2016-10-11 | Murata Manufacturing Co., Ltd. | Multilayer wiring substrate |
-
2000
- 2000-08-30 JP JP2000261835A patent/JP2002076193A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005286331A (en) * | 2004-03-30 | 2005-10-13 | Internatl Business Mach Corp <Ibm> | Minute bump for improving lga interconnection |
JP4583213B2 (en) * | 2004-03-30 | 2010-11-17 | インターナショナル・ビジネス・マシーンズ・コーポレーション | How to make micro bumps on metal contact pads |
JP2007095832A (en) * | 2005-09-27 | 2007-04-12 | Kyocera Corp | Electronic component and its mounting structure |
JP4566105B2 (en) * | 2005-09-27 | 2010-10-20 | 京セラ株式会社 | Electronic component and its mounting structure |
JP2007208243A (en) * | 2006-02-01 | 2007-08-16 | Samsung Electro Mech Co Ltd | Ltcc module, and method of fabricating same |
CN102610586A (en) * | 2011-01-19 | 2012-07-25 | 旭德科技股份有限公司 | Package carrier |
US9468100B2 (en) | 2012-01-27 | 2016-10-11 | Murata Manufacturing Co., Ltd. | Multilayer wiring substrate |
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