JPH10189815A - Mounting structure for semiconductor element mounting substrate - Google Patents

Mounting structure for semiconductor element mounting substrate

Info

Publication number
JPH10189815A
JPH10189815A JP8348262A JP34826296A JPH10189815A JP H10189815 A JPH10189815 A JP H10189815A JP 8348262 A JP8348262 A JP 8348262A JP 34826296 A JP34826296 A JP 34826296A JP H10189815 A JPH10189815 A JP H10189815A
Authority
JP
Japan
Prior art keywords
semiconductor element
substrate
insulating substrate
mounting structure
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8348262A
Other languages
Japanese (ja)
Inventor
Noriaki Hamada
紀彰 浜田
Hideto Yonekura
秀人 米倉
Koichi Yamaguchi
浩一 山口
Kenichi Nagae
謙一 永江
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP8348262A priority Critical patent/JPH10189815A/en
Publication of JPH10189815A publication Critical patent/JPH10189815A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting structure of a high quality and a highly reliable semiconductor element mounted substrate, having high connection reliability and unaffected by thermal affection. SOLUTION: A semiconductor element housing package A, which is provided with an insulated substrate 1, having a semiconductor element 5, and a metallized wiring layer 3, is arranged on an electric circuit substrate B having a wiring conductor 8 and thermal expansion coefficient different from that of the insulated substrate 1, and a semiconductor element mounting substrate, having a notched part 9, which is electrically non-conductive on a part other than a semiconductor element housing cavity, is mounted on the main surface of the insulated substrate 1.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子収納用パ
ッケージなどの半導体素子搭載基板の実装構造に関する
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor element mounting substrate such as a semiconductor element housing package.

【0002】[0002]

【従来の技術】配線基板は絶縁基板の表面もしくは内部
にメタライズ配線層が配設された構造であり、この配線
基板を用いた代表的な例として、半導体素子、とくにL
SI等の半導体素子を収容する半導体素子収納用パッケ
ージがある。
2. Description of the Related Art A wiring board has a structure in which a metallized wiring layer is disposed on the surface or inside of an insulating substrate. As a typical example using this wiring board, a semiconductor element, especially
There is a semiconductor element housing package for housing a semiconductor element such as SI.

【0003】上記半導体素子収納用パッケージによれ
ば、アルミナセラミックス等からなる絶縁基板の表面お
よび内部にWやMo等のメタライズ配線層が、さらに底
面に接続端子が配設され、そして、絶縁基板の上面中央
部に半導体素子を収容するためのキャビティが形成され
て、キャビティは蓋体によって気密に封止される。
According to the package for accommodating a semiconductor element, a metallized wiring layer such as W or Mo is provided on the surface and inside of an insulating substrate made of alumina ceramic or the like, and a connection terminal is further provided on the bottom surface. A cavity for accommodating a semiconductor element is formed at the center of the upper surface, and the cavity is hermetically sealed by a lid.

【0004】ところで、半導体素子はその集積度が高ま
るほど、これに形成される電極数も増大するが、これに
伴って半導体収納用パッケージの端子数も増大する。
[0004] As the degree of integration of a semiconductor element increases, the number of electrodes formed thereon increases, and the number of terminals of the semiconductor storage package also increases accordingly.

【0005】しかしながら、この端子数が増大するにし
ても、半導体収納用パッケージ自体の寸法には限界があ
り、その上、近年の小型化という市場ニーズに応じるた
めには、半導体収納用パッケージの接続端子の形成密度
を高くすることが必要である。
[0005] However, even if the number of terminals is increased, the dimensions of the semiconductor storage package itself are limited. In addition, in order to meet the market needs for recent miniaturization, the connection of the semiconductor storage package is required. It is necessary to increase the formation density of the terminals.

【0006】そこで、半導体収納用パッケージの端子数
を増大させるために、その下面にコバールなどの金属ピ
ンを接続したピングリッドアレイ(PGA)を配する技
術が最も一般的におこなわれているが、最近では4つの
側面に導出されたメタライズ配線層にガルウイング状
(L字状)の金属ピンが接続された、所謂クワッドフラ
ットパッケージ(QFP)、パッケージの4つの側面に
電極パッドを備えてリードピンがないリードレスチップ
キャリア(LCC)、Siチップをフリップチップ実装
したチップサイズパッケージ(CSP)、さらに絶縁基
板の下面に半田からなる球状端子を多数配置したボール
グリッドアレイ(BGA)等が提示されている。そし
て、これらの中でBGAが最も高密度化が可能であると
言われている。
Therefore, in order to increase the number of terminals of the semiconductor storage package, a technique of arranging a pin grid array (PGA) in which metal pins such as Kovar are connected to the lower surface thereof is most commonly performed. Recently, a so-called quad flat package (QFP) in which gull-wing (L-shaped) metal pins are connected to metallized wiring layers led to four side surfaces, and four side surfaces of the package are provided with electrode pads and have no lead pins A leadless chip carrier (LCC), a chip size package (CSP) in which a Si chip is flip-chip mounted, a ball grid array (BGA) in which a number of spherical terminals made of solder are arranged on the lower surface of an insulating substrate, and the like are presented. It is said that among these, the BGA can achieve the highest density.

【0007】このボールグリッドアレイ(BGA)は、
接続パッドに半田などのロウ材からなる球状端子をロウ
付けした接続端子を配した構成であり、この球状端子を
電気回路基板の配線導体上に載置および当接させ、しか
る後、上記球状端子を約250〜400℃の温度で加熱
溶融し、球状端子を配線導体に接合させることによって
電気回路基板上に実装するという技術である。そして、
このような実装構造により半導体素子収納用パッケージ
の内部に収容されている半導体素子はその各電極がメタ
ライズ配線層および接続端子を介して電気回路基板と電
気的に接続される。
[0007] This ball grid array (BGA)
A connection terminal in which a spherical terminal made of a brazing material such as solder is brazed to a connection pad, and the spherical terminal is placed on and abuts on a wiring conductor of an electric circuit board. Is heated and melted at a temperature of about 250 to 400 [deg.] C., and the spherical terminals are bonded to a wiring conductor to be mounted on an electric circuit board. And
With such a mounting structure, each electrode of the semiconductor element housed inside the semiconductor element housing package is electrically connected to the electric circuit board via the metallized wiring layer and the connection terminal.

【0008】[0008]

【発明が解決しようとする課題】これらの半導体収納用
パッケージの絶縁基板は、アルミナ、ムライト、低温焼
成材料などのセラミックスからなるので、200MPa
以上の高強度特性があり、しかも、メタライズ配線層な
どの多層化技術の信頼性も高いと言われている。
The insulating substrate of these semiconductor storage packages is made of ceramics such as alumina, mullite, low-temperature fired material, etc.
It is said that it has the above-mentioned high strength characteristics and that the reliability of the multilayer technology such as a metallized wiring layer is also high.

【0009】しかしながら、半導体素子収納用パッケー
ジに半導体素子を収容し、あるいは配線基板に半導体素
子を搭載したり、しかる後、ガラス−エポキシ樹脂等か
らなるプリント基板などに実装した場合、半導体素子の
作動時に発する熱が絶縁基板とプリント基板の双方に繰
り返し印加され、これにより、双方の基板間の熱膨張差
に起因して、大きな熱応力が発生する。
However, when the semiconductor element is housed in the semiconductor element housing package, or the semiconductor element is mounted on the wiring board, and then mounted on a printed board made of glass-epoxy resin, etc. Occasionally generated heat is repeatedly applied to both the insulating substrate and the printed circuit board, thereby generating a large thermal stress due to the difference in thermal expansion between the two substrates.

【0010】かかる熱応力は、半導体収納用パッケージ
における端子数が300個以下の場合には影響が小さい
が、端子数が300個を超えたり、半導体収納用パッケ
ージのサイズが大型化するにしたがって、その熱応力が
大きくなり、そのために半導体素子の作動および停止の
繰り返しによって熱応力が絶縁基板下面の接続パッドの
外周部、および外部電気電気回路基板の配線導体と端子
との接合界面に作用し、接続パッドが絶縁基板より剥離
したり、端子が配線導体より剥離し、その結果、配線基
板や半導体収納用パッケージをプリント基板に長期にわ
たり安定して電気的接続させられないという問題点があ
る。
[0010] Such thermal stress has a small effect when the number of terminals in the semiconductor storage package is 300 or less, but as the number of terminals exceeds 300 or the size of the semiconductor storage package increases, the thermal stress increases. The thermal stress increases, and the thermal stress acts on the outer peripheral portion of the connection pad on the lower surface of the insulating substrate and the bonding interface between the wiring conductor and the terminal of the external electric / electrical circuit board due to repetition of operation and stop of the semiconductor element, There is a problem that the connection pads are peeled off from the insulating substrate, and the terminals are peeled off from the wiring conductors. As a result, the wiring substrate and the semiconductor storage package cannot be stably and electrically connected to the printed circuit board for a long period of time.

【0011】したがって、本発明の目的は、半導体素子
収納用パッケージなどの配線基板を電気回路基板上に実
装した場合に、熱的影響を受けないようにした高品質か
つ高信頼性の半導体素子搭載基板の実装構造を提供する
ことにある。
Accordingly, an object of the present invention is to provide a high-quality and high-reliability semiconductor element mounting that is not affected by heat when a wiring board such as a semiconductor element storage package is mounted on an electric circuit board. It is to provide a mounting structure of a substrate.

【0012】[0012]

【課題を解決するための手段】本発明の半導体素子搭載
基板の実装構造は、半導体素子が配設された絶縁基板
と、メタライズ配線層とを具備した配線基板を、そのメ
タライズ配線層と電気的に導通された配線を有し、かつ
絶縁基板と異なる熱膨張率を示す電気回路基板に配した
実装構造において、前記絶縁基板の主面に電気的に非導
通の切り欠き部を設けたことを特徴とする。
According to the present invention, there is provided a mounting structure of a semiconductor element mounting substrate, wherein a wiring substrate having an insulating substrate provided with a semiconductor element and a metallized wiring layer is electrically connected to the metallized wiring layer. In a mounting structure having an electrically conductive wiring and being disposed on an electric circuit board having a different coefficient of thermal expansion from that of the insulating substrate, a cutout portion that is electrically non-conductive is provided on a main surface of the insulating substrate. Features.

【0013】また、本発明の他の半導体素子搭載基板の
実装構造は、上記配線基板が半導体素子収納用パッケー
ジであり、上記絶縁基板の主面に半導体素子収納用のキ
ャビティ以外で切り欠き部を設けたことを特徴とする。
In another aspect of the present invention, the wiring substrate is a package for storing a semiconductor element, and a cutout portion is formed on a main surface of the insulating substrate except for a cavity for storing a semiconductor element. It is characterized by having been provided.

【0014】[0014]

【発明の実施の形態】以下、本発明を添付図面に基づき
詳細に説明する。図1〜図3は本発明に係るBGA型半
導体素子収納用パッケージの実装構造であり、図1はそ
の断面図である。また、図2はその斜視図、図3はその
要部拡大断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1 to 3 show a mounting structure of a package for accommodating a BGA type semiconductor element according to the present invention, and FIG. 1 is a sectional view thereof. FIG. 2 is a perspective view thereof, and FIG. 3 is an enlarged sectional view of a main part thereof.

【0015】これらの図において、Aは半導体素子収納
用パッケージ、Bは電気回路基板である。まず、半導体
素子収納用パッケージAにおいて、1は絶縁基板、2は
蓋体、3はメタライズ配線層、4は接続端子、5は半導
体素子であり、絶縁基板1および蓋体2によって半導体
素子5を内部に気密に収容するためのキャビティ6を形
成する。そして、半導体素子5はガラス、樹脂等の接着
剤を介して絶縁基板1上に接着固定される。
In these figures, A is a package for housing a semiconductor element, and B is an electric circuit board. First, in the semiconductor element housing package A, 1 is an insulating substrate, 2 is a lid, 3 is a metallized wiring layer, 4 is a connection terminal, 5 is a semiconductor element, and the semiconductor element 5 is formed by the insulating substrate 1 and the lid 2. A cavity 6 for hermetically receiving the inside is formed. Then, the semiconductor element 5 is bonded and fixed on the insulating substrate 1 via an adhesive such as glass or resin.

【0016】また、絶縁基板1の表面および内部にはメ
タライズ配線層3が配設され、半導体素子5および接続
端子4と電気的に接続される。各接続端子4には、接続
パッド4aを介して半田(錫−鉛合金)などのロウ材か
ら成る突起状端子4bが取着されている。この突起状端
子4bは、球状もしくは柱状のロウ材を接続パッド4a
に並べるか、またはスクリーン印刷法によりロウ材を接
続パッド4a上に印刷することにより形成される。
A metallized wiring layer 3 is provided on the surface and inside of the insulating substrate 1, and is electrically connected to the semiconductor element 5 and the connection terminal 4. Projecting terminals 4b made of a brazing material such as solder (tin-lead alloy) are attached to each connection terminal 4 via a connection pad 4a. The protruding terminal 4b is formed by connecting a spherical or columnar brazing material to the connection pad 4a.
Or by printing a brazing material on the connection pads 4a by a screen printing method.

【0017】そして、図3および図4に示すように、絶
縁基板1の主面である表面および裏面にはキャビティ6
以外に切り欠き部9を有している。この切り欠き部9は
円形状であっても、あるいは四角、三角等々様々な形状
が採用でき、さらにその大きさについても適宜選択でき
る。ただし、切り欠き部9の総面積が大きいほどに本発
明の効果が大きいと言える。
As shown in FIGS. 3 and 4, cavities 6 are formed on the front and back surfaces of the insulating substrate 1 as the main surface.
In addition, a notch 9 is provided. The notch 9 may have a circular shape or various shapes such as a square and a triangle, and the size thereof may be appropriately selected. However, it can be said that the greater the total area of the cutouts 9, the greater the effect of the present invention.

【0018】また、切り欠き部9の部位も絶縁基板1の
主面である表面および裏面、もしくはその一方面だけで
あってもよく、さらに図3のように各接続端子4間に設
けてもよい。
The cutout 9 may be formed on the front surface and the back surface, which are the main surfaces of the insulating substrate 1, or only one of them, and may be provided between the connection terminals 4 as shown in FIG. Good.

【0019】他方の外部電気電気回路基板Bについて
は、一般にプリント基板と呼ばれるものであって、7は
絶縁体、8は絶縁体7上に形成された配線導体であり、
この絶縁体7は有機樹脂を含む材料からなり、具体的に
はガラス−エポキシ系複合材料などからなる。このよう
な複合材料の場合、40〜400℃における熱膨張係数
は12〜16ppm/℃である。また、配線導体8は絶
縁体7との熱膨張係数の整合性ならびに良電気伝導性の
点で、通常、Cu、Au、Al、Ni、Pb−Snなど
の金属導体からなる。
The other external electric circuit board B is generally called a printed circuit board, 7 is an insulator, 8 is a wiring conductor formed on the insulator 7,
The insulator 7 is made of a material containing an organic resin, specifically, a glass-epoxy composite material. In the case of such a composite material, the coefficient of thermal expansion at 40 to 400 ° C is 12 to 16 ppm / ° C. The wiring conductor 8 is usually made of a metal conductor such as Cu, Au, Al, Ni, or Pb-Sn in view of the matching of the thermal expansion coefficient with the insulator 7 and good electrical conductivity.

【0020】半導体素子収納用パッケージAを電気回路
基板Bに実装するには、絶縁基板1の突起状端子4bを
電気回路基板Bの配線導体8上に載置当接させ、しかる
後、約250〜400℃の温度で加熱することにより、
半田などのロウ材からなる突起状端子4b自体が溶融し
て配線導体8と接合され、電気回路基板B上に実装され
る。なお、配線導体8の表面には突起状端子4bとの接
続を容易に行うためにロウ材が被着形成されていること
が望ましい。
In order to mount the semiconductor element housing package A on the electric circuit board B, the protruding terminals 4b of the insulating substrate 1 are placed and contacted on the wiring conductors 8 of the electric circuit board B. By heating at a temperature of ~ 400 ° C,
The protruding terminal 4 b itself made of a brazing material such as solder is melted and joined to the wiring conductor 8 and mounted on the electric circuit board B. It is preferable that a brazing material is formed on the surface of the wiring conductor 8 so as to be easily connected to the protruding terminal 4b.

【0021】かくして上記構成のBGA型半導体素子収
納用パッケージの実装構造によれば、半導体素子5の作
動時に発する熱が絶縁基板1と絶縁体7の双方に繰り返
し印加され、これにより、双方の基板間の熱膨張差に起
因して、大きな熱応力が生じるような事態になっても、
絶縁基板1の主面(表面および裏面)に切り欠き部9を
形成したことで、その見かけ上のヤング率を低下させ、
絶縁基板1と絶縁体7との接続端子4に発生する応力を
低下させて、接続信頼性を向上させることができた。
Thus, according to the mounting structure of the BGA type semiconductor device housing package having the above-described structure, the heat generated when the semiconductor device 5 is operated is repeatedly applied to both the insulating substrate 1 and the insulator 7, and thereby, both the substrates Due to the difference in thermal expansion between them, even if a situation where large thermal stress occurs,
By forming the notch 9 on the main surface (front and back) of the insulating substrate 1, the apparent Young's modulus is reduced,
The stress generated in the connection terminals 4 between the insulating substrate 1 and the insulator 7 was reduced, and the connection reliability was improved.

【0022】[0022]

【実施例】つぎに本発明の実装構造に対する熱サイクル
試験を以下のとおりおこなった。絶縁基板1(ヤング率
110Gpa、熱膨張係数7ppm/℃の低温焼成基
板)の上下面に、上面のみに、もしくは下面のみに本発
明に係る切り欠き部9を設けた半導体素子収納用パッケ
ージA(ただし、半導体素子5を搭載せず)を、電気回
路基板B(プリント基板)上に実装して、それぞれ試料
No.1〜No.3の実装構造を作製した。さらに比較
例として切り欠き部9を設けない半導体素子収納用パッ
ケージに対応する実装構造も作製した。
EXAMPLE Next, a heat cycle test was performed on the mounting structure of the present invention as follows. A semiconductor device housing package A (in which a cutout 9 according to the present invention is provided only on the upper surface or lower surface, or only on the lower surface, of the insulating substrate 1 (low-temperature fired substrate having a Young's modulus of 110 Gpa and a thermal expansion coefficient of 7 ppm / ° C.)) However, the semiconductor element 5 was not mounted) on the electric circuit board B (printed board), and each of the sample Nos. 1 to No. 3 was fabricated. Further, as a comparative example, a mounting structure corresponding to a semiconductor element housing package having no cutout 9 was also manufactured.

【0023】なお、上記パッケージAは35mm角、厚
み1.2mmであり、各面における切り欠きの形状は配
線形成領域の配線間において、直径0.1mm、深さ
0.25mmの円形状のものを100個形成した。ま
た、非配線形成領域には直径1mm、深さ0.25mm
の切り欠きを20個形成した。
The package A has a size of 35 mm square and a thickness of 1.2 mm, and the shape of the notch on each surface is a circle having a diameter of 0.1 mm and a depth of 0.25 mm between the wirings in the wiring forming area. Was formed 100 times. The non-wiring formation region has a diameter of 1 mm and a depth of 0.25 mm.
20 notches were formed.

【0024】そして、各試料を大気雰囲気の恒温槽に入
れて、−40℃に温度設定した雰囲気内に15分間保持
し、さらに125℃に温度設定した雰囲気内に15分間
保持した場合を1サイクルとして、そのサイクルを繰り
返すというテストをおこなって、各サイクル毎に電気回
路基板Bの配線導体8と、半導体素子収納用パッケージ
Aの配線との電気抵抗を測定し、電気抵抗に変化が現れ
るまでのサイクル数を測定することで、耐久性をしらべ
たところ、表1に示すような結果が得られた。
Then, each sample is placed in a thermostat in an air atmosphere and held for 15 minutes in an atmosphere set at -40 ° C., and further held for 15 minutes in an atmosphere set at 125 ° C. for one cycle. A test is performed to repeat the cycle, and the electrical resistance between the wiring conductor 8 of the electric circuit board B and the wiring of the package A for semiconductor element storage is measured for each cycle, and until the electrical resistance changes. When the durability was measured by measuring the number of cycles, the results shown in Table 1 were obtained.

【0025】[0025]

【表1】 [Table 1]

【0026】表1に示す結果から明らかなとおり、本発
明の試料No.1〜No.3については、高い寿命特性
を示し、とくに試料No.1では1500サイクルでも
抵抗変化なかったが、これに対して、比較例では700
サイクルで抵抗上昇が認められた。
As is clear from the results shown in Table 1, the sample No. of the present invention. 1 to No. The sample No. 3 exhibits high life characteristics, and especially the sample No. In No. 1, the resistance did not change even after 1500 cycles, whereas in Comparative Example 700
An increase in resistance was observed during the cycle.

【0027】[0027]

【発明の効果】以上のとおり、本発明の半導体素子搭載
基板の実装構造によれば、半導体素子収納用パッケージ
などの配線基板を電気回路基板上に実装した場合に、半
導体素子が配設された絶縁基板の主面に電気的に非導通
の切り欠き部を設けたことで、絶縁基板と異なる熱膨張
率を示す電気回路基板との間で、大きな熱応力が生じる
ような事態になっても、絶縁基板の見かけ上のヤング率
を低下させ、高い接続信頼性が得られ、その結果、熱的
影響を受けないようにした高品質かつ高信頼性の半導体
素子搭載基板の実装構造が提供できた。
As described above, according to the mounting structure of the semiconductor element mounting board of the present invention, when the wiring board such as the semiconductor element storing package is mounted on the electric circuit board, the semiconductor element is provided. The provision of the electrically non-conductive cutout portion on the main surface of the insulating substrate allows a large thermal stress to occur between the insulating substrate and the electric circuit board having a different coefficient of thermal expansion. In addition, the apparent Young's modulus of the insulating substrate is reduced, and high connection reliability is obtained. As a result, a high-quality and high-reliability semiconductor element mounting substrate mounting structure that is not affected by heat can be provided. Was.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係るBGA型半導体素子収納用パッケ
ージの実装構造の断面図である。
FIG. 1 is a cross-sectional view of a mounting structure of a BGA type semiconductor device housing package according to the present invention.

【図2】本発明に係るBGA型半導体素子収納用パッケ
ージの斜視図である。
FIG. 2 is a perspective view of a BGA type semiconductor element storage package according to the present invention.

【図3】本発明に係るBGA型半導体素子収納用パッケ
ージの実装構造の要部拡大断面図である。
FIG. 3 is an enlarged sectional view of a main part of a mounting structure of a package for housing a BGA type semiconductor element according to the present invention.

【符号の説明】[Explanation of symbols]

A 半導体素子収納用パッケージ B 電気回路基板 1 絶縁基板 2 蓋体 3 メタライズ配線層 4 接続端子 5 半導体素子 6 キャビティ 4a 接続パッド 4b 突起状端子 7 絶縁体 8 配線導体 9 切り欠き部 Reference Signs List A Package for storing semiconductor element B Electric circuit board 1 Insulating substrate 2 Lid 3 Metallized wiring layer 4 Connection terminal 5 Semiconductor element 6 Cavity 4a Connection pad 4b Projecting terminal 7 Insulator 8 Wiring conductor 9 Notch

───────────────────────────────────────────────────── フロントページの続き (72)発明者 永江 謙一 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 東 昌彦 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kenichi Nagae 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute (72) Inventor Masahiko Higashi 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Kyocera Shikisha Research Institute

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子が配設された絶縁基板と、メ
タライズ配線層とを具備した配線基板を、該メタライズ
配線層と電気的に導通された配線を有し、かつ絶縁基板
と異なる熱膨張率を示す電気回路基板に配した実装構造
において、前記絶縁基板の主面に切り欠き部を設けたこ
とを特徴とする半導体素子搭載基板の実装構造。
A wiring board having an insulating substrate on which a semiconductor element is provided and a metallized wiring layer has a thermal expansion different from that of the insulating substrate, the wiring board having wiring electrically connected to the metallized wiring layer. A mounting structure for a semiconductor element mounting substrate, wherein a cutout portion is provided on a main surface of the insulating substrate in a mounting structure disposed on an electric circuit board exhibiting a ratio.
【請求項2】 前記配線基板が半導体素子収納用パッケ
ージであり、前記絶縁基板の主面で半導体素子収納用の
キャビティ以外に切り欠き部を設けたことを特徴とする
請求項1記載の半導体素子搭載基板の実装構造。
2. The semiconductor device according to claim 1, wherein the wiring substrate is a package for housing a semiconductor element, and a cutout portion is provided on a main surface of the insulating substrate in addition to a cavity for housing the semiconductor element. Mounting structure of mounting board.
JP8348262A 1996-12-26 1996-12-26 Mounting structure for semiconductor element mounting substrate Pending JPH10189815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8348262A JPH10189815A (en) 1996-12-26 1996-12-26 Mounting structure for semiconductor element mounting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8348262A JPH10189815A (en) 1996-12-26 1996-12-26 Mounting structure for semiconductor element mounting substrate

Publications (1)

Publication Number Publication Date
JPH10189815A true JPH10189815A (en) 1998-07-21

Family

ID=18395855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8348262A Pending JPH10189815A (en) 1996-12-26 1996-12-26 Mounting structure for semiconductor element mounting substrate

Country Status (1)

Country Link
JP (1) JPH10189815A (en)

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JP2008311427A (en) * 2007-06-14 2008-12-25 Toyota Central R&D Labs Inc Circuit apparatus and insulating board used for it
JP2010281641A (en) * 2009-06-03 2010-12-16 Denso Corp Mechanical quantity sensor and method for manufacturing mechanical quantity sensor
US8077478B2 (en) 2005-03-17 2011-12-13 Panasonic Corporation Module board
DE102005029175B4 (en) * 2004-06-30 2013-10-02 Denso Corporation Angular velocity sensor with a printed circuit board and a housing

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Publication number Priority date Publication date Assignee Title
DE102005029175B4 (en) * 2004-06-30 2013-10-02 Denso Corporation Angular velocity sensor with a printed circuit board and a housing
US8077478B2 (en) 2005-03-17 2011-12-13 Panasonic Corporation Module board
US8675369B2 (en) 2005-03-17 2014-03-18 Panasonic Corporation Module board
JP2008049464A (en) * 2006-08-28 2008-03-06 Matsushita Electric Works Ltd Semiconductor device
JP2008049467A (en) * 2006-08-28 2008-03-06 Matsushita Electric Works Ltd Semiconductor device
JP2008049466A (en) * 2006-08-28 2008-03-06 Matsushita Electric Works Ltd Semiconductor device
JP2008311427A (en) * 2007-06-14 2008-12-25 Toyota Central R&D Labs Inc Circuit apparatus and insulating board used for it
JP2010281641A (en) * 2009-06-03 2010-12-16 Denso Corp Mechanical quantity sensor and method for manufacturing mechanical quantity sensor
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