JP3631638B2 - Mounting structure of semiconductor device package - Google Patents

Mounting structure of semiconductor device package Download PDF

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Publication number
JP3631638B2
JP3631638B2 JP27686599A JP27686599A JP3631638B2 JP 3631638 B2 JP3631638 B2 JP 3631638B2 JP 27686599 A JP27686599 A JP 27686599A JP 27686599 A JP27686599 A JP 27686599A JP 3631638 B2 JP3631638 B2 JP 3631638B2
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Prior art keywords
package
insulating substrate
semiconductor element
thermal expansion
lid
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JP2001102475A (en
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秀人 米倉
昌彦 東
正也 國分
謙一 永江
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

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  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子用パッケージの実装構造に関し、特に大型の配線基板上に半導体素子をロウ付けにより表面実装し、その半導体素子から発生する熱を放熱するための蓋体を具備してなり、使用耐久性、信頼性に優れた半導体素子用パッケージの実装構造に関する。
【０００２】
【従来技術】
従来より、配線基板は絶縁基板の表面あるいは内部にメタライズ配線層が配設された構造からなる。また、この配線基板の代表的な例として、半導体素子、特にＬＳＩ（大規模集積回路素子）等の半導体集積回路素子を収容するための半導体素子収納用パッケージは、一般にアルミナセラミックスからなる絶縁基板の表面および内部には、タングステン、モリブデン等の高融点金属粉末から成る複数個のメタライズ配線層が配設され、上部に載置される半導体素子と電気的に接続される。一般に、半導体素子の集積度が高まるほど、半導体素子に形成される電極数も増大するが、これに伴いこれを収納する半導体収納用パッケージにおける端子数も増大することになる。
【０００３】
電極数が増大するに伴い、対応する接続端子の設置密度を変えない場合は、パッケージ自体の寸法を大きくする必要があるが、最近では、パッケージの小型化の要求が強いため、その寸法を大きくするにも限界がある。
【０００４】
従って、パッケージにおける接続端子の設置密度は高くならざるをえないが、それも最近の半導体素子の高度集積化傾向に対しては従来のワイヤボンディング方式の接続方法では十分な対応が困難になり、限界に近づきつつある。
【０００５】
そのため最近では、パッケージと半導体素子との接続は、半導体素子の周辺からパッケージの接続端子ワイヤで繋ぐワイヤボンディング方式から半導体素子下面の接続用電極とパッケージの接続端子とを直接ロウ付けするフリップチップ実装に移行しつつある。
【０００６】
また、このフリップチップ実装による接続では、半導体素子とパッケージの絶縁基板との間に熱硬化性樹脂と球状フィラーとの複合体からなるアンダーフィル剤と呼ばれる充填剤を注入後硬化させ、半導体素子の実装部を機械的に補強することがしばしば行われる。
【０００７】
また、昨今の半導体素子の高発熱化にともない、半導体素子から発生した熱を放熱するために、放熱フィンを具備した半導体素子収納用パッケージが多く使用される傾向にある。そこで、リッドと呼ばれる高熱伝導性蓋体を基板表面に取付け、さらにこのリッド上面に放熱フィンを取り付けた構造の半導体素子収納用パッケージが提案されている（特開平８− ２６４６８８号公報参照）。
【０００８】
この提案によれば、アルミナセラミック製のパッケージ基体と熱膨張係数が同等な材質からなるアルミナやコバールなどからなるリッドを有し、基体表面に搭載した電子部品から発生した熱をリッドを介して放熱フィンに伝導することができる。
【０００９】
一方で、このようなパッケージの外部回路基板への実装は、前記半導体素子が搭載されたパッケージの裏面に、いわゆるボールグリッドアレイ（ＢＧＡ）のように、半田ボールからなる接続端子を取着し、この接続端子を介して外部回路基板表面の電極にロウ材によって電気的に接続してなる。なお、外部回路基板は、おもに、プリント基板の絶縁基材はガラス−エポキシ樹脂複合材料などのように、有機質材料ないし有機質材料と無機質材料との複合材で構成される。
【００１０】
しかしながら、ＢＧＡのような接続端子を高密度に形成したパッケージの絶縁基板として従来より使用されているアルミナ、ムライト等のセラミックスを用いると、上記プリント基板などの外部回路基板に表面実装した場合、半導体素子の作動時に発する熱が絶縁基板と外部回路基板の両方に繰り返し印加され、前記外部回路基板と絶縁基板との熱膨張係数差によって熱応力が発生し、この応力によって、接続端子が絶縁基板から剥離したり、接続端子にクラックが生じ、配線基板を外部回路基板上に長期にわたり安定に維持できないという問題があった。
【００１１】
そこで、本出願人は、従来のアルミナ、ムライト等のセラミックスに変えて、絶縁基板を高熱膨張セラミック材料によって形成することによってパッケージの絶縁基板と外部回路基板の絶縁基材との熱膨張差を小さくすることにより接続信頼性を改善することを提案した（特開平８−２７９５７４号、特願平８−３２２０３８号）。
【００１２】
【発明が解決しようとする課題】
しかしながら、上記高熱膨張セラミック材料を絶縁基板として用い、前記特開平８− ２６４６８８号公報のように、絶縁基板と同等の熱膨張係数を有する同じ材質からなるリッドを取り付けた半導体素子収納用パッケージを前記プリント基板等の外部回路基板に表面実装した場合、半導体素子の作動停止による熱サイクルが印加されると、特に冷却過程においてたとえ絶縁基板に高熱膨張ガラスセラミックスを用いても外部回路基板との熱膨張差は存在するために、絶縁基板は外部回路基板との実装面が凸となるように撓もうとするが、絶縁基板は実装面と反対側に強固に接合されたリッドによって拘束されているために絶縁基板はほとんど撓むことができない。その結果、外部回路基板の絶縁基板との実装面が凸となるように撓んでしまう。
【００１３】
この撓みは配線基板と外部回路基板との接続端子のうち、外周に位置する両者の接続部を引き剥がす方向に作用する結果、接続端子が絶縁基板より剥離したり、接続端子にクラックなどが生じ、配線基板を外部回路基板上に長期にわたり安定に維持できないという欠点を有していた。
【００１４】
従って、本発明では、上記のようなリッドを具備する半導体素子用パッケージを外部回路基板に実装した場合においても、強固でかつ長期にわたり安定した電気接続を維持させることのできる長期使用信頼性に顕著に優れた半導体素子用パッケージとその実装構造を提供することを目的とするものである。
【００１５】
【課題を解決するための手段】
本発明者らは、メタライズ配線層が被着形成されたガラスセラミックスからなる絶縁基板の表面に接続用電極を備えた半導体素子を載置し、前記メタライズ配線層と前記半導体素子の接続用電極とをロウ付けすることによりフリップチップ実装してなるとともに、前記半導体素子を覆うようにして前記絶縁基板表面に取着され且つその一部をシリコーン樹脂で前記半導体素子の上面に接着されてなるＡｌ−ＳｉＣ複合材料からなる蓋体と、前記絶縁基板裏面に設けられ前記半導体素子と電気的に接続された接続端子とを具備する半導体素子用パッケージを、有機樹脂を含有する絶縁基材を備えた外部回路基板表面に実装してなる実装構造に対して、種々検討した結果、前記絶縁基板の４０〜１５０℃における熱膨張係数を８乃至２０ｐｐｍ／℃で前記外部回路基板の絶縁基材の熱膨張係数よりも小さくするとともに、前記蓋体の熱膨張係数を６ｐｐｍ／℃以上で前記絶縁基板の熱膨張係数よりも小さくすることにより、上記目的が達成できることを見いだした。
【００１６】
【発明の実施の形態】
以下、本発明に係わる実施形態について詳細に説明する。図１は、本発明の半導体素子用パッケージと、その実装構造の一例を示す概略断面図である。図１は、本発明におけるパッケージとして接続端子がボール状端子からなるＢＧＡ型パッケージを例としたものであり、Ａは半導体素子、ＢはＢＧＡ型パッケージ、Ｃは外部回路基板である。
【００１７】
図１において、パッケージＢは、セラミック絶縁基板１の表面および内部にメタライズ配線層２が被着形成されており、またパッケージＢの底面には、接続パッド３が形成され、絶縁基板１の表面および内部に配設されたメタライズ配線層２と電気的に接続されている。この図のＢＧＡ型パッケージにおいては、接続パッド３には、接続端子として球状端子４が半田などにより接続されている。
【００１８】
一方、外部回路基板Ｃは、いわゆるプリント基板からなり、ガラス−エポキシ樹脂、ガラス−ポリイミド樹脂複合材料などの有機樹脂を含む材料からなる絶縁基材５の表面に、Ｃｕ、Ａｕ、Ａｌ、Ｎｉ、Ｐｂ−Ｓｎなどの金属からなる接続パッド６が被着形成されたものである。
【００１９】
そして、この外部回路基板Ｃの接続パッド６にパッケージＢの球状端子４が半田７などにより接続されて、パッケージＢが外部回路基板Ｃの表面に実装されている。
【００２０】
パッケージＢを構成する絶縁基板１は、４０℃〜１５０℃における熱膨張係数が８乃至２０ｐｐｍ／℃のセラミックスから構成される。これは、有機樹脂を含む絶縁基材５を具備する外部回路基板Ｃとの長期接続信頼性を得るために必要である。よって、絶縁基板１の熱膨張係数が８ｐｐｍ／℃よりも小さいか、あるいは２０ｐｐｍ／℃よりも大きいと、外部回路基板Ｃとの熱膨張差が大きくなり、熱膨張差に起因する応力によって接続信頼性が損なわれるためである。
【００２１】
また、パッケージＢの表面に実装される半導体素子Ａの底面に複数の接続用電極８が設けられており、パッケージＢの表面のメタライズ配線層２と半田などのロウ材からなる接続端子９により電気的に接続されており、その周りには通常、熱硬化性樹脂からなるアンダーフィル剤１０が充填され、補強されている。
【００２２】
本発明によれば、上記の半導体素子ＡをパッケージＢの表面にロウ付け実装した構造において、半導体素子Ａの上面、すなわち、半導体素子ＡのパッケージＢへの実装面の反対側の面には、絶縁基板１より熱膨張係数が低いＡｌ−ＳｉＣ複合材料からなる蓋体（以下、単にリッドという。）１２がシリコーン樹脂１１によって接着されている。さらにはリッド１２は、絶縁基板１と接着剤１３によって接合される。
【００２３】
このような実装構造においては、リッド１２の熱膨張係数が絶縁基板１の熱膨張係数と同等とするために、リッド１２と前記絶縁基板１とを同一材料によって形成した場合、リッド１２と前記絶縁基板１とのヤング率も同等であるため、温度サイクル試験において絶縁基板１と外部回路基板Ｃとの熱膨張差により外部回路基板Ｃには撓みが発生するが、絶縁基板１、リッド１２によって拘束されている結果、絶縁基板１は撓むことができず、前記外部回路基板Ｃと絶縁基板１との接続部に応力が集中し絶縁基板１と外部回路基板Ｃとの接続が不安定になる。
【００２４】
そこで、本発明によれば、リッド１２を絶縁基板１より熱膨張係数の低い材質によって形成し、リッド１２＜絶縁基板１＜外部回路基板Ｃの順に熱膨張係数が大きくなるように組み合わせ、パッケージＢの絶縁基板１を外部回路基板Ｃとの実装面側が凹となるように撓ませることができる結果、熱膨張差により発生する絶縁基板１と外部回路基板Ｃとの接続部に作用する応力を低減することができるのである。
【００２５】
このリッド１２は、上記の熱膨張関係を満足するとともに、その役割上、高熱伝導性を有することが望まれる。具体的には、Ａｌ−ＳｉＣ複合材料（ＡｌＳｉＣ）を挙げることができ、この組成を変化させることにより、熱膨張特性を容易に変えることができ、用いるパッケージの絶縁基板の熱膨張特性に合わせて、適宜選択使用する。
【００２６】
本発明において、半導体素子Ａの上面、すなわち、半導体素子ＡのパッケージＢへの実装面の反対側の面にリッド１２を取り付けるには、まず、半導体素子Ａを絶縁基板１に実装後、半導体素子Ａの上面とリッド１２の間にシリコーン樹脂を充填する。そして、リッド１２は接着剤１３で絶縁基板１に取り付けられる。この接着剤としては具体的にはエポキシ樹脂が用いられる。この時、リッド１２の絶縁基板１への取付は、リッド１２が例えば平面的にみて四角形状である場合、絶縁基板１に対して四角形状の全ての周囲を接続すると、リッド１２の絶縁基板１への機械的な拘束力が大きくなってしまうために、絶縁基板１への取付は、四角形状の４隅のみを接続することが望ましい。
【００２７】
なお、本発明におけるパッケージＢの熱膨張係数が８乃至２０ｐｐｍ／℃である絶縁基板１は、本発明者らが先に提案した、例えば、ＢａＯを５乃至６０重量％の割合で含有する低軟化点、高熱膨張のガラスを用いて、所定のフィラーとを混合し焼成した高熱膨張性を有し、しかも１０００℃以下の低温でＣｕなどの低抵抗金属と同時焼成可能なガラスセラミック焼結体からなる。その他、特願平８−３２２０３８号の明細書中に記載されているような、例えば、リチウム珪酸系ガラス、ＰｂＯ系ガラス、ＺｎＯ系ガラス、ＢａＯ系ガラス等のガラス成分にエンスタタイト、フォルステライト、フォルステライトとＳｉＯ２ 系フィラー、ＭｇＯ、ＺｒＯ２ 、ペタライト等の各種セラミックフィラーの複合材料によって形成される。
【００２８】
例えば、上記ガラスに２０乃至９０体積％、上記フィラー８０乃至１０体積％の割合で混合した混合粉末に、適宜有機バインダーを添加してスラリーを作製し、そのスラリーをシート状に成形した後、そのシート状成形体の表面に、Ｃｕ、Ａｕ、Ａｇなどの低抵抗金属を含む導体ペーストを印刷塗布する。また、所望により、シート状成形体の所定箇所にパンチングやレーザー等によりスルーホールを形成して、スルーホール内に前記導体ペーストを充填する。そして、そのシート状成形体を積層圧着して積層体を作製した後、これを大気中あるいは窒素雰囲気で８００乃至１０００℃で焼成することにより絶縁基板を作製することができる。
【００２９】
また、上記リッド１２の上面には、所望により図１に示すように、エポキシ樹脂等の接着剤１４を用いて放熱フィン１５を取着して、半導体素子Ａから発生した熱をさらに効率的に放熱させることもできる。
【００３０】
【実施例】
表１に示す各種セラミック材料について、５ｍｍ×４ｍｍ×４０ｍｍの形状のセラミック焼結体を作製した後、各焼結体について熱膨張係数を測定した。測定値を表１に示す。
【００３１】
【表１】

Figure 0003631638
【００３２】
また、表１に示す各種セラミック焼結体を絶縁基板として用いて、それらに銅からなるメタライズ配線層及びスルーホール導体を形成し、 また、パッケージ上面のスルーホール導体に接続する個所に半導体素子と接続される多数の電極パッドを形成し、さらに底面には、外部回路基板と接続するための接続パッドを形成し、メタライズ配線層、スルーホール導体、電極パッド、接続パッドとともに、絶縁基板と窒素雰囲気中で９５０℃で同時焼成してパッケージを作製した。
【００３３】
そして、パッケージの底面の接続パッドに、高融点半田（Ｓｎ：Ｐｂ重量比＝１０：９０）からなる球状端子を低融点半田（Ｓｎ：Ｐｂ重量比＝６３：３７）により取り付けてパッケージを作製した。作製したパッケージは、縦×横×厚みを４０ｍｍ×４０ｍｍ×１ｍｍとした。
【００３４】
そして、電極パッドにＮｉメッキを施した後、電極パッドに対して、０乃至１００℃における熱膨張係数が２．８ｐｐｍ／℃のＳｉからなる半導体素子を準備し、半導体素子の底面に配設された接続用電極を低融点半田により電極パッドに接続して実装した後、半導体素子とパッケージとの間の空隙にアンダーフィル剤（エポキシ樹脂）を注入し、１８０℃で２時間熱処理して硬化させて半導体素子をパッケージに固着した。
【００３５】
その後、パッケージの上面に実装された半導体素子の上面に高熱伝導性樹脂（シリコーン樹脂）を塗布し、さらに、リッドのパッケージとの接着部に接着剤（エポキシ樹脂）を塗布した後、リッドを位置合わせして１５０℃で硬化させて固着した。
【００３６】
そして、この半導体素子及びリッドを実装したパッケージを、ガラスエポキシ基板からなる−４０乃至１２５℃における熱膨張係数が２０ｐｐｍ／℃の絶縁基材の表面に銅箔からなる接続パッドが形成されたプリント基板に対して、パッケージの球状端子と、プリント基板の接続パッドとが接続されるように位置あわせして低融点半田を用いて窒素雰囲気中で２４０℃で３分間熱処理してパッケージをプリント基板の表面に実装した。
【００３７】
（温度サイクル試験）
上記のようにパッケージをプリント基板表面に実装したものを大気雰囲気にて−４０℃と１２５℃の各温度に制御した高温槽に試験サンプルを１５分／１５分の保持を１サイクルとして最高１０００サイクル繰り返した。そして、１００サイクル毎にプリント基板の接続パッドとパッケージとの電気抵抗を測定し電気抵抗に変化が生じるまでのサイクル数を表２に示した。
【００３８】
【表２】
Figure 0003631638
【００３９】
表１、表２から明らかなように本発明であるパッケージの絶縁基板よりも熱膨張係数が低い材質からなるリッドを有する実装構造、即ち、試料Ｎｏ．１〜４、８〜１０、１５〜２０では１０００回までの熱サイクル試験においてパッケージとプリント基板との間に電気抵抗変化は全く見られず、 極めて安定で良好な電気的接続を維持した。 上記以外の試料Ｎｏ．５〜７、１１〜１４、２１（本発明外の試料）では熱サイクル試験１０００サイクル未満でパッケージとプリント基板との間に電気抵抗変化が見られ、パッケージとプリント基板の接続部で球状端子が絶縁基板から剥離したり、接続部にクラックなどが生じた。また、絶縁基板材料としてＤ：アルミナを用いた試料Ｎｏ．２２〜２８はパッケージとプリント基板間の実装信頼性が低いものであった。
【００４０】
【発明の効果】
上述した通り、本発明によれば、パッケージの絶縁基板より熱膨張係数の低い材質からなるリッドをパッケージに取り付けることにより、パッケージと外部回路基板との熱膨張差により接続部に作用する応力を低減することができる。これにより、パッケージと外部回路基板との間で接続不良を起こすことが無く、長期にわたり確実で強固な電気的接続を保持させることができる。
【図面の簡単な説明】
【図１】本発明の半導体素子用パッケージの一実施態様としてＢＧＡ型の半導体素子用パッケージとその実装構造を説明するための断面図である。
【符号の説明】
１ 絶縁基板
２ メタライズ配線層
３ 接続パッド
４ 球状端子
５ 絶縁基板
６ 接続パッド
７ 半田
８ 接続用電極
９ 接続端子
１０ アンダーフィル材
１１ 高熱伝導性樹脂
１２ 高熱伝導性蓋体
１３，１４ 接着剤
１５ 放熱フィン
Ａ 半導体素子
Ｂ パッケージ
Ｃ 外部回路基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a mounting structure for a package for a semiconductor element, and in particular, includes a lid for surface-mounting a semiconductor element on a large wiring board by brazing and dissipating heat generated from the semiconductor element, The present invention relates to a mounting structure of a package for a semiconductor element having excellent durability and reliability.
[0002]
[Prior art]
Conventionally, a wiring board has a structure in which a metallized wiring layer is disposed on the surface or inside of an insulating substrate. As a typical example of this wiring board, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI (Large Scale Integrated Circuit Element) is generally an insulating substrate made of alumina ceramics. A plurality of metallized wiring layers made of a refractory metal powder such as tungsten or molybdenum are disposed on the surface and inside, and are electrically connected to a semiconductor element mounted on the upper part. In general, as the degree of integration of a semiconductor element increases, the number of electrodes formed on the semiconductor element also increases. In accordance with this, the number of terminals in a semiconductor storage package that stores the electrode also increases.
[0003]
As the number of electrodes increases, if the installation density of the corresponding connection terminals is not changed, it is necessary to increase the size of the package itself. There are limits to doing this.
[0004]
Therefore, the installation density of the connection terminals in the package has to be high, but it is difficult to sufficiently cope with the recent trend of highly integrated semiconductor elements with the conventional wire bonding connection method. The limit is approaching.
[0005]
Therefore, recently, the connection between the package and the semiconductor element is a flip chip mounting in which the connection electrode on the lower surface of the semiconductor element and the connection terminal of the package are directly brazed from the wire bonding method in which the connection terminal wire of the package is connected from the periphery of the semiconductor element. It is moving to.
[0006]
In addition, in this connection by flip chip mounting, a filler called an underfill agent composed of a composite of a thermosetting resin and a spherical filler is injected between the semiconductor element and the insulating substrate of the package and then cured, so that the semiconductor element Often, the mounting portion is mechanically reinforced.
[0007]
In addition, with the recent increase in heat generation of semiconductor elements, semiconductor element storage packages equipped with heat radiation fins are often used to dissipate heat generated from the semiconductor elements. In view of this, there has been proposed a package for housing a semiconductor element having a structure in which a lid having a high thermal conductivity called a lid is attached to the surface of a substrate and a heat radiating fin is attached to the upper surface of the lid (see Japanese Patent Application Laid-Open No. 8-264688).
[0008]
According to this proposal, there is a lid made of alumina or Kovar made of a material having the same thermal expansion coefficient as a package base made of alumina ceramic, and heat generated from electronic components mounted on the surface of the base is radiated through the lid. Can conduct to fins.
[0009]
On the other hand, the mounting of such a package on an external circuit board is performed by attaching connection terminals made of solder balls, such as a so-called ball grid array (BGA), to the back surface of the package on which the semiconductor element is mounted. It is electrically connected to the electrode on the surface of the external circuit board through this connection terminal with a brazing material. The external circuit board is mainly composed of an organic material or a composite material of an organic material and an inorganic material, such as a glass-epoxy resin composite material, as an insulating base material of a printed board.
[0010]
However, when ceramics such as alumina and mullite, which are conventionally used as an insulating substrate of a package in which connection terminals such as BGA are formed at a high density, are used, the surface is mounted on an external circuit board such as the printed circuit board. Heat generated during the operation of the element is repeatedly applied to both the insulating substrate and the external circuit substrate, and a thermal stress is generated due to a difference in thermal expansion coefficient between the external circuit substrate and the insulating substrate. There was a problem that peeling or cracks occurred in the connection terminals, and the wiring board could not be stably maintained on the external circuit board for a long time.
[0011]
Therefore, the present applicant reduced the difference in thermal expansion between the insulating substrate of the package and the insulating base material of the external circuit board by forming the insulating substrate with a high thermal expansion ceramic material instead of the conventional ceramics such as alumina and mullite. It has been proposed to improve the connection reliability (Japanese Patent Application Laid-Open No. 8-279574, Japanese Patent Application No. 8-322038).
[0012]
[Problems to be solved by the invention]
However, a package for housing a semiconductor element in which the above-mentioned high thermal expansion ceramic material is used as an insulating substrate, and a lid made of the same material having the same thermal expansion coefficient as that of the insulating substrate is attached as described in JP-A-8-264688. When surface-mounted on an external circuit board such as a printed circuit board, thermal expansion with the external circuit board occurs even when a high thermal expansion glass ceramic is used for the insulating board, especially during the cooling process, when a thermal cycle due to the deactivation of the semiconductor element is applied. Because there is a difference, the insulating substrate tries to bend so that the mounting surface with the external circuit board becomes convex, but the insulating substrate is constrained by a lid firmly bonded to the opposite side of the mounting surface However, the insulating substrate can hardly be bent. As a result, the mounting surface of the external circuit board with the insulating substrate is bent so as to be convex.
[0013]
This bending acts in the direction of peeling the connection parts of the connection terminals on the outer periphery of the connection board between the wiring board and the external circuit board. As a result, the connection terminals are peeled off from the insulating board or cracks are generated in the connection terminals. The wiring board cannot be stably maintained on the external circuit board for a long time.
[0014]
Therefore, in the present invention, even when the semiconductor element package having the lid as described above is mounted on the external circuit board, the long-term reliability of use that can maintain a strong and stable electrical connection is remarkable. It is an object of the present invention to provide a package for a semiconductor device and a mounting structure thereof.
[0015]
[Means for Solving the Problems]
The inventors have placed a semiconductor element provided with a connection electrode on the surface of an insulating substrate made of glass ceramics on which a metallized wiring layer is deposited, and the metallized wiring layer and the connection electrode for the semiconductor element Flip chip mounting is performed by brazing, and Al-- is attached to the surface of the insulating substrate so as to cover the semiconductor element, and a part thereof is bonded to the upper surface of the semiconductor element with a silicone resin . A semiconductor device package comprising a lid made of a SiC composite material and a connection terminal provided on the back surface of the insulating substrate and electrically connected to the semiconductor device, and an external substrate provided with an insulating base material containing an organic resin the mounting structure formed by mounting on a circuit board surface, a result of various studies, the insulating substrate of 40 to 150 ° C. 8 to the thermal expansion coefficient of 20 ppm / As well as smaller than the thermal expansion coefficient of the insulating base material of the external circuit board in, to be smaller than the thermal expansion coefficient of the insulating substrate thermal expansion coefficient of the cover body 6 ppm / ° C. or higher, the object is achieved I found what I could do.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments according to the present invention will be described in detail. FIG. 1 is a schematic cross-sectional view showing an example of a package for a semiconductor device of the present invention and a mounting structure thereof. FIG. 1 shows an example of a BGA type package in which connection terminals are ball terminals as a package according to the present invention. A is a semiconductor element, B is a BGA type package, and C is an external circuit board.
[0017]
In FIG. 1, a package B has a metallized wiring layer 2 deposited and formed on the surface and inside of a ceramic insulating substrate 1, and a connection pad 3 is formed on the bottom surface of the package B. It is electrically connected to the metallized wiring layer 2 disposed inside. In the BGA type package of this figure, a spherical terminal 4 is connected to the connection pad 3 as a connection terminal by solder or the like.
[0018]
On the other hand, the external circuit board C is a so-called printed board, and Cu, Au, Al, Ni, and the like are formed on the surface of the insulating base 5 made of a material containing an organic resin such as a glass-epoxy resin and a glass-polyimide resin composite material. A connection pad 6 made of a metal such as Pb—Sn is deposited.
[0019]
The spherical terminals 4 of the package B are connected to the connection pads 6 of the external circuit board C by solder 7 or the like, and the package B is mounted on the surface of the external circuit board C.
[0020]
The insulating substrate 1 constituting the package B is made of ceramics having a thermal expansion coefficient of 8 to 20 ppm / ° C. at 40 ° C. to 150 ° C. This is necessary to obtain long-term connection reliability with the external circuit board C including the insulating base material 5 containing an organic resin. Therefore, if the thermal expansion coefficient of the insulating substrate 1 is smaller than 8 ppm / ° C. or larger than 20 ppm / ° C., the thermal expansion difference with the external circuit board C becomes large, and the connection reliability is caused by the stress due to the thermal expansion difference. This is because the properties are impaired.
[0021]
In addition, a plurality of connection electrodes 8 are provided on the bottom surface of the semiconductor element A mounted on the surface of the package B, and are electrically connected by the metallized wiring layer 2 on the surface of the package B and the connection terminals 9 made of a brazing material such as solder. The underfill agent 10 made of a thermosetting resin is usually filled and reinforced around the periphery.
[0022]
According to the present invention, in the structure in which the semiconductor element A is brazed and mounted on the surface of the package B, the upper surface of the semiconductor element A, that is, the surface opposite to the mounting surface of the semiconductor element A on the package B, A lid (hereinafter simply referred to as a lid) 12 made of an Al—SiC composite material having a thermal expansion coefficient lower than that of the insulating substrate 1 is bonded by a silicone resin 11. Furthermore, the lid 12 is bonded to the insulating substrate 1 by the adhesive 13.
[0023]
In such a mounting structure, when the lid 12 and the insulating substrate 1 are formed of the same material so that the thermal expansion coefficient of the lid 12 is equal to the thermal expansion coefficient of the insulating substrate 1, the lid 12 and the insulating substrate 1 are insulated. Since the Young's modulus is the same as that of the substrate 1, the external circuit substrate C is bent due to a difference in thermal expansion between the insulating substrate 1 and the external circuit substrate C in the temperature cycle test, but is restrained by the insulating substrate 1 and the lid 12. As a result, the insulating substrate 1 cannot be bent, stress concentrates on the connection portion between the external circuit substrate C and the insulating substrate 1, and the connection between the insulating substrate 1 and the external circuit substrate C becomes unstable. .
[0024]
Therefore, according to the present invention, the lid 12 is formed of a material having a lower thermal expansion coefficient than that of the insulating substrate 1, and is combined so that the thermal expansion coefficient becomes larger in the order of the lid 12 <insulating substrate 1 <external circuit board C. As a result, it is possible to bend the insulating substrate 1 so that the mounting surface side with the external circuit substrate C is concave, thereby reducing the stress acting on the connecting portion between the insulating substrate 1 and the external circuit substrate C, which is caused by a difference in thermal expansion. It can be done.
[0025]
The lid 12 is desired to satisfy the above thermal expansion relationship and to have high thermal conductivity due to its role. Specifically, an Al-SiC composite material (AlSiC) can be cited, and by changing this composition, the thermal expansion characteristics can be easily changed, and in accordance with the thermal expansion characteristics of the insulating substrate of the package used. , Select and use as appropriate.
[0026]
In the present invention, in order to attach the lid 12 to the upper surface of the semiconductor element A, that is, the surface opposite to the mounting surface of the semiconductor element A on the package B, first, after mounting the semiconductor element A on the insulating substrate 1, A silicone resin is filled between the upper surface of A and the lid 12. The lid 12 is attached to the insulating substrate 1 with an adhesive 13. Specifically, an epoxy resin is used as the adhesive. At this time, the lid 12 is attached to the insulating substrate 1 when, for example, the lid 12 has a quadrangular shape in plan view, when the entire periphery of the quadrilateral shape is connected to the insulating substrate 1, the lid 12 is insulated. Therefore, it is desirable to connect only the four corners of the quadrangular shape to the insulating substrate 1.
[0027]
Note that the insulating substrate 1 in which the thermal expansion coefficient of the package B in the present invention is 8 to 20 ppm / ° C. is a low softening containing, for example, BaO in a proportion of 5 to 60% by weight previously proposed by the present inventors. From a glass ceramic sintered body that has a high thermal expansion that is obtained by mixing and firing a predetermined filler using high thermal expansion glass, and that can be simultaneously fired with a low resistance metal such as Cu at a low temperature of 1000 ° C. or lower. Become. In addition, as described in the specification of Japanese Patent Application No. 8-322038, for example, enstatite, forsterite, glass components such as lithium silicate glass, PbO glass, ZnO glass, BaO glass, etc. It is formed of a composite material of various ceramic fillers such as forsterite and SiO 2 filler, MgO, ZrO 2 , and petalite.
[0028]
For example, a slurry is prepared by appropriately adding an organic binder to a mixed powder mixed with 20 to 90% by volume of the glass and 80 to 10% by volume of the filler, and the slurry is formed into a sheet shape. A conductive paste containing a low-resistance metal such as Cu, Au, or Ag is printed on the surface of the sheet-like molded body. Further, if desired, a through hole is formed in a predetermined portion of the sheet-like molded body by punching, laser, or the like, and the conductive paste is filled into the through hole. Then, after the sheet-like molded body is laminated and pressure-bonded to produce a laminated body, this is fired at 800 to 1000 ° C. in the air or in a nitrogen atmosphere, whereby an insulating substrate can be produced.
[0029]
Further, as shown in FIG. 1, if necessary, a heat radiating fin 15 is attached to the upper surface of the lid 12 by using an adhesive 14 such as an epoxy resin so that the heat generated from the semiconductor element A can be more efficiently generated. It is possible to dissipate heat.
[0030]
【Example】
After producing ceramic sintered bodies having a shape of 5 mm × 4 mm × 40 mm for various ceramic materials shown in Table 1, the thermal expansion coefficient of each sintered body was measured. The measured values are shown in Table 1.
[0031]
[Table 1]
Figure 0003631638
[0032]
In addition, using various ceramic sintered bodies shown in Table 1 as an insulating substrate, a metallized wiring layer made of copper and a through-hole conductor are formed on them, and a semiconductor element is connected to the through-hole conductor on the upper surface of the package. A large number of electrode pads to be connected are formed, and further, a connection pad for connection to an external circuit board is formed on the bottom surface, together with the metallized wiring layer, through-hole conductor, electrode pad, connection pad, insulating substrate and nitrogen atmosphere The package was fabricated by simultaneous firing at 950 ° C.
[0033]
Then, spherical terminals made of high melting point solder (Sn: Pb weight ratio = 10: 90) were attached to the connection pads on the bottom surface of the package with low melting point solder (Sn: Pb weight ratio = 63: 37) to produce a package. . The produced package was 40 mm x 40 mm x 1 mm in length x width x thickness.
[0034]
Then, after Ni plating is applied to the electrode pad, a semiconductor element made of Si having a thermal expansion coefficient of 2.8 ppm / ° C. at 0 to 100 ° C. is prepared with respect to the electrode pad and disposed on the bottom surface of the semiconductor element. After connecting the connecting electrode to the electrode pad with a low melting point solder and mounting, an underfill agent (epoxy resin) is injected into the gap between the semiconductor element and the package and cured by heat treatment at 180 ° C. for 2 hours. The semiconductor element was fixed to the package.
[0035]
After that, a high thermal conductive resin (silicone resin) is applied to the upper surface of the semiconductor element mounted on the upper surface of the package, and an adhesive (epoxy resin) is applied to the bonding portion of the lid with the package, and then the lid is positioned. Combined, cured at 150 ° C. and fixed.
[0036]
Then, the package on which the semiconductor element and the lid are mounted is a printed board in which a connection pad made of copper foil is formed on the surface of an insulating base material made of a glass epoxy board and having a thermal expansion coefficient of -20 to 125 ° C. at 20 ppm / ° C. On the other hand, the package terminal is subjected to heat treatment at 240 ° C. for 3 minutes in a nitrogen atmosphere using a low-melting point solder so that the spherical terminals of the package and the connection pads of the printed circuit board are connected to each other. Implemented.
[0037]
(Temperature cycle test)
Up to 1000 cycles with the test sample held at 15 minutes / 15 minutes in a high-temperature bath controlled at -40 ° C and 125 ° C in an air atmosphere with the package mounted on the printed circuit board surface as described above Repeated. Table 2 shows the number of cycles until the electrical resistance changes between the connection pads of the printed circuit board and the package every 100 cycles.
[0038]
[Table 2]
Figure 0003631638
[0039]
As is apparent from Tables 1 and 2, the mounting structure having a lid made of a material having a lower thermal expansion coefficient than the insulating substrate of the package according to the present invention, that is, sample No. In 1 to 4, 8 to 10, and 15 to 20, no change in electrical resistance was observed between the package and the printed circuit board in the thermal cycle test up to 1000 times, and extremely stable and good electrical connection was maintained. Sample No. other than the above In 5-7, 11-14, and 21 (samples other than the present invention), a change in electric resistance is observed between the package and the printed circuit board in less than 1000 cycles of the thermal cycle test, and a spherical terminal is formed at the connection between the package and the printed circuit board. Peeling from the insulating substrate, cracks, etc. occurred in the connection part. Sample No. D: Alumina was used as the insulating substrate material. Nos. 22 to 28 had low mounting reliability between the package and the printed circuit board.
[0040]
【The invention's effect】
As described above, according to the present invention, by attaching a lid made of a material having a lower thermal expansion coefficient than the insulating substrate of the package to the package, the stress acting on the connection portion due to the difference in thermal expansion between the package and the external circuit board is reduced. can do. Thereby, there is no connection failure between the package and the external circuit board, and a reliable and strong electrical connection can be maintained for a long time.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view for explaining a BGA type semiconductor device package and its mounting structure as an embodiment of the semiconductor device package of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Metallized wiring layer 3 Connection pad 4 Spherical terminal 5 Insulating substrate 6 Connection pad 7 Solder 8 Connection electrode 9 Connection terminal 10 Underfill material 11 High thermal conductive resin 12 High thermal conductive lid 13, 14 Adhesive 15 Heat radiation Fin A Semiconductor element B Package C External circuit board

Claims (3)

メタライズ配線層が被着形成されたガラスセラミックスからなる絶縁基板の表面に接続用電極を備えた半導体素子を載置し、前記メタライズ配線層と前記半導体素子の接続用電極とをロウ付けすることによりフリップチップ実装してなるとともに、前記半導体素子を覆うようにして前記絶縁基板表面に取着され且つその一部をシリコーン樹脂で前記半導体素子の上面に接着されてなるＡｌ−ＳｉＣ複合材料からなる蓋体と、前記絶縁基板裏面に設けられ前記半導体素子と電気的に接続された接続端子とを具備する半導体素子用パッケージを、有機樹脂を含有する絶縁基材を備えた外部回路基板表面に実装してなる実装構造であって、
前記絶縁基板の４０〜１５０℃における熱膨張係数が８乃至２０ｐｐｍ／℃であり前記外部回路基板の絶縁基材の熱膨張係数よりも小さく、
前記蓋体の熱膨張係数が６ｐｐｍ／℃以上であり前記絶縁基板の熱膨張係数よりも小さいことを特徴とする半導体素子用パッケージの実装構造。 By metallized wiring layer is placed a semiconductor device having a connection electrode on the surface of an insulating substrate made of glass ceramic, which is deposited and formed, brazing the connection electrode of the said metallized wiring layer semiconductor device A lid made of an Al-SiC composite material, which is flip-chip mounted and attached to the surface of the insulating substrate so as to cover the semiconductor element, and a part of which is bonded to the upper surface of the semiconductor element with silicone resin A package for a semiconductor element comprising a body and a connection terminal provided on the back surface of the insulating substrate and electrically connected to the semiconductor element, and mounted on the surface of an external circuit board provided with an insulating base material containing an organic resin. The mounting structure
The thermal expansion coefficient at 40 to 150 ° C. of the insulating substrate is 8 to 20 ppm / ° C., which is smaller than the thermal expansion coefficient of the insulating base material of the external circuit board,
A mounting structure for a package for a semiconductor element, wherein the lid has a thermal expansion coefficient of 6 ppm / ° C. or more and is smaller than the thermal expansion coefficient of the insulating substrate. 前記蓋体の上面に、放熱フィンを接合してなる請求項１記載の半導体素子用パッケージの実装構造。The package structure for a semiconductor element package according to claim 1, wherein a heat radiating fin is joined to an upper surface of the lid . 前記メタライズ配線層が銅を主成分とする導体からなることを特徴とする請求項１または２記載の半導体素子用パッケージの実装構造。3. The package structure for a semiconductor device package according to claim 1, wherein the metallized wiring layer is made of a conductor mainly composed of copper.
JP27686599A 1999-09-29 1999-09-29 Mounting structure of semiconductor device package Expired - Fee Related JP3631638B2 (en)

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US6979894B1 (en) * 2001-09-27 2005-12-27 Marvell International Ltd. Integrated chip package having intermediate substrate
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