JPH0773110B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a package structure used for high-density mounting of a logic LSI of a CPU for a very large computer.

[Conventional technology]

Figure 2 shows a chip 14 bonded with a chip 14
Is a mounting structure disclosed in JP-A-57-21845, in which the back surface of the cover 20 is connected to the cover 20 with a highly heat-conductive adhesive 21, and the cover is then joined with the adhesive 22 to hermetically seal. . As a result, corrosion is prevented even when brought into contact with a cooling liquid such as CFC.

However, in this flip chip structure, even if cooling from the back surface of the chip is possible, and even if it is a moisture resistant structure, it is not a structure that relaxes the thermal stress caused by the difference in thermal expansion between the chip and the substrate. , That it is considered to have a thermal fatigue life equivalent to that of conventional flip chips, and that the metallized film of the chip is a thin film that is weak against thermal history and cannot withstand the repair process. Furthermore, it is removed after the chip inspection in the repair process, and the multilayer It is thought that it is difficult to make the solder of the connection part high and uniform when reattaching it to the circuit board. Therefore, there are problems in heat fatigue resistance and repair resistance.

[Problems to be solved by the invention]

Although the above-mentioned conventional technique is sufficient for protecting the chip against moisture, it has a problem in repairability and thermal fatigue resistance required for a multi-chip device used in a computer or the like.

The object of the present invention is to flip a high-power LSI chip on a multilayer circuit board by a flip-chip method to reduce the stress of the connection terminals between the carrier board and the multilayer circuit board, and to guarantee the required heat fatigue resistance, repairability and moisture resistance. It is to provide a chip carrier mounting structure.

[Means for solving problems]

The above-mentioned object is to provide a semiconductor element, a carrier board on which the semiconductor element is mounted, a multilayer circuit board on which the board is mounted, solder for flip-chip connecting the terminals of the semiconductor element and the terminals of the carrier board, and the terminals of the carrier board and the multilayer board. In what has a solder for connecting to a circuit board, a resin composition having a thermal expansion coefficient close to the thermal expansion coefficient of the semiconductor element is filled between the semiconductor element and the carrier board, and the terminals of the carrier board are provided. This is achieved by connecting the entire outer peripheral portion of the carrier board to the multilayer circuit board by solder so that the solder connecting the terminals of the multilayer circuit board is shielded from the outside air.

Further, the resin composition is achieved by including a thermosetting resin, a rubber-like resin, a curing accelerator, a coupling agent, and an inorganic powder having a thermal expansion coefficient smaller than that of the resin component.

[Action]

The drawback of the resin carrier reinforced chip type chip carrier structure, which has both high thermal fatigue resistance and moisture resistance around the chip, is the moisture resistance of the minute soldered parts.

Therefore, by providing a repairable solder sealing part around the minute soldering part, it has become possible to greatly improve the high moisture resistance of the chip carrier.

In addition, the solder sealing part also acts as a reinforcement against the thermal stress of the chip carrier connection part caused by the temperature difference between the carrier and the multilayer circuit board, and the solder of the sealing part melts to lift the terminal solder slightly higher. Since the stress acting on the solder of the terminal is reduced, it also leads to improvement in heat resistance fatigue.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

FIG. 3 shows a multilayer ceramic circuit board 8 (referred to as a multilayer circuit board) made of a mixed mast sintered body of Al ₂ O ₃ and SiO _2.
As the carrier substrate 16, a mullite plate of a sintered body having the same coefficient of thermal expansion (which may be a glass ceramic substrate having a low dielectric constant and a coefficient of thermal expansion close to that of a mullite multilayer circuit substrate, may be used as the carrier substrate 16) 8mm Si on carrier board 16
Chip 14 is flip-chip connected with high temperature Pb-5% Sn solder 4 (melting point 300 ° C), and after connection, the space between the chip and the carrier substrate is filled with resin 15 (Japanese Patent Application No. 60-276807) shown below. , A hardened resin-reinforced chip carrier. As shown, the carrier substrate 16 is larger than the chip 14. resin
15 is a main component of thermosetting resin, rubber-like resin, curing agent,
Having a curing accelerator and a coupling agent, and an inorganic insulating powder having a thermal expansion coefficient smaller than that of the resin component, the rubber-like resin has 5 to 20% by weight in the resin, and the inorganic powder has 40 to 70% by volume of the whole.
(Preferably 50 to 60% by volume).

The particle size of the inorganic insulating powder and the rubber-like resin is preferably 5 μm or less.

Epoxy resin (EP828) 100 parts Rubber-like resin: Polybutadiene (CTBN) 15 parts Curing agent: Dicyandiamide 10 parts Curing accelerator: Imidazole (2P4MHZ) 5 parts Silane coupling agent (A-187) 2 parts Quartz powder (particle size 1 μm) , EMC-Y40) 55VOL% The life of the solder between the chip carrier and the carrier substrate is about 10 times as high as the thermal fatigue resistance of the normal flip chip bare structure.

The carrier substrate 16 is preferably 1.2 times or more the chip thickness for the purpose of avoiding a reduction in life due to warpage due to a bimetal effect caused by a difference in thermal expansion from the chip 14.

In the case of a mullite substrate, a W conductor is used as the through-hole conductor portion 5 of the carrier substrate (simultaneous firing with the substrate). The terminal surface 26 is plated with Ni in a thickness of 2 to 3 .mu.m, and then Au is plated in a thickness of 0.1 to 0.2 .mu.m.

For glass ceramic substrates, Cu paste or Cu
When the Cu paste conductor that forms the plated through-hole conductor is used, it is fired at a low temperature at the same time as the substrate. In the case of a Cu-plated conductor, the fired ceramic substrate is formed after making holes with an electron beam, laser, or the like.

On the side of the carrier substrate that is connected to the multilayer circuit board, a metallizing film 26 for sealing is provided around the terminals so as to surround the terminals (formed simultaneously with the metallizing film of the through-hole conductor). Note that Mo can be used instead of W as the sintered conductor.

Since this chip carrier needs to go through a repair process in which it is detached and then reattached to the multilayer circuit board after it is connected to the characteristic evaluation board, the thick film method, which is robust and can withstand several repairs, is optimal as the metallized film. is there. As the conductor, a Cu conductor is preferable from the viewpoint of resistance, and the terminal portion is excellent in a structure in which Ni plating and Cu plating are applied on Cu.

Solder 6 to seal the chip carrier connection area
Is a punched foil 27 having a thickness of 30 μm as shown in FIG. 3 (b). The solder material is Pb-60% Sn (melting point 183 ° C), similar to the chip carrier terminals. At the time of inspection, the sealing portion is not connected, and is connected at the same time as the chip carrier terminal portion only when connecting to the multilayer circuit board.

FIG. 3 (c) shows a state in which the chip carrier is positioned on the mullite multilayer circuit board and pressed. The size of the solder foil in the sealing portion is wider than that of the metallized portion of the terminal, and the thickness is such that even if a pressure is applied, there is a slight gap. When melted, the chip carrier terminal and the sealing portion are simultaneously melted and joined as shown in FIG. By adjusting the dimensions of the solder foil, the solder in the sealing portion also has a high effect of lifting the solder in the chip carrier connecting portion, thereby improving the thermal fatigue resistance. As the shape of the sealing portion, it is desirable that the inside and outside of the four corners are not rectangular or arcuate in order to reduce stress concentration at the four corners.

Thus, by adopting the connection structure shown in FIG. 3D, even in a chip carrier having minute terminals, the moisture resistance is greatly improved.

In addition, there is no difference in thermal expansion between the multilayer circuit board and the carrier board, but even if thermal stress is generated due to a local temperature difference, the sealing part will share the stress load, and the area of the sealing part Since the width is wide, the connection terminal is slightly lifted during melting, and the thermal fatigue resistance is also improved.

In order to improve the heat flow to the back surface of the chip, the same effect can be expected in the chip carrier structure in which the high thermal conductive plate 13 such as SiC, AlN, Cu, Cu-C composite material having a size larger than the chip is joined.

PCT (Pressure Cooker Test 121 ℃, 2kgf / cm ²
In the test), as a result of comparison with the chip carrier structure without sealing, the bare chip carrier was broken in 50 hours,
The solder-sealed structure was able to clear 800 hours. From this, it can be seen that it has a moisture resistant chip carrier structure that is more than 10 times.

In addition, when you want to replace the chip carrier connected to the multilayer circuit board, after melting and removing it, wet the excess solder of the sealing part, for example, Cu with a large surface area, and after removing by adsorption, as described above, solder foil Reconnect using.

FIGS. 4 and 5 show a cross-section of a multi-chip carrier mounting structure in which the chip carrier is joined to the multilayer circuit board 8.

Assembling is done by applying a certain amount of heat conducting grease 12 to the back surface of the chip 14 (the back surface of the SiC heat conducting plate if there is one), and then setting the height to keep the gap between the back surface and the cooling plate 11 of the housing at an average of 100 μm in advance. The side wall 29 portion is mechanically fixed to the multilayer circuit board 8 with bolts or the like, or is fixed with a thermoplastic resin to have a structure corresponding to repairability.

Since the chip carrier structure is already moisture resistant, no particular humidity protection is required. However, thermal grease
Since 12 is used, mechanical fixing of the side wall portion and resin fixing are effective for protection against deterioration of resin grease and prevention of dust intrusion.

Fig. 5 shows a structure in which the comb teeth 35 are attached in the middle. When the gap between the chip carrier and the cooling plate is not uniform, grease 12
Shows the method of inserting the between the SiC plate, the lower comb teeth and the comb teeth. This system has a structure capable of absorbing warpage of the multilayer circuit board 8 and unevenness of the gap due to variations in chip carrier height. The back surface of the chip and the SiC plate were bonded using a solder 3 having a high thermal conductivity of Au-20 wt% Sn.

FIG. 6 shows an application example in which the heat radiation stud 32 is used. The heat is transferred from the heat dissipation stud 32 to the heat transfer block 31, and further to the cooling plate 11. This structure is not a soldering or resin sealing method, but is a mechanical sealing method using bolts, springs, or the like.

FIG. 7 shows a cooling system using the CFC liquid 37 (sometimes boiling is used). Cooling efficiency is high when the multilayer circuit board 8 is used vertically.

The chip carrier structure is a resin 15 with adhesive force on the chip side.
Also, since the multilayer circuit board side is sealed with the solder 6 or the like, adverse effects due to CFC or the like cannot be considered.

Figure 8 shows a multilayered mullite board of chip carrier.
This is a structure in which the dimensions and pitch of the chip carrier connection are enlarged. By enlarging the chip carrier connection terminal 17 in this way, it can be used in the same way as the conventional chip carrier, so it is also strong in corrosion resistance to some extent, it is not necessary to seal it as a housing structure, and only the heat dissipation should be taken into consideration. .

FIG. 9 shows an example in which the chip is applied to a structure without resin sealing. The back surface of the chip is soldered to a cap 20 made of AlN, SiC, Cu-C or the like having high thermal conductivity and low expansion, and the carrier substrate is the same as described above. The drawback of this structure is that its thermal fatigue life is as short as that of a bare chip.

FIG. 10 (a) shows a chip carrier structure in which a resistor element is provided on the surface or inside of the carrier substrate for the purpose of matching the characteristic impedance. Conventionally, a flip-chip structure has been adopted, which is provided on a multi-layer circuit board or has a chip structure in which resistive elements are assembled. In the former case, the terminals of an expensive multilayer circuit board may be destroyed if the number of chip repairs is large. In the latter case, the arrangement is not suitable for high-speed computer calculation.

Therefore, as shown in the enlarged view of FIG. 2B, a thin film resistance element 40 (for example, Cr-Si-O) is formed on the carrier substrate, and a multi-layer wiring film 44 composed of the polyimide insulating layer 24 is formed thereon.
The method of connecting to the Si element through the solder bump 4 (Pb-5% Sn solder), the method of forming the thick film resistance element 42 inside the carrier substrate as shown in the enlarged view of FIG. (C), or the surface of the carrier substrate, or By forming an element on a carrier board such as a method of forming a thick film resistance element on a through-hole conductor, the burden on the thin film wiring layer on an expensive multilayer circuit board such as the ease of trimming is reduced and the process yield is improved. A structure with excellent usability such as improvement is possible.

In addition to resistors, L and C circuits can be formed as elements on the carrier substrate.

〔The invention's effect〕

Since the chip carrier and the connection terminal are protected in the chip carrier of the present invention, a direct cooling structure by boiling of CFC or the like becomes possible.

By making the flip chip a chip carrier, it is possible to use a thick film conductor with strong sintering W-Ni plating, which facilitates repairing and is easy to inspect and maintain.

Compared with the conventional bare flip-chip structure, the thermal fatigue resistance and the moisture resistance can be improved by one digit, although the structure is almost the same.

Since the area occupied by the sealing portion is large, the pressure applied to the solder terminal is small even for the pressure structure applied to the spring shown in FIG. 6, so that the structure is a creep resistant structure.

[Brief description of drawings]

1 (a) is a sectional view showing a semiconductor device chip carrier mounting structure of the present invention and its enlarged view (b), FIG. 2 is a sectional view of a conventional semiconductor device, and FIG. 3 is another mounting structure of the present invention. 2A and 2B are cross-sectional views showing the connection process of (a) before connection,
Is the shape of the solder foil, (c) is the state before joining, (d) is the one after joining, FIG. 4 is a cross-sectional view of the multi-chip structure of the mounting structure of the present invention, and FIG. 5 is the comb structure of the present invention. 6 is a sectional view of a heat dissipation stud structure according to the present invention, FIG. 7 is a sectional view when using a CFC liquid according to the present invention, and FIG. 8 is an enlarged view of a connecting portion of a carrier substrate according to the present invention. Cross-sectional view of the structure, FIG. 9 is a cross-sectional view of an application example of the resinless structure, FIG. 10 is a cross-sectional view (a) of the carrier substrate of the present invention, (b) is an enlarged cross-sectional view of the thin film resistor,
(C) is an enlarged sectional view of the thick film resistance. 1 ... Cooling plate, 2 ... Thermal grease, 3 ... Au-20% S
n solder, 4 ... Pb-5% Sn solder, 5 ... through-hole conductor, 6 ... sealing solder, 7 ... adhesive, 8 ... multilayer circuit board, 9 ... pin, 10 ... cooling channel , 11 …… cooling plate,
12 …… Thermal conductive grease, 13 …… Thermal conductive plate, 14 …… Si chip, 15 …… Resin, 16 …… Carrier board, 17 …… Pb-60% S
n Solder, 18 ... Printed board, 19 ... Low temperature solder, 20 ...
… Cover, 21 …… High thermal conductivity adhesive, 22 …… Adhesive, 23
...... Bonding part, 24 ...... Insulation layer, 25 ...... Conductor, 26 ...
… W-Ni plating-Au plating, 27 …… Solder foil, 29 …… Side wall, 30 …… Flange, 31 …… Heat conduction block, 32 …… Heat radiation stud, 33 …… Spring, 34 …… Pin , 35 …… Lower comb teeth, 36 …… Upper comb teeth, 37 …… CFC liquid, 39 …… Pb-5% Sn
Solder, 40 ... Thin film resistance, 41 ... Thin film metallization, 42 ...
… Thick film resistor, 43 …… Through-hole thick film resistor, 44 …… Thin film wiring.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoru Ogihara 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi Research Laboratory, Ltd. Computer Development Division Device Development Center (72) Inventor Mamoru Sawahata 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Institute, Ltd. (72) Masahiro Goda 4026 Kuji Town, Hitachi City, Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Tadao Kushima 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Co., Ltd. (56) References JP 59-165446 (JP, A) JP 59-996 (JP) , A) JP-A-58-39043 (JP, A) JP-A-56-104445 (JP, A) JP-A-51-147255 (JP, )

Claims (2)

[Claims] 1. A semiconductor element, a carrier board on which the semiconductor element is mounted, a multilayer circuit board on which the board is mounted, solder for flip-chip connecting the terminals of the semiconductor element and the terminals of the carrier board, and the terminals of the carrier board. In one having solder for connecting to a multilayer circuit board, a resin composition having a thermal expansion coefficient close to that of the semiconductor element is filled between the semiconductor element and the carrier board, and terminals of the carrier board are filled. A semiconductor integrated circuit device, wherein the entire outer peripheral portion of the carrier substrate is connected to the multilayer circuit board by solder so that the solder connecting the terminal of the multilayer circuit board and the terminal of the multilayer circuit board is shielded from the outside air. 2. The resin composition according to claim 1, wherein the resin composition comprises a thermosetting resin, a rubber-like resin, a curing accelerator and a coupling agent, and an inorganic powder having a thermal expansion coefficient smaller than that of the resin component. Semiconductor integrated circuit device.