JP2001244390A - Package for semiconductor device and mounting structure - Google Patents

Package for semiconductor device and mounting structure

Info

Publication number
JP2001244390A
JP2001244390A JP2000054003A JP2000054003A JP2001244390A JP 2001244390 A JP2001244390 A JP 2001244390A JP 2000054003 A JP2000054003 A JP 2000054003A JP 2000054003 A JP2000054003 A JP 2000054003A JP 2001244390 A JP2001244390 A JP 2001244390A
Authority
JP
Japan
Prior art keywords
package
semiconductor device
insulating substrate
semiconductor element
high thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000054003A
Other languages
Japanese (ja)
Inventor
Masaya Kokubu
正也 國分
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000054003A priority Critical patent/JP2001244390A/en
Publication of JP2001244390A publication Critical patent/JP2001244390A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To maintain strong and stable electrical connection for a long period even in the case where a package for semiconductor device provided with the lid for heat radiation is mounted in the outside circuit board. SOLUTION: In this solution, the package B for semiconductor device is structured by means of loading the semiconductor device A provided with a connecting electrode 8 on the surface of the insulating board 1 whereupon a metalization wiring layer 2 is formed on the surface or inside, by means of brazing both the metalization wiring layer 2 and the connecting electrode 8 of the semiconductor device A, by means of arranging the high heat conductive closure 13 with the leg 13a for covering the semiconductor device A, by means of adhering and stabilizing the leg 13a to the surface of the insulating board 1, and by means of adhering a part of the high heat conductive closure 13 to the topside of the semiconductor device A. In this package B for semiconductor device, the heat expansion coefficient of the insulating board 1 is from 8 to 20 ppm/ deg.C in the temperature from 40 to 150 deg.C, and the leg part 12a of the high heat conductive closure 12 is installed and stabilized to the surface of the insulating board 1 by the bonding agent 13 which is under 1 GPa in Young's modulus.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子用パッ
ケージに関し、特に大型の配線基板上に半導体素子をロ
ウ付けにより表面実装し、その半導体素子から発生する
熱を放熱するための高熱伝導性蓋体を具備してなり、使
用耐久性、信頼性に優れた半導体素子用パッケージとそ
の実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for a semiconductor device, and more particularly to a high thermal conductive cover for surface mounting a semiconductor device on a large-sized wiring board by brazing and dissipating heat generated from the semiconductor device. TECHNICAL FIELD The present invention relates to a semiconductor device package having a body and excellent in use durability and reliability and a mounting structure thereof.

【0002】[0002]

【従来技術】従来より、配線基板は絶縁基板の表面ある
いは内部にメタライズ配線層が配設された構造からな
る。また、この配線基板の代表的な例として、半導体素
子、特にLSI(大規模集積回路素子)等の半導体集積
回路素子を収容するための半導体素子収納用パッケージ
は、一般にアルミナセラミックスからなる絶縁基板の表
面および内部には、タングステン、モリブデン等の高融
点金属粉末から成る複数個のメタライズ配線層が配設さ
れ、上部に載置される半導体素子と電気的に接続され
る。一般に、半導体素子の集積度が高まるほど、半導体
素子に形成される電極数も増大するが、これに伴いこれ
を収納する半導体収納用パッケージにおける端子数も増
大することになる。
2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is provided on the surface or inside of an insulating substrate. A typical example of the wiring board is a semiconductor element housing package for housing a semiconductor element, especially a semiconductor integrated circuit element such as an LSI (large-scale integrated circuit element). A plurality of metallized wiring layers made of a high melting point metal powder such as tungsten or molybdenum are provided on the surface and inside, and are electrically connected to a semiconductor element mounted thereon. In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases, and accordingly, the number of terminals in a semiconductor storage package for storing the same increases.

【0003】電極数が増大するに伴い、対応する接続端
子の設置密度を変えない場合は、パッケージ自体の寸法
を大きくする必要があるが、最近では、パッケージの小
型化の要求が強いため、その寸法を大きくするにも限界
がある。
If the installation density of the corresponding connection terminals is not changed with an increase in the number of electrodes, the dimensions of the package itself must be increased. However, recently, there has been a strong demand for downsizing of the package. There is a limit in increasing the size.

【0004】従って、パッケージにおける接続端子の設
置密度は高くならざるをえないが、それも最近の半導体
素子の高度集積化傾向に対しては従来のワイヤボンディ
ング方式の接続方法では十分な対応が困難になり、限界
に近づきつつある。
Therefore, the installation density of the connection terminals in the package is unavoidable, but it is difficult for the conventional wire bonding type connection method to sufficiently cope with the recent tendency of highly integrated semiconductor devices. And is approaching its limits.

【0005】そのため最近では、パッケージと半導体素
子との接続は、半導体素子の周辺からパッケージの接続
端子ワイヤで繋ぐワイヤボンディング方式から半導体素
子下面の接続用電極とパッケージの接続端子とを直接ロ
ウ付けするフリップチップ実装に移行しつつある。
For this reason, recently, the connection between the package and the semiconductor element is directly brazed to the connection electrode on the lower surface of the semiconductor element and the connection terminal of the package by a wire bonding method in which the periphery of the semiconductor element is connected to the connection terminal wire of the package. We are moving to flip chip mounting.

【0006】また、このフリップチップ実装による接続
では、半導体素子とパッケージの絶縁基板との間に熱硬
化性樹脂と球状フィラーとの複合体からなるアンダーフ
ィル材と呼ばれる充填剤を注入後硬化させ、半導体素子
の実装部を機械的に補強することがしばしば行われる。
In connection by the flip-chip mounting, a filler called an underfill material composed of a composite of a thermosetting resin and a spherical filler is injected between a semiconductor element and an insulating substrate of a package, and then cured. It is often performed to mechanically reinforce the mounting part of a semiconductor element.

【0007】また、昨今の半導体素子の高発熱化にとも
ない、半導体素子から発生した熱を放熱するために、放
熱フィンを具備した半導体素子収納用パッケージが多く
使用される傾向にある。そこで、リッドと呼ばれる高熱
伝導性蓋体を基板表面に取付け、さらにこのリッド上面
に放熱フィンを取り付けた構造の半導体素子収納用パッ
ケージが提案されている(特開平8−264688号公
報参照)。
[0007] Further, with the recent increase in heat generation of semiconductor elements, semiconductor element storage packages provided with heat radiation fins tend to be often used to radiate heat generated from the semiconductor elements. In view of this, there has been proposed a package for housing a semiconductor element having a structure in which a highly heat-conductive lid called a lid is attached to the surface of a substrate, and further, a radiation fin is attached to the upper surface of the lid (see Japanese Patent Application Laid-Open No. 8-264688).

【0008】この提案によれば、アルミナセラミック製
のパッケージ基体と熱膨張係数が同等な材質からなるア
ルミナやコバールなどからなるリッドを有し、基体表面
に搭載した電子部品から発生した熱をリッドを介して放
熱フィンに伝導することができる。
According to this proposal, there is provided a lid made of alumina or Kovar made of a material having the same thermal expansion coefficient as that of a package base made of alumina ceramic, and the lid generates heat generated from electronic components mounted on the surface of the base. Through the heat dissipation fins.

【0009】一方で、このようなパッケージの外部回路
基板への実装は、前記半導体素子が搭載されたパッケー
ジの裏面に、いわゆるボールグリッドアレイ(BGA)
のように、半田ボールからなる接続端子を取着し、この
接続端子を介して外部回路基板表面の電極にロウ材によ
って電気的に接続してなる。なお、外部回路基板は、お
もに、プリント基板の絶縁基材はガラス−エポキシ樹脂
複合材料などのように、有機質材料ないし有機質材料と
無機質材料との複合材で構成される。
On the other hand, such a package is mounted on an external circuit board by mounting a so-called ball grid array (BGA) on the back surface of the package on which the semiconductor element is mounted.
As shown in the above, a connection terminal formed of a solder ball is attached, and the connection terminal is electrically connected to an electrode on the surface of the external circuit board by a brazing material via the connection terminal. In the external circuit board, the insulating base material of the printed board is mainly made of an organic material or a composite material of an organic material and an inorganic material, such as a glass-epoxy resin composite material.

【0010】しかしながら、BGAのような接続端子を
高密度に形成したパッケージの絶縁基板として従来より
使用されているアルミナ、ムライト等のセラミックスを
用いると、上記プリント基板などの外部回路基板に表面
実装した場合、半導体素子の作動時に発する熱が絶縁基
板と外部回路基板の両方に繰り返し印加され、前記外部
回路基板と絶縁基板との熱膨張係数差によって熱応力が
発生し、この応力によって、接続端子が絶縁基板から剥
離したり、接続端子にクラックが生じ、配線基板を外部
回路基板上に長期にわたり安定に維持できないという問
題があった。
However, when ceramics such as alumina and mullite which are conventionally used as an insulating substrate of a package in which connection terminals such as a BGA are formed at a high density are used, they are mounted on an external circuit board such as the above-mentioned printed circuit board. In this case, heat generated during operation of the semiconductor element is repeatedly applied to both the insulating substrate and the external circuit board, and a thermal stress is generated due to a difference in thermal expansion coefficient between the external circuit board and the insulating substrate. There has been a problem that the wiring board cannot be stably maintained on the external circuit board for a long period of time because the wiring board is peeled off from the insulating substrate or cracks occur in the connection terminals.

【0011】そこで、本出願人は、従来のアルミナ、ム
ライト等のセラミックスに変えて、絶縁基板を高熱膨張
セラミック材料によって形成することによってパッケー
ジの絶縁基板と外部回路基板の絶縁基材との熱膨張差を
小さくすることにより接続信頼性を改善することを提案
した(特開平8−279574号、特願平8−3220
38号)。
Therefore, the present applicant has changed the conventional ceramics, such as alumina and mullite, and formed the insulating substrate with a high thermal expansion ceramic material, so that the thermal expansion between the insulating substrate of the package and the insulating base material of the external circuit substrate was improved. It has been proposed to improve the connection reliability by reducing the difference (Japanese Patent Application Laid-Open No. Hei 8-279574, Japanese Patent Application No. Hei 8-3220).
No. 38).

【0012】[0012]

【発明が解決しようとする課題】しかしながら、上記高
熱膨張セラミック材料を絶縁基板として用い、前記特開
平8−264688号公報のように、絶縁基板と同等の
熱膨張係数を有する同じ材質からなるリッドを取り付け
た半導体素子収納用パッケージを前記プリント基板等の
外部回路基板に表面実装した場合、半導体素子の作動停
止による熱サイクルが印加されると、特に冷却過程にお
いてたとえ絶縁基板に高熱膨張ガラスセラミックスを用
いても外部回路基板との熱膨張差は存在するために、絶
縁基板は外部回路基板との実装面が凸となるように撓も
うとするが、絶縁基板は実装面と反対側に強固に接合さ
れたリッドによって拘束されているために絶縁基板はほ
とんど撓むことができない。その結果、外部回路基板の
絶縁基板との実装面が凸となるように撓んでしまう。
However, a lid made of the same material having the same coefficient of thermal expansion as that of the insulating substrate as disclosed in JP-A-8-264688 is used by using the above-mentioned high thermal expansion ceramic material as an insulating substrate. When the mounted semiconductor element storage package is surface-mounted on an external circuit board such as the printed circuit board, when a heat cycle is applied by stopping the operation of the semiconductor element, a high thermal expansion glass ceramic is used for the insulating substrate, especially in a cooling process. However, since there is a difference in thermal expansion with the external circuit board, the insulating substrate tries to bend so that the mounting surface with the external circuit board becomes convex, but the insulating substrate is firmly joined to the opposite side to the mounting surface The insulating substrate can hardly bend because it is restrained by the provided lid. As a result, the mounting surface of the external circuit board with the insulating substrate is bent so as to be convex.

【0013】この撓みは配線基板と外部回路基板との接
続端子のうち、外周に位置する両者の接続部を引き剥が
す方向に作用する結果、接続端子が絶縁基板より剥離し
たり、接続端子にクラックなどが生じ、配線基板を外部
回路基板上に長期にわたり安定に維持できないという欠
点を有していた。
This bending acts in the direction of peeling off the connecting portions of the connection terminals between the wiring board and the external circuit board, which are located on the outer periphery. For example, the wiring board cannot be stably maintained on the external circuit board for a long time.

【0014】従って、本発明では、上記のようなリッド
を具備する半導体素子用パッケージを外部回路基板に実
装した場合においても、強固でかつ長期にわたり安定し
た電気接続を維持させることのできる長期使用信頼性に
顕著に優れた半導体素子用パッケージとその実装構造を
提供することを目的とするものである。
Therefore, according to the present invention, even when a package for a semiconductor device having the above-mentioned lid is mounted on an external circuit board, a long-term reliability which can maintain a strong and stable electric connection for a long period of time. It is an object of the present invention to provide a package for a semiconductor element having remarkably excellent performance and a mounting structure thereof.

【0015】[0015]

【課題を解決するための手段】本発明者らは、表面ある
いは内部にメタライズ配線層が形成された絶縁基板の表
面に接続用電極を備えた半導体素子を載置し、前記メタ
ライズ配線層と前記半導体素子の接続用電極とをロウ付
けしてなるとともに、前記半導体素子を覆うようにして
脚部を有する高熱伝導性蓋体を配置し、前記脚部を前記
絶縁基板の表面に接着固定するとともに、前記高熱伝導
性蓋体の一部を前記半導体素子の上面と接着してなる半
導体素子用パッケージに対して、種々検討した結果、絶
縁基板の40〜150℃における熱膨張係数を8乃至2
0ppm/℃とし、且つ前記高熱伝導性蓋体を前記絶縁
基板表面にヤング率が1GPa以下の低ヤング率の接着
材によって取着固定することにより、外部回路基板に実
装した場合においても、強固でかつ長期にわたり安定し
た電気接続を維持させることのできることを見いだし
た。
Means for Solving the Problems The present inventors place a semiconductor element having connection electrodes on a surface of an insulating substrate having a metallized wiring layer formed on the surface or inside thereof, and connect the metallized wiring layer to the metallized wiring layer. A soldering electrode and a connection electrode of a semiconductor element are formed, and a high thermal conductive lid having legs is arranged so as to cover the semiconductor element, and the legs are bonded and fixed to the surface of the insulating substrate. As a result of various studies on a semiconductor element package in which a part of the high thermal conductive lid is bonded to the upper surface of the semiconductor element, the thermal expansion coefficient of the insulating substrate at 40 to 150 ° C. is 8 to 2
0 ppm / ° C., and the high thermal conductive lid is attached and fixed to the surface of the insulating substrate with a low Young's modulus adhesive having a Young's modulus of 1 GPa or less. It has been found that a stable electrical connection can be maintained for a long time.

【0016】[0016]

【発明の実施の形態】以下、本発明に係わる実施形態に
ついて詳細に説明する。図1は、本発明の半導体素子用
パッケージと、その実装構造の一例を示す概略断面図で
ある。図1は、本発明におけるパッケージとして接続端
子がボール状端子からなるBGA型パッケージを例とし
たものであり、Aは半導体素子、BはBGA型パッケー
ジ、Cは外部回路基板である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments according to the present invention will be described in detail. FIG. 1 is a schematic sectional view showing an example of a semiconductor device package of the present invention and an example of a mounting structure thereof. FIG. 1 shows an example of a BGA type package having connection terminals formed of ball terminals as a package in the present invention, wherein A is a semiconductor element, B is a BGA type package, and C is an external circuit board.

【0017】図1において、パッケージBは、セラミッ
ク絶縁基板1の表面および内部にメタライズ配線層2が
被着形成されており、またパッケージBの底面には、接
続パッド3が形成され、絶縁基板1の表面および内部に
配設されたメタライズ配線層2と電気的に接続されてい
る。この図のBGA型パッケージにおいては、接続パッ
ド3には、ボール状の接続端子4が半田により接続され
ている。
In FIG. 1, a package B has a metallized wiring layer 2 formed on the surface and inside of a ceramic insulating substrate 1, and a connection pad 3 is formed on the bottom surface of the package B. Is electrically connected to the metallized wiring layer 2 disposed on the surface and inside. In the BGA type package of this figure, ball-shaped connection terminals 4 are connected to the connection pads 3 by soldering.

【0018】一方、外部回路基板Cは、いわゆるプリン
ト基板からなり、ガラス−エポキシ樹脂、ガラス−ポリ
イミド樹脂複合材料などの有機樹脂を含む材料からなる
樹脂基板5の表面に、Cu、Au、Al、Ni、Pb−
Snなどの金属からなる接続導体6が被着形成されたも
のである。
On the other hand, the external circuit board C is made of a so-called printed board, and Cu, Au, Al, Al, Al, Al, Al, and Al are formed on the surface of a resin substrate 5 made of a material containing an organic resin such as a glass-epoxy resin or a glass-polyimide resin composite material. Ni, Pb-
A connection conductor 6 made of a metal such as Sn is adhered and formed.

【0019】そして、この外部回路基板Cの接続導体6
にパッケージBのボール状の接続端子4が半田7などに
より接続されて、パッケージBが外部回路基板Cの表面
に実装されている。
The connection conductor 6 of the external circuit board C
The package B is mounted on the surface of the external circuit board C by connecting the ball-shaped connection terminals 4 of the package B with solder 7 or the like.

【0020】パッケージBを構成する絶縁基板1は、−
40℃〜150℃における熱膨張係数が8乃至20pp
m/℃のセラミックスから構成される。これは、有機樹
脂を含む樹脂基板5を具備する外部回路基板Cとの長期
接続信頼性を得るために必要である。よって、絶縁基板
1の熱膨張係数が8ppm/℃よりも小さいか、あるい
は20ppm/℃よりも大きいと、外部回路基板Cとの
熱膨張差が大きくなり、熱膨張差に起因する応力によっ
て接続信頼性が損なわれるためである。
The insulating substrate 1 constituting the package B is
The coefficient of thermal expansion at 40 ° C to 150 ° C is 8 to 20 pp
It is composed of m / C ceramics. This is necessary to obtain long-term connection reliability with the external circuit board C having the resin substrate 5 containing an organic resin. Therefore, when the coefficient of thermal expansion of the insulating substrate 1 is smaller than 8 ppm / ° C. or larger than 20 ppm / ° C., the difference in thermal expansion with the external circuit board C increases, and the connection reliability is increased due to the stress caused by the difference in thermal expansion. This is because the property is impaired.

【0021】また、パッケージBの表面に実装される半
導体素子Aの底面に複数の接続用電極8が設けられてお
り、パッケージBの表面のメタライズ配線層2と半田な
どのロウ材からなる接続端子9により電気的に接続され
ており、その周りには通常、熱硬化性樹脂からなるアン
ダーフィル材10が充填され、補強されている。
A plurality of connection electrodes 8 are provided on the bottom surface of the semiconductor element A mounted on the surface of the package B, and the metallized wiring layer 2 on the surface of the package B and connection terminals made of a brazing material such as solder. The underfill material 10 is made of a thermosetting resin, and is electrically reinforced.

【0022】本発明によれば、半導体素子Aのパッケー
ジBへの実装面の反対側の面には、高熱伝導性蓋体(以
下、単にリッドという。)12が高熱伝導性樹脂によっ
て接着されている。さらにはリッド12は、リッド12
の脚部12aをもって、絶縁基板1の表面に接着材13
によって取着固定されている。
According to the present invention, a high thermal conductive lid (hereinafter, simply referred to as a lid) 12 is adhered to the surface opposite to the surface on which the semiconductor element A is mounted on the package B by a high thermal conductive resin. I have. Further, the lid 12 is the lid 12
Of the adhesive 13 on the surface of the insulating substrate 1
It is attached and fixed by.

【0023】このような半導体素子収納用パッケージ構
造において、リッド12の脚部12aを絶縁基板1に取
着するための接着材13のヤング率が高いと、前記絶縁
基板1と前記リッド12との接着が強固、且つ拘束力が
高まり、温度サイクル試験において前記絶縁基板1と前
記外部回路基板Cとの熱膨張係数差により外部回路基板
Cには撓みが発生するが、絶縁基板1はリッド12によ
って拘束されている結果、絶縁基板1は撓むことができ
ず、前記回路基板Cと絶縁基板1との接続部に応力が集
中し、絶縁基板1と外部回路基板Cとの接続が不安定に
なる。
In such a semiconductor device housing package structure, if the Young's modulus of the adhesive 13 for attaching the leg 12a of the lid 12 to the insulating substrate 1 is high, the insulating substrate 1 and the lid 12 may be in contact with each other. The adhesion is strong, the binding force is increased, and in the temperature cycle test, the external circuit board C bends due to the difference in thermal expansion coefficient between the insulating substrate 1 and the external circuit board C. As a result of the restraint, the insulating substrate 1 cannot bend, stress is concentrated on the connection portion between the circuit substrate C and the insulating substrate 1, and the connection between the insulating substrate 1 and the external circuit substrate C becomes unstable. Become.

【0024】そこで、本発明によれば、接着材13のヤ
ング率を1GPa以下、特に0.5GPa以下と小さく
することにより、パッケージBの絶縁基板1へかかるリ
ッド12の応力を吸収低減させることによって絶縁基板
1と外部回路基板Cとの接続部に作用する応力を低減す
ることができるものである。
Therefore, according to the present invention, the stress of the lid 12 applied to the insulating substrate 1 of the package B is reduced by reducing the Young's modulus of the adhesive 13 to 1 GPa or less, especially 0.5 GPa or less. It is possible to reduce the stress acting on the connection between the insulating substrate 1 and the external circuit board C.

【0025】この接着材13はリッド12を絶縁基板1
に接着させるという役割上、強い接着性を有することが
望まれる。具体的には、エポキシ系樹脂、シリコーン系
樹脂メラミン系樹脂、エステル系樹脂の群から選ばれる
少なくとも1種の熱硬化性樹脂を含有することが望まし
く、さらには、上記樹脂分に対して、ガラスクロス、球
状シリカ、アルミナの群から選ばれる少なくとも1種の
無機フィラーと複合化させたものでもよい。
The adhesive 13 is used to attach the lid 12 to the insulating substrate 1.
It is desired to have a strong adhesive property in the role of bonding to the substrate. Specifically, it is desirable to contain at least one thermosetting resin selected from the group consisting of an epoxy-based resin, a silicone-based resin, a melamine-based resin, and an ester-based resin. It may be a composite formed with at least one inorganic filler selected from the group consisting of cloth, spherical silica, and alumina.

【0026】一方、リッド12は半導体素子の発熱する
熱を外部に放熱するという役割上、高熱伝導性を有する
ことが望まれる。具体的には、Al−SiC複合材料
(AlSiC)、Cu−W合金、Cu、Fe−Ni−C
o合金、Cu−Cr合金、Alのうち1種を挙げること
ができ、放熱量、放熱フィン15の取着の有無に合わせ
て、便宜選択使用する。
On the other hand, the lid 12 is desired to have high thermal conductivity in order to radiate heat generated by the semiconductor element to the outside. Specifically, Al-SiC composite material (AlSiC), Cu-W alloy, Cu, Fe-Ni-C
One of o alloy, Cu-Cr alloy, and Al can be cited, and it is conveniently used depending on the amount of heat radiation and whether or not the heat radiation fins 15 are attached.

【0027】また、上記の半導体素子収納用パッケージ
構造および実装構造における熱膨張差に起因する応力を
低減する上では、リッド12を絶縁基板1より熱膨張係
数の低い材質によって形成し、リッド12<絶縁基板1
<樹脂基板5の順に熱膨張係数が大きくなるように組み
合わせることが望ましい。
In order to reduce the stress caused by the difference in thermal expansion between the package structure for mounting a semiconductor element and the mounting structure, the lid 12 is formed of a material having a lower coefficient of thermal expansion than the insulating substrate 1. Insulating substrate 1
<It is desirable to combine the resin substrates 5 so that the coefficient of thermal expansion increases in this order.

【0028】半導体素子の上面とリッド12とを接続す
る高熱伝導性接着材としては、エポキシ系樹脂が好適で
ある。
As a highly heat conductive adhesive for connecting the upper surface of the semiconductor element and the lid 12, an epoxy resin is preferable.

【0029】さらに、本発明によれば、リッド12に
は、絶縁基板1への取付けのために脚部12aが設けら
れているが、この脚部12aの絶縁基板1への取付け位
置は、図2の平面図に示すように、絶縁基板1の裏面に
配設された複数の接続端子4のうち、最外部に設けられ
た接続端子4aよりも内側の領域、詳細には、最外部に
位置する接続端子4aを結ぶ線分xで囲まれた領域より
も内側であることが望ましい。
Further, according to the present invention, the lid 12 is provided with the legs 12a for mounting to the insulating substrate 1, and the mounting position of the legs 12a to the insulating substrate 1 is shown in FIG. As shown in the plan view of FIG. 2, of the plurality of connection terminals 4 arranged on the back surface of the insulating substrate 1, a region inside the connection terminal 4 a provided on the outermost side, more specifically, located on the outermost side. It is preferable that the inner side be inside a region surrounded by a line segment x connecting the connecting terminals 4a to be connected.

【0030】これは、リッド12の脚部12aの下に最
大の応力が発生しており、また、絶縁基板1と外部配線
基板5の間の最大応力が接続端子4aに発生することか
ら、リッド12の脚部12aの取付け箇所を線分Xより
内側に取り付けることによりこれらの応力の集中を避け
ることによって応力を分散させることができる。
This is because the maximum stress is generated below the leg 12a of the lid 12 and the maximum stress between the insulating substrate 1 and the external wiring substrate 5 is generated at the connection terminal 4a. By attaching the attachment portions of the twelve legs 12a inside the line segment X, it is possible to disperse the stress by avoiding the concentration of these stresses.

【0031】なお、本発明におけるパッケージBの熱膨
張係数が8乃至20ppm/℃である絶縁基板1は、本
発明者らが先に提案した、例えば、BaOを5乃至60
重量%の割合で含有する低軟化点、高熱膨張のガラスを
用いて、所定のフィラーとを混合し焼成した高熱膨張性
を有し、しかも1000℃以下の低温でCuなどの低抵
抗金属と同時焼成可能なガラスセラミック焼結体からな
る。その他、特願平8−322038号の明細書中に記
載されているような、例えば、リチウム珪酸系ガラス、
PbO系ガラス、ZnO系ガラス、BaO系ガラス等の
ガラス成分にエンスタタイト、フォルステライト、フォ
ルステライトとSiO2系フィラー、MgO、ZrO2
ペタライト等の各種セラミックフィラーの複合材料によ
って形成される。
The insulating substrate 1 according to the present invention, in which the package B has a coefficient of thermal expansion of 8 to 20 ppm / ° C., is made of, for example, BaO of 5 to 60 as proposed by the present inventors.
Using a glass with low softening point and high thermal expansion contained in a proportion of weight%, it has a high thermal expansion property obtained by mixing with a predetermined filler and firing, and at the same time as a low resistance metal such as Cu at a low temperature of 1000 ° C or less. It consists of a sinterable glass ceramic sintered body. In addition, as described in the specification of Japanese Patent Application No. 8-322038, for example, lithium silicate glass,
Enstatite, forsterite, forsterite and SiO 2 filler, MgO, ZrO 2 , glass components such as PbO-based glass, ZnO-based glass, BaO-based glass,
It is formed of a composite material of various ceramic fillers such as petalite.

【0032】例えば、上記ガラスに20乃至90体積
%、上記フィラー80乃至10体積%の割合で混合した
混合粉末に、適宜有機バインダーを添加してスラリーを
作製し、そのスラリーをシート状に成形した後、そのシ
ート状成形体の表面に、Cu、Au、Agなどの低抵抗
金属を含む導体ペーストを印刷塗布する。また、所望に
より、シート状成形体の所定箇所にパンチングやレーザ
ー等によりスルーホールを形成して、スルーホール内に
前記導体ペーストを充填する。そして、そのシート状成
形体を積層圧着して積層体を作製した後、これを大気中
あるいは窒素雰囲気で800乃至1000℃で焼成する
ことにより絶縁基板を作製することができる。
For example, a slurry is prepared by appropriately adding an organic binder to a mixed powder obtained by mixing 20 to 90% by volume of the glass and 80 to 10% by volume of the filler, and the slurry is formed into a sheet. Thereafter, a conductor paste containing a low-resistance metal such as Cu, Au, or Ag is printed and applied to the surface of the sheet-shaped molded body. If desired, a through hole is formed at a predetermined position of the sheet-like molded body by punching, laser, or the like, and the conductive paste is filled in the through hole. Then, the sheet-shaped molded body is laminated and pressed to produce a laminated body, which is then fired at 800 to 1000 ° C. in the air or a nitrogen atmosphere to produce an insulating substrate.

【0033】また、絶縁基板表面に、いわゆる薄膜法に
よる低抵抗金属膜を形成し、ポジ型フォトレジストを用
いたフォトリソグラフィー技術により、微細配線を有す
る絶縁基板を作製することもできる。
Also, a low-resistance metal film is formed on the surface of the insulating substrate by a so-called thin film method, and an insulating substrate having fine wiring can be manufactured by photolithography using a positive photoresist.

【0034】また、上記リッド12の上面には、所望に
より、図1に示すように、エポキシ樹脂等の接着材14
を用いて放熱フィン15を取着して、半導体素子Aから
発生した熱をさらに効率的に放熱させることもできる。
As shown in FIG. 1, an adhesive 14 such as an epoxy resin may be provided on the upper surface of the lid 12 if desired.
The heat generated from the semiconductor element A can be more efficiently radiated by attaching the radiating fins 15 by using.

【0035】[0035]

【実施例】表1に示す各種セラミック材料について、5
mm×4mm×40mmの形状のセラミック焼結体を作
製した後、各焼結体について熱膨張係数を測定した。測
定値を表1に示す。
EXAMPLES For various ceramic materials shown in Table 1, 5
After preparing a ceramic sintered body having a shape of mm × 4 mm × 40 mm, the coefficient of thermal expansion of each sintered body was measured. Table 1 shows the measured values.

【0036】[0036]

【表1】 [Table 1]

【0037】また、表1に示す各種セラミック焼結体を
絶縁基板として用いて、それらに銅からなるメタライズ
配線層及びスルーホール導体を形成し、また、パッケー
ジ上面のスルーホール導体に接続する個所に半導体素子
と接続される多数の電極パッドを形成し、さらに底面に
は、外部回路基板と接続するための接続パッドを形成
し、メタライズ配線層、スルーホール導体、電極パッ
ド、接続パッドとともに、絶縁基板と窒素雰囲気中で9
50℃で同時焼成してパッケージを作製した。
Further, using the various ceramic sintered bodies shown in Table 1 as an insulating substrate, a metallized wiring layer made of copper and a through-hole conductor are formed thereon, and the ceramic sintered body is connected to the through-hole conductor on the upper surface of the package. A large number of electrode pads to be connected to the semiconductor element are formed, and further, on the bottom surface, connection pads for connection to an external circuit board are formed, and a metallized wiring layer, through-hole conductors, electrode pads, connection pads, and an insulating substrate are formed. And 9 in a nitrogen atmosphere
A package was prepared by simultaneous firing at 50 ° C.

【0038】そして、パッケージの底面の接続パッド
に、高融点半田(Sn:Pb重量比=10:90)から
なる1444個のボール状の接続端子を低融点半田(S
n:Pb重量比=63:37)により取り付けてパッケ
ージを作製した。作製したパッケージは、縦×横×厚み
を40mm×40mm×1mmとし、接続端子は、絶縁
基板の裏面の38mm×38mmの領域に取り付けた。
Then, 1444 ball-shaped connection terminals made of high melting point solder (Sn: Pb weight ratio = 10: 90) are connected to the connection pads on the bottom surface of the package with low melting point solder (S
n: Pb weight ratio = 63: 37) to produce a package. The prepared package had a length × width × thickness of 40 mm × 40 mm × 1 mm, and connection terminals were attached to a region of 38 mm × 38 mm on the back surface of the insulating substrate.

【0039】そして、電極パッドにNiメッキを施した
後、電極パッドに対して、0乃至100℃における熱膨
張係数が2.8ppm/℃のSiからなる半導体素子を
準備し、半導体素子の底面に配設された接続用電極を低
融点半田により接続して実装した後、半導体素子とパッ
ケージとの間の空隙にアンダーフィル材(エポキシ樹
脂)を注入し、180℃で2時間熱処理して硬化させて
半導体素子をパッケージに固着した。
After the electrode pads are plated with Ni, a semiconductor element made of Si having a thermal expansion coefficient of 2.8 ppm / ° C. at 0 to 100 ° C. is prepared for the electrode pads. After the connection electrodes provided are connected by low-melting point solder and mounted, an underfill material (epoxy resin) is injected into the gap between the semiconductor element and the package, and heat-treated at 180 ° C. for 2 hours to be cured. Thus, the semiconductor element was fixed to the package.

【0040】一方、SiCに対してAlを30重量%含
有する高熱伝導体からなるリッドを準備した。このリッ
ドは、0〜100℃における熱膨張係数が7×10-6
℃であり、ヤング率が300GPaであった。なお、リ
ッドの平面的なサイズは、35mm×35mmである
(接続端子取付け領域よりも狭くすること)。
On the other hand, a lid made of a high thermal conductor containing 30% by weight of Al with respect to SiC was prepared. This lid has a thermal expansion coefficient of 7 × 10 −6 / 0 to 100 ° C.
° C and the Young's modulus was 300 GPa. Note that the planar size of the lid is 35 mm × 35 mm (narrower than the connection terminal attachment area).

【0041】その後、パッケージの上面に実装された半
導体素子の上面に高熱伝導性樹脂(シリコーン樹脂)を
塗布し、さらに、リッドの脚部の先端と、絶縁基板の取
付け部に表2からなる接着材を塗布した後、上記リッド
を位置合わせして接着し、150℃で硬化させて接着固
定した。
Thereafter, a high thermal conductive resin (silicone resin) is applied to the upper surface of the semiconductor element mounted on the upper surface of the package, and further, the bonding shown in Table 2 is applied to the tip of the leg of the lid and the mounting portion of the insulating substrate. After applying the material, the lid was aligned and bonded, and cured at 150 ° C. and fixed.

【0042】この時のリッドの脚部の絶縁基板への取付
け位置は、図2に示すように、絶縁基板裏面の接続端子
取付け部の最外部に位置する接続端子よりも内側領域に
接着固定した。
At this time, the mounting positions of the legs of the lid to the insulating substrate were, as shown in FIG. 2, adhered and fixed to a region inside the connecting terminals located on the outermost side of the connecting terminal mounting portion on the back surface of the insulating substrate. .

【0043】そして、この半導体素子及びリッドを設け
たパッケージを、ガラスエポキシ基板からなる−40乃
至125℃における熱膨張係数が20ppm/℃の樹脂
基板の表面に銅箔からなる接続導体が形成されたプリン
ト基板に対して、パッケージのボール状の接続端子と、
プリント基板の接続導体とが接続されるように位置あわ
せして低融点半田を用いて窒素雰囲気中で240℃で3
分間熱処理してパッケージをプリント基板の表面に実装
した。
A connection conductor made of copper foil was formed on the surface of a resin substrate having a thermal expansion coefficient of 20 ppm / ° C. at −40 to 125 ° C. made of a glass epoxy substrate. With respect to the printed circuit board, the ball-shaped connection terminals of the package,
It is positioned at 240 ° C. in a nitrogen atmosphere using low-melting-point solder at a temperature of 240 ° C. so as to be connected to the connection conductor of the printed circuit board.
The package was mounted on the surface of the printed circuit board by heat treatment for minutes.

【0044】(温度サイクル試験)上記のようにパッケ
ージをプリント基板表面に実装したものを大気雰囲気に
て−40℃と125℃の各温度に制御した高温槽に試験
サンプルを15分/15分の保持を1サイクルとして最
高2000サイクル繰り返した。そして、100サイク
ル毎にプリント基板の接続とパッケージとの電気抵抗を
測定し電気抵抗に変化が生じるまでのサイクル数を表2
に示した。
(Temperature Cycle Test) The test sample was placed in a high-temperature bath controlled at -40 ° C. and 125 ° C. in an air atmosphere in a state in which the package was mounted on the printed circuit board surface as described above, and the test sample was subjected to 15 minutes / 15 minutes. Up to 2000 cycles were repeated with one cycle of holding. Then, the electrical resistance between the connection of the printed circuit board and the package is measured every 100 cycles, and the number of cycles until the electrical resistance changes is shown in Table 2.
It was shown to.

【0045】[0045]

【表2】 [Table 2]

【0046】[0046]

【表3】 [Table 3]

【0047】表2、表3からも明らかなように本発明で
ある絶縁基板とリッドの接着材のヤング率が1GPa以
下の場合では、2000回までの熱サイクル試験におい
てパッケージとプリント基板との間に電気抵抗変化は全
く見られず、極めて安定で良好な電気的接続を維持し
た。
As is clear from Tables 2 and 3, when the Young's modulus of the adhesive between the insulating substrate and the lid according to the present invention is 1 GPa or less, the distance between the package and the printed circuit board in a thermal cycle test up to 2000 times is possible. No electrical resistance change was observed at all, and an extremely stable and good electrical connection was maintained.

【0048】上記以外の試料No.1〜3、8〜10、
15〜17、22〜24、29〜31(本発明外の試
料)では熱サイクル試験2000サイクル未満でパッケ
ージとプリント基板との間に電気抵抗変化が見られ、パ
ッケージとプリント基板の接続部でボール状の接続端子
が絶縁基板から剥離したり、接続部にクラックなどが生
じた。
Sample Nos. Other than the above 1-3, 8-10,
In 15 to 17, 22 to 24, and 29 to 31 (samples other than the present invention), a change in electric resistance was observed between the package and the printed circuit board in less than 2000 cycles of the thermal cycle test. Connection terminals peeled off from the insulating substrate, and cracks occurred in the connection portions.

【0049】[0049]

【発明の効果】上述した通り、本発明よれば、パッケー
ジの絶縁基板とリッドとを取着するための接着材とし
て、ヤング率1GPa以下の接着材を使用することによ
り、パッケージと外部回路基板との熱膨張差により接続
部に作用する応力を低減することができる。これによ
り、パッケージと外部回路基板との間で接続不良を起こ
すことが無く、長期にわたり確実で強固な電気的接続を
保持させることができる。
As described above, according to the present invention, by using an adhesive having a Young's modulus of 1 GPa or less as an adhesive for attaching the insulating substrate and the lid of the package, the package and the external circuit board can be connected to each other. Can reduce the stress acting on the connecting portion due to the difference in thermal expansion between the two. Thus, a connection failure between the package and the external circuit board does not occur, and a reliable and strong electrical connection can be maintained for a long time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子用パッケージの一実施態様
としてBGA型の半導体素子用パッケージとその実装構
造を説明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a BGA type semiconductor element package and its mounting structure as one embodiment of a semiconductor element package of the present invention.

【図2】本発明の半導体素子収納用パッケージにおける
リッドの取付け位置を説明するための平面図である。
FIG. 2 is a plan view for explaining a mounting position of a lid in the package for housing a semiconductor element of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 メタライズ配線層 3 接続パッド 4 接続端子 5 樹脂基板 6 配線導体 7 半田 8 接続用電極 9 接続端子 10 アンダーフィル材 11 高熱伝導性樹脂 12 高熱伝導性蓋体 13 接着材 14 接着材 15 放熱フィン A 半導体素子 B パッケージ C 外部回路基板 REFERENCE SIGNS LIST 1 insulating substrate 2 metallized wiring layer 3 connection pad 4 connection terminal 5 resin substrate 6 wiring conductor 7 solder 8 connection electrode 9 connection terminal 10 underfill material 11 high heat conductive resin 12 high heat conductive lid 13 adhesive material 14 adhesive material 15 Heat radiation fin A Semiconductor element B Package C External circuit board

Claims (14)

【特許請求の範囲】[Claims] 【請求項1】表面あるいは内部にメタライズ配線層が形
成された絶縁基板の表面に接続用電極を備えた半導体素
子を載置し、前記メタライズ配線層と前記半導体素子の
接続用電極とをロウ付けしてなるとともに、前記半導体
素子を覆うようにして脚部を有する高熱伝導性蓋体を配
置し、前記脚部を前記絶縁基板の表面に接着固定すると
ともに、前記高熱伝導性蓋体の一部を前記半導体素子の
上面と接着してなる半導体素子用パッケージであって、
前記絶縁基板の40〜150℃における熱膨張係数が8
乃至20ppm/℃であり、且つ前記高熱伝導性蓋体の
脚部をヤング率が1GPa以下の接着材によって前記絶
縁基板表面に取着固定してなることを特徴とする半導体
素子用パッケージ。
1. A semiconductor device provided with a connection electrode on a surface of an insulating substrate having a metallized wiring layer formed on the surface or inside thereof, and the metallized wiring layer and the connection electrode of the semiconductor device are brazed. A high thermal conductive lid having legs is arranged so as to cover the semiconductor element, and the legs are adhesively fixed to the surface of the insulating substrate, and a part of the high thermal conductive lid is provided. A semiconductor device package formed by adhering to the upper surface of the semiconductor device,
The thermal expansion coefficient of the insulating substrate at 40 to 150 ° C. is 8
A package for a semiconductor element, wherein the leg of the high thermal conductive lid is fixed to the surface of the insulating substrate with an adhesive having a Young's modulus of 1 GPa or less.
【請求項2】前記絶縁基板の裏面に、前記メタライズ配
線層を介して前記半導体素子と電気的に接続された複数
の接続端子が取着されており、平面的にみて前記複数の
接続端子の最外の接続端子取着位置よりも内側の領域に
て、前記高熱伝導性蓋体の脚部が前記絶縁基板表面に取
り付けられていることを特徴とする請求項1記載の半導
体素子用パッケージ。
2. A plurality of connection terminals which are electrically connected to the semiconductor element via the metallized wiring layer are attached to a back surface of the insulating substrate. 2. The semiconductor device package according to claim 1, wherein a leg portion of the high thermal conductive lid is attached to a surface of the insulating substrate in a region inside the outermost connection terminal attachment position.
【請求項3】前記半導体素子の上面を、高熱伝導性接着
材によって前記高熱伝導性蓋体に接着してなる請求項1
または請求項2記載の半導体素子用パッケージ。
3. The semiconductor device according to claim 1, wherein an upper surface of the semiconductor element is bonded to the high thermal conductive lid with a high thermal conductive adhesive.
A package for a semiconductor device according to claim 2.
【請求項4】前記高熱伝導性蓋体の上面に、放熱フィン
を接合してなる請求項1乃至請求項3記載の半導体素子
用パッケージ。
4. The package for a semiconductor device according to claim 1, wherein a radiating fin is joined to an upper surface of the high thermal conductive lid.
【請求項5】前記高熱伝導性蓋体が、アルミニウムとS
iCとの複合材料、またはCuからなることを特徴とす
る請求項1乃至請求項4のいずれか記載の半導体素子用
パッケージ。
5. The high thermal conductive lid is made of aluminum and sulfur.
The semiconductor device package according to any one of claims 1 to 4, wherein the package is made of a composite material with iC or Cu.
【請求項6】前記絶縁基板が、ガラスセラミックスから
なり、前記メタライズ配線層が銅を主成分とする導体か
らなることを特徴とする請求項1乃至請求項5のいずれ
か記載の半導体素子用パッケージ。
6. The package for a semiconductor device according to claim 1, wherein said insulating substrate is made of glass ceramic, and said metallized wiring layer is made of a conductor containing copper as a main component. .
【請求項7】前記半導体素子が前記絶縁基板表面のメタ
ライズ配線層に、フリップチップ実装してなる請求項1
乃至請求項6のいずれか記載の半導体素子用パッケー
ジ。
7. The semiconductor device according to claim 1, wherein said semiconductor element is flip-chip mounted on a metallized wiring layer on a surface of said insulating substrate.
A package for a semiconductor device according to claim 6.
【請求項8】表面あるいは内部にメタライズ配線層が形
成された絶縁基板の表面に接続用電極を備えた半導体素
子を載置し、前記メタライズ配線層と前記半導体素子の
接続用電極とをロウ付けしてなるとともに、前記半導体
素子を覆うようにして脚部を有する高熱伝導性蓋体を配
置し、前記脚部を前記絶縁基板の表面に接着固定すると
ともに、前記高熱伝導性蓋体の一部を前記半導体素子の
上面と接着してなり、且つ前記絶縁基板裏面に設けられ
前記半導体素子と前記メタライズ配線層を介して電気的
に接続された接続端子を具備する半導体素子用パッケー
ジを、有機樹脂を含有する樹脂基板を備えた外部回路基
板表面に実装してなる実装構造であって、 前記絶縁基板の40〜150℃における熱膨張係数が8
乃至20ppm/℃であり、且つ前記高熱伝導性蓋体の
脚部をヤング率が1GPa以下の接着材によって前記絶
縁基板表面に取着固定してなることを特徴とする半導体
素子用パッケージの実装構造。
8. A semiconductor device provided with a connection electrode on a surface of an insulating substrate having a metallized wiring layer formed on the surface or inside thereof, and brazing the metallized wiring layer and the connection electrode of the semiconductor device. A high thermal conductive lid having legs is arranged so as to cover the semiconductor element, and the legs are adhesively fixed to the surface of the insulating substrate, and a part of the high thermal conductive lid is provided. A semiconductor element package having a connection terminal provided on the back surface of the insulating substrate and having a connection terminal electrically connected to the semiconductor element via the metallized wiring layer. A mounting structure formed on a surface of an external circuit board provided with a resin substrate containing: wherein the insulating substrate has a coefficient of thermal expansion at 40 to 150 ° C. of 8
Wherein the leg of the high thermal conductive lid is fixed to the surface of the insulating substrate with an adhesive having a Young's modulus of 1 GPa or less. .
【請求項9】平面的にみて前記複数の接続端子の最外の
接続端子取着位置よりも内側の領域にて、前記高熱伝導
性蓋体の脚部が前記絶縁基板表面に取り付けられている
ことを特徴とする請求項8記載の半導体素子用パッケー
ジの実装構造。
9. A leg portion of the high thermal conductive lid is attached to the surface of the insulating substrate in a region inside the outermost connection terminal mounting position of the plurality of connection terminals when viewed in plan. The mounting structure of a package for a semiconductor device according to claim 8, wherein:
【請求項10】前記半導体素子の上面を、高熱伝導性接
着材によって前記高熱伝導性蓋体に接着してなる請求項
8または請求項9記載の半導体素子用パッケージの実装
構造。
10. The semiconductor element package mounting structure according to claim 8, wherein an upper surface of said semiconductor element is bonded to said high heat conductive lid with a high heat conductive adhesive.
【請求項11】前記高熱伝導性蓋体の上面に、放熱フィ
ンを接合してなる請求項8乃至請求項10記載の半導体
素子用パッケージの実装構造。
11. The mounting structure for a semiconductor element package according to claim 8, wherein a heat radiation fin is joined to an upper surface of said high thermal conductive lid.
【請求項12】前記高熱伝導性蓋体が、アルミニウムと
SiCとの複合材料、またはCuからなることを特徴と
する請求項8乃至請求項11のいずれか記載の半導体素
子用パッケージの実装構造。
12. The package structure for a semiconductor element package according to claim 8, wherein said high thermal conductive lid is made of a composite material of aluminum and SiC, or Cu.
【請求項13】前記絶縁基板が、ガラスセラミックスか
らなり、前記メタライズ配線層が銅を主成分とする導体
からなることを特徴とする請求項8乃至請求項12のい
ずれか記載の半導体素子用パッケージの実装構造。
13. The semiconductor device package according to claim 8, wherein said insulating substrate is made of glass ceramic, and said metallized wiring layer is made of a conductor containing copper as a main component. Mounting structure.
【請求項14】前記半導体素子を前記絶縁基板表面のメ
タライズ配線層に、フリップチップ実装してなる請求項
8乃至請求項13のいずれか記載の半導体素子用パッケ
ージの実装構造。
14. The package structure for a semiconductor element package according to claim 8, wherein said semiconductor element is flip-chip mounted on a metallized wiring layer on a surface of said insulating substrate.
JP2000054003A 2000-02-29 2000-02-29 Package for semiconductor device and mounting structure Pending JP2001244390A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000054003A JP2001244390A (en) 2000-02-29 2000-02-29 Package for semiconductor device and mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000054003A JP2001244390A (en) 2000-02-29 2000-02-29 Package for semiconductor device and mounting structure

Publications (1)

Publication Number Publication Date
JP2001244390A true JP2001244390A (en) 2001-09-07

Family

ID=18575314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000054003A Pending JP2001244390A (en) 2000-02-29 2000-02-29 Package for semiconductor device and mounting structure

Country Status (1)

Country Link
JP (1) JP2001244390A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008214692A (en) * 2007-03-02 2008-09-18 Furukawa Electric Co Ltd:The Copper alloy wire for metallic container for storing semiconductor
JP2009532892A (en) * 2006-04-06 2009-09-10 バレオ・エチユード・エレクトロニク In particular a stand for power electronics components, a power module comprising such a stand, an assembly comprising a module, and an electrical member controlled by said module
JPWO2011074221A1 (en) * 2009-12-14 2013-04-25 パナソニック株式会社 Semiconductor device
WO2024051275A1 (en) * 2022-09-05 2024-03-14 华为技术有限公司 Case package, packaging assembly, and lidar transmitting module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009532892A (en) * 2006-04-06 2009-09-10 バレオ・エチユード・エレクトロニク In particular a stand for power electronics components, a power module comprising such a stand, an assembly comprising a module, and an electrical member controlled by said module
JP2008214692A (en) * 2007-03-02 2008-09-18 Furukawa Electric Co Ltd:The Copper alloy wire for metallic container for storing semiconductor
JPWO2011074221A1 (en) * 2009-12-14 2013-04-25 パナソニック株式会社 Semiconductor device
WO2024051275A1 (en) * 2022-09-05 2024-03-14 华为技术有限公司 Case package, packaging assembly, and lidar transmitting module

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