JPH11274356A - Surface mounting type electronic component and its mounting method - Google Patents

Surface mounting type electronic component and its mounting method

Info

Publication number
JPH11274356A
JPH11274356A JP7209598A JP7209598A JPH11274356A JP H11274356 A JPH11274356 A JP H11274356A JP 7209598 A JP7209598 A JP 7209598A JP 7209598 A JP7209598 A JP 7209598A JP H11274356 A JPH11274356 A JP H11274356A
Authority
JP
Japan
Prior art keywords
electrodes
bga
electronic component
bump
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7209598A
Other languages
Japanese (ja)
Other versions
JP3862120B2 (en
Inventor
Tatsuo Ietomi
辰夫 家富
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7209598A priority Critical patent/JP3862120B2/en
Publication of JPH11274356A publication Critical patent/JPH11274356A/en
Application granted granted Critical
Publication of JP3862120B2 publication Critical patent/JP3862120B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of connection practically adequately by providing a plurality of dummy bumps at the same height as a bump in at least a plurality of places, which are not on the same straight line of one surface. SOLUTION: A dummy bump 11 is formed of solder whose practical melting point is higher than a melting point of each bump 2B, and heat resistance guaranteed temperature is equal to that of a ball grid array(BGA) 10 and is formed by screen print through method, etc., respectively in four or more places on one surface of a printed wiring board 2 at the same height and configuration as each bump 2B. As a result, in the BGA 10, each dummy bump 11 and each land 6C of a motherboard 6 corresponding thereto come into direct contact with each other and can be mounted on the motherboard 6, since each bump 2B is conductivity connected through a creamy solder 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【目次】以下の順序で本発明を説明する。[Table of Contents] The present invention will be described in the following order.

【0002】発明の属する技術分野 従来の技術(図5〜図7) 発明が解決しようとする課題(図5〜図7) 課題を解決するための手段 発明の実施の形態 (1)本実施の形態によるBGAの構成(図1) (2)本実施の形態によるBGAの実装方法(図2) (3)本実施の形態の動作及び効果(図1〜図3) (4)他の実施の形態(図4) 発明の効果BACKGROUND OF THE INVENTION Prior Art (FIGS. 5 to 7) Problems to be Solved by the Invention (FIGS. 5 to 7) Means for Solving the Problems Embodiments of the Invention (1) This embodiment Configuration of BGA According to Embodiment (FIG. 1) (2) Method of Mounting BGA According to Embodiment (FIG. 2) (3) Operation and Effect of Embodiment (FIGS. 1 to 3) (4) Other Embodiments Form (FIG. 4) Effect of the Invention

【0003】[0003]

【発明の属する技術分野】本発明は表面実装型電子部品
及びその実装方法に関し、例えばBGA(Ball Grid Ar
ray )に適用して好適である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type electronic component and a mounting method thereof, for example, a BGA (Ball Grid Arrangement).
ray).

【0004】[0004]

【従来の技術】従来、この種の表面実装型電子部品とし
て例えば図5に示すようなBGA1が広く知られてい
る。
2. Description of the Related Art Conventionally, for example, a BGA 1 as shown in FIG. 5 has been widely known as this kind of surface mount type electronic component.

【0005】このBGA1は、プリント配線板2の一面
2A上に複数のバンプ2Bが形成される一方他面2C上
にパツド2Dが複数形成されると共に半導体チツプ3が
配設され、当該半導体チツプ3の各電極3Aと各パツド
2Dとがワイヤ4により導通接続される。そして各パツ
ド2D、ワイヤ4及び半導体チツプ3を覆うようにプリ
ント配線板2の他面2C上に、例えばエポキシ系の絶縁
樹脂等からなる封止樹脂5を供給することにより構成さ
れている。
In this BGA 1, a plurality of bumps 2B are formed on one surface 2A of a printed wiring board 2, while a plurality of pads 2D are formed on another surface 2C, and a semiconductor chip 3 is provided. Each electrode 3A and each pad 2D are electrically connected by a wire 4. Then, a sealing resin 5 made of, for example, an epoxy-based insulating resin is supplied onto the other surface 2C of the printed wiring board 2 so as to cover the pads 2D, the wires 4, and the semiconductor chips 3.

【0006】これによりこのBGA1は、プリント配線
板2の各バンプ2Bとマザー基板6の実装面6A上の各
ランド6Bとがクリームはんだ7を介して導通接続され
ることにより、マザー基板6上に実装することができる
ようになされている。
As a result, the BGA 1 is connected to the bumps 2 B of the printed wiring board 2 and the lands 6 B on the mounting surface 6 A of the mother board 6 via the cream solder 7 so that the BGA 1 is electrically connected to the mother board 6. It has been made so that it can be implemented.

【0007】ここでこのようなBGA1は図6(A)〜
図6(C)において示す以下の手順によりマザー基板6
上に実装される。すなわちまず図6(A)に示すよう
に、マザー基板6の各ランド6B上にクリームはんだ7
をスクリーン転写等の方法により供給する。
Here, such a BGA 1 is shown in FIGS.
The mother substrate 6 is formed by the following procedure shown in FIG.
Implemented above. That is, first, as shown in FIG. 6A, the cream solder 7 is placed on each land 6B of the mother substrate 6.
Is supplied by a method such as screen transfer.

【0008】この状態で図6(B)に示すようにBGA
1の各バンプ2Bとマザー基板6上の各ランド6Bとが
対向するように位置合わせした後、図6(C)に示すよ
うにBGA1の各バンプ2Bが各ランド6Bに当接する
ようにBGA1を所定圧力で押し付けマウントする。
In this state, as shown in FIG.
1 and the lands 6B on the mother substrate 6 are opposed to each other. Then, as shown in FIG. 6C, the BGA 1 is positioned so that the bumps 2B of the BGA 1 contact the lands 6B. Press and mount with a predetermined pressure.

【0009】そしてこのBGA1をマウントしたマザー
基板6を所定温度でリフロー加熱することにより、BG
A1をマザー基板6上に実装することができる。
The mother substrate 6 on which the BGA 1 is mounted is reflow-heated at a predetermined temperature, thereby
A1 can be mounted on the motherboard 6.

【0010】[0010]

【発明が解決しようとする課題】ところがこのようなB
GA1では、図6(C)に示すBGAマウント工程にお
いて、BGA1をマザー基板6上に押し付ける圧力は一
定ではない。これにより例えば図7(A)に示すよう
に、BGA1の押し付け圧力が大きい場合は、マザー基
板6の各ランド6B上に供給されたクリームはんだ7を
必要以上に押し潰すためこの各ランド6B上のクリーム
はんだ7同士が接触し、ランド6B間のシヨート不良を
引き起こす問題があつた。
However, such a B
In GA1, in the BGA mounting step shown in FIG. 6C, the pressure for pressing BGA1 onto mother substrate 6 is not constant. Thus, for example, as shown in FIG. 7A, when the pressing pressure of the BGA 1 is large, the cream solder 7 supplied on each land 6B of the mother board 6 is crushed more than necessary, so that the There is a problem that the cream solders 7 come into contact with each other and cause short-circuit failure between the lands 6B.

【0011】またBGA1をマウントしたマザー基板6
をリフロー加熱する加熱加工工程時において、マザー基
板6の各ランド6B上に供給されたクリームはんだ7が
溶解した後、BGA1が当該BGA1の自重により各ラ
ンド6B上に押し付けられ、当該各ランド6B上に供給
されたクリームはんだ7を必要以上に押し潰すためこの
各ランド6B上のクリームはんだ7同士が接触し、ラン
ド6B間のシヨート不良を引き起こす問題もあつた。
A mother board 6 on which the BGA 1 is mounted
In the heating step of reflow heating, after the cream solder 7 supplied on each land 6B of the mother board 6 is melted, the BGA 1 is pressed onto each land 6B by its own weight, and There is also a problem that the cream solder 7 on each land 6B comes into contact with each other to crush the cream solder 7 supplied to the lands more than necessary, causing short shot between the lands 6B.

【0012】一方、これとは逆にBGA1の押し付け圧
力が小さい場合において図7(B)に示すように、例え
ばBGA1の各バンプ2Bの形状が均等ではなく当該バ
ンプ2Bの高さのばらつき(コプラナリテイ)が大きい
場合、BGA1のバンプ2Bの中でマザー基板6の各ラ
ンド6B上に供給されたクリームはんだ7と接触しない
バンプ2Bが発生するため、バンプ浮きによるオープン
不良を引き起こす問題があつた。
On the other hand, when the pressing pressure of the BGA 1 is small, on the other hand, as shown in FIG. 7B, for example, the shapes of the bumps 2B of the BGA 1 are not uniform and the height of the bumps 2B varies (coplanarity). ) Is large, the bumps 2B that do not come into contact with the cream solder 7 supplied on the lands 6B of the mother board 6 are generated in the bumps 2B of the BGA1, and there is a problem that an open defect is caused by the floating of the bumps.

【0013】そして従来これらBGA1の押し付け圧力
の制御は、BGA1の実装装置の条件設定にのみ依存し
ていたため、例えばBGA1やマザー基板6自体に反り
等の欠陥を有する場合には、上述のようなシヨート不良
等を回避し難かつた。
Conventionally, the control of the pressing pressure of the BGA 1 depends only on the setting of the conditions of the mounting device of the BGA 1. For example, when the BGA 1 or the mother board 6 itself has a defect such as warpage, the above-described control is performed. It was difficult to avoid short shots.

【0014】さらに加熱加工工程時にBGA1に負荷さ
れる加熱温度は、BGA1を加熱する前の加熱炉を事前
に温度測定することにより確認されるが、これは加熱炉
の温度のばらつきや温度測定器の精度のばらつきにより
事前測定の温度と実際の加熱時の温度に差が生じる場合
があり、このため実際にBGA1を加熱している加熱加
工時のBGA1に負荷される加熱温度が、このBGA1
の耐熱保証温度よりも大きい場合には当該BGA1の封
止樹脂5が溶解するため、このBGA1は使用できなく
なる問題があつた。
Further, the heating temperature applied to the BGA 1 during the heating processing step is confirmed by measuring the temperature of the heating furnace before heating the BGA 1, which is caused by the temperature variation of the heating furnace and the temperature measuring device. In some cases, there is a difference between the temperature of the pre-measurement and the temperature of the actual heating due to the variation in accuracy of the BGA1. Therefore, the heating temperature applied to the BGA1 at the time of the heating processing for actually heating the BGA1 is the BGA1.
When the temperature is higher than the heat-resistant guaranteed temperature, the sealing resin 5 of the BGA 1 is dissolved, so that there is a problem that the BGA 1 cannot be used.

【0015】本発明は以上の点を考慮してなされたもの
で、接続の信頼性を実用上十分に向上させ得る表面実装
型電子部品を実現しようとするものである。
The present invention has been made in view of the above points, and has as its object to realize a surface mount electronic component capable of sufficiently improving the reliability of connection in practical use.

【0016】[0016]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、一面上に第1の導電材料からなる
複数の第1の突起電極が設けられた表面実装型電子部品
の当該一面の同一直線上にのらない少なくとも3ヶ所以
上の位置に、第1の導電材料よりも高融点の第2の導電
材料を用いてそれぞれ各第1の突起電極と同じ高さで複
数の第2の突起電極を設けるようにした。
According to the present invention, there is provided a surface mounting type electronic component having a plurality of first protruding electrodes made of a first conductive material provided on one surface thereof. Using a second conductive material having a melting point higher than that of the first conductive material, at least at three or more positions that are not on the same straight line, a plurality of second conductive materials having the same height as the first protruding electrodes. Protrusion electrodes were provided.

【0017】これによりこの表面実装型電子部品では、
マザー基板に実装する際に第2の突起電極によつて所定
状態に安定させて実装することができる。
Thus, in this surface mount type electronic component,
When mounting on a motherboard, the second projection electrode can stably mount the motherboard in a predetermined state.

【0018】また本発明においては、一面上に第1の導
電材料からなる複数の第1の突起電極が設けられた表面
実装型電子部品の実装方法に、一面の同一直線上にのら
ない少なくとも3ヶ所以上の位置に第1の導電材料より
も高融点の第2の導電材料を用いてそれぞれ各第1の突
起電極と同じ高さで複数の第2の突起電極を形成する第
1のステツプと、一面上に第1及び第2の突起電極にそ
れぞれ対応して複数の電極が設けられたマザー基板の当
該各電極と表面実装型電子部品の第1及び第2の突起電
極とをそれぞれ導通接続する第2のステツプとを設ける
ようにした。
According to the present invention, there is provided a method for mounting a surface-mounted electronic component having a plurality of first projecting electrodes made of a first conductive material on one surface, wherein at least one surface is not on the same straight line. A first step of forming a plurality of second projecting electrodes at the same height as each first projecting electrode by using a second conductive material having a higher melting point than the first conductive material at three or more positions; And electrically connecting the respective electrodes of the motherboard provided with a plurality of electrodes corresponding to the first and second projecting electrodes on one surface with the first and second projecting electrodes of the surface mount type electronic component, respectively. A second step for connection is provided.

【0019】これによりこの表面実装型電子部品の実装
方法では、マザー基板に実装する際に第2の突起電極に
よつて所定状態に安定させて実装することができる。
According to this method of mounting a surface mount type electronic component, it is possible to stably mount the electronic component on a mother board in a predetermined state by the second protruding electrode.

【0020】[0020]

【発明の実施の形態】以下図面について、本発明の一実
施の形態を詳述する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0021】(1)本実施の形態によるBGAの構成 図5との対応部分に同一符号を付した図1において10
は全体として本実施の形態によるBGAを示し、プリン
ト配線板2の一面2A上の各バンプ2Bに加えてダミー
バンプ11がこの一面2A上に形成されている点を除い
てBGA1とほぼ同様の構成からなる。
(1) Configuration of BGA According to the Present Embodiment In FIG.
Indicates a BGA according to the present embodiment as a whole, and has substantially the same configuration as that of the BGA 1 except that a dummy bump 11 is formed on the surface 2A in addition to the bumps 2B on the surface 2A of the printed wiring board 2. Become.

【0022】この場合このダミーバンプ11は、実際上
融点が各バンプ2Bの融点よりも高くかつBGA10の
耐熱保証温度と同等の例えば 220〔℃〕〜 250〔℃〕程
度のSn−Ag系等のはんだからなり、例えば各バンプ
2Bの高さと同寸法の高さ及び同形状でプリント配線板
2の一面2A上の4隅等にそれぞれスクリーン転写法等
により形成される。
In this case, the dummy bump 11 has a melting point higher than the melting point of each of the bumps 2B, and is, for example, about 220 [° C.] to 250 [° C.], such as Sn-Ag based solder, which is equivalent to the heat-resistant guaranteed temperature of the BGA 10. The bumps 2B are formed, for example, at four corners on the one surface 2A of the printed wiring board 2 by the screen transfer method or the like with the same height and the same size as the height of each bump 2B.

【0023】これによりこのBGA10は、各ダミーバ
ンプ11とこれに対応するマザー基板6の各ランド6C
とがそれぞれ直接当接する一方、各バンプ2Bとこれに
対応するマザー基板6の各ランド6Bとがクリームはん
だ7を介して導通接続されることによりマザー基板6上
に実装することができるようになされている。
As a result, the BGA 10 is provided with the dummy bumps 11 and the corresponding lands 6C of the mother substrate 6 corresponding to the dummy bumps 11.
Are directly in contact with each other, and the bumps 2B and the corresponding lands 6B of the mother board 6 are electrically connected via the cream solder 7 so that the bumps 2B can be mounted on the mother board 6. ing.

【0024】(2)本実施の形態によるBGAの実装方
法 ここで実際上このBGA10は図2(A)〜図2(C)
に示す以下の手順により、マザー基板6上に実装するこ
とができる。すなわちまず図2(A)のようにマザー基
板6の実装面6A上にBGA10の各ダミーバンプ11
に対応して形成されたランド6Cを除く、各ランド6B
上にそれぞれクリームはんだ7をスクリーン転写等の方
法で供給する。
(2) Method of Mounting BGA According to the Present Embodiment Here, this BGA 10 is actually shown in FIGS. 2 (A) to 2 (C).
Can be mounted on the motherboard 6 by the following procedure shown in FIG. That is, first, as shown in FIG. 2A, each dummy bump 11 of the BGA 10 is mounted on the mounting surface 6A of the mother substrate 6.
Each land 6B except the land 6C formed corresponding to
The cream solder 7 is supplied onto each of them by a method such as screen transfer.

【0025】次にこの状態で図2(B)に示すようにB
GA10の各バンプ2Bとマザー基板6上の各ランド6
B及び各ダミーバンプ11とこれに対応する各ランド6
Cとが対向するように位置合わせした後、図6(C)に
示すようにBGA10の各ダミーバンプ11が各ランド
6Cに当接するようにBGA10を所定圧力で押し付け
マウントする。このときこのBGA10の押し付け圧力
は、各ダミーバンプ11と各ランド6Cとが当接するこ
とから常に均等となるようになされている。
Next, in this state, as shown in FIG.
Each bump 2B of GA10 and each land 6 on mother substrate 6
B and each dummy bump 11 and each corresponding land 6
6C, the BGA 10 is pressed and mounted at a predetermined pressure so that each dummy bump 11 of the BGA 10 comes into contact with each land 6C as shown in FIG. 6C. At this time, the pressing pressure of the BGA 10 is always equal since each dummy bump 11 and each land 6C are in contact with each other.

【0026】そしてこの後BGA10をマウントしたマ
ザー基板6を所定温度でリフロー加熱することにより、
クリームはんだ7が溶解して各バンプ2Bと各ランド6
Bとが導通接続するためBGA10をマザー基板6上に
実装することができる。
Thereafter, the mother substrate 6 on which the BGA 10 is mounted is reflow-heated at a predetermined temperature,
The cream solder 7 is melted and each bump 2B and each land 6
Since B is electrically connected, the BGA 10 can be mounted on the motherboard 6.

【0027】(3)本実施の形態の動作及び効果 以上の構成において、BGA10はプリント配線板2の
一面2A上の直線上以外の少なくとも4ヵ所以上にダミ
ーバンプ11を形成し、当該ダミーバンプ11とマザー
基板6の各ランド6Cとを直接当接させる一方、これと
共に各バンプ2Bと各ランド6Bとをクリームはんだ7
を介して導通接続することにより、BGA10をマザー
基板6上に常に均等な押し付け圧力で押し付け実装する
ことができる。
(3) Operation and Effect of the Present Embodiment In the above configuration, the BGA 10 forms the dummy bumps 11 at at least four places other than on a straight line on the one surface 2A of the printed wiring board 2, and The respective lands 6C of the substrate 6 are brought into direct contact with each other, and at the same time, each bump 2B and each
The BGA 10 can be always mounted on the mother substrate 6 by pressing with uniform pressing pressure.

【0028】かくするにつきBGA10をマザー基板6
上に必要以上に強く押し付けたり、又はBGA10の自
重により当該BGA10が各ランド6B上に必要以上に
押し付けられ、当該各ランド6B上に供給されたクリー
ムはんだ7を必要以上に押し潰すことによる各ランド6
B間のシヨート不良を未然に防止することができると共
に、各バンプ2Bの高さにばらつきを有する場合におい
ても、各バンプ2Bと各ランド6Bとをクリームはんだ
7を介して確実に接続するため、バンプ浮きによるオー
プン不良を未然に防止することができる。
In this way, the BGA 10 is attached to the mother board 6
Each land is pressed more than necessary or the BGA 10 is pressed more than necessary on each land 6B by its own weight, and the cream solder 7 supplied on each land 6B is crushed more than necessary. 6
In order to prevent short-circuit failure between B beforehand and to reliably connect each bump 2B and each land 6B via the cream solder 7, even when the height of each bump 2B varies, Open failure due to bump floating can be prevented beforehand.

【0029】一方このときダミーバンプ11は各バンプ
2Bよりも高くかつBGA10の耐熱保証温度と同等の
融点を有するため、リフロー加熱温度がBGA10の耐
熱保証温度よりも低い場合は図3(A)に示すように各
バンプ2Bはクリームはんだ7がBGA10を当該BG
A10の高さ方向に浮かすように凝固する一方、各ダミ
ーバンプ11とこれに対応する各ランド6Cとの間には
クリームはんだ7が供給されていないため、この分僅か
に隙間を有するようになされている。
On the other hand, at this time, since the dummy bumps 11 are higher than the respective bumps 2B and have a melting point equivalent to the heat resistance assurance temperature of the BGA 10, the case where the reflow heating temperature is lower than the heat resistance assurance temperature of the BGA 10 is shown in FIG. As shown in FIG.
While the solidification is performed so as to float in the height direction of A10, the cream solder 7 is not supplied between each dummy bump 11 and each corresponding land 6C. I have.

【0030】一方、リフロー加熱温度がBGA10の耐
熱保証温度よりも高い場合は図3(B)に示すように、
各ダミーバンプ11が溶解し各ランド6Cと接合してし
まうため、各ダミーバンプ11とこれに対応する各ラン
ド6Cとの間には隙間はできず、これら各ダミーバンプ
11と各ランド6Cとが当接した状態になる。
On the other hand, when the reflow heating temperature is higher than the guaranteed heat resistance temperature of the BGA 10, as shown in FIG.
Since each of the dummy bumps 11 melts and joins with each of the lands 6C, there is no gap between each of the dummy bumps 11 and each of the corresponding lands 6C, and these dummy bumps 11 and each of the lands 6C contact each other. State.

【0031】かくしてこのBGA10では、リフロー加
熱後にBGA10のダミーバンプ11がマザー基板6の
ランド6Cに当接しているか否かにより、リフロー加熱
時の加熱加工温度がBGA10の耐熱保証温度未満か否
かを知ることができるようになされている。
Thus, in this BGA 10, it is known whether or not the heating processing temperature during the reflow heating is lower than the heat resistance assurance temperature of the BGA 10 based on whether or not the dummy bump 11 of the BGA 10 is in contact with the land 6C of the mother substrate 6 after the reflow heating. It has been made possible.

【0032】以上の構成によれば、BGA10はプリン
ト配線板2の一面2A上の直線上以外の少なくとも4ヵ
所以上にダミーバンプ11を形成し、当該ダミーバンプ
11とマザー基板6の各ランド6Cとが当接するように
マザー基板6上に実装することにより、BGA10を常
に均等な押し付け圧力でマザー基板6上に押し付けるこ
とができ、BGA10の自重又は当該BGA10をマザ
ー基板6上に必要以上に強く押し付けることによる各ラ
ンド6B間のシヨート不良を未然に防止することができ
ると共に、各バンプ2Bの高さにばらつきを有する場合
においても各バンプ2Bと各ランド6Bとを確実に接続
するため、バンプ浮きによるオープン不良を未然に防止
することができ、かくして接続の信頼性を実用上十分に
向上させ得るBGA10を実現することができる。
According to the above configuration, the BGA 10 forms the dummy bumps 11 in at least four places other than on a straight line on the one surface 2A of the printed wiring board 2, and the dummy bumps 11 and the lands 6C of the mother board 6 correspond to each other. By mounting the BGA 10 on the mother board 6 so as to be in contact with the mother board 6, the BGA 10 can always be pressed on the mother board 6 with an even pressing pressure, and the weight of the BGA 10 or the pressing of the BGA 10 on the mother board 6 more than necessary can be achieved. Short failure between the lands 6B can be prevented beforehand, and even when the height of each bump 2B varies, the bump 2B and each land 6B are securely connected. Can be prevented beforehand, and thus the connection reliability can be sufficiently improved in practical use. It is possible to realize a 10.

【0033】(4)他の実施の形態 なお上述の実施の形態においては、支持手段としてのダ
ミーバンプ11の材料をSn−Ag系のはんだを用いて
形成するようにした場合について述べたが、本発明はこ
れに限らず、要は融点がバンプ2Bよりも高くかつBG
A10の耐熱保証温度と同等であるものであればダミー
バンプ11の材料としては、この他Sn−Sb系等の種
々の材料を用いて形成する場合においても広く適用する
ことができる。
(4) Other Embodiments In the above-described embodiment, the case where the material of the dummy bumps 11 as the support means is formed using Sn-Ag based solder has been described. The invention is not limited to this, but the point is that the melting point is higher than that of bump 2B and BG
As long as the material is equivalent to the heat-resistant guaranteed temperature of A10, the material of the dummy bump 11 can be widely applied to the case where various materials such as Sn—Sb are used.

【0034】また上述の実施の形態においては、ダミー
バンプ11をプリント配線板2の一面2A上の4隅に形
成するようにした場合について述べたが、本発明はこれ
に限らず、要はプリント配線板2の一面2A上の直線上
以外の少なくとも4ヵ所であればダミーバンプ11の形
成位置としては、この他種々の位置に形成する場合にお
いても広く適用することができる。
In the above-described embodiment, the case where the dummy bumps 11 are formed at the four corners on the one surface 2A of the printed wiring board 2 has been described. However, the present invention is not limited to this, and As long as the dummy bumps 11 are formed at at least four places other than on a straight line on the one surface 2A of the plate 2, the present invention can be widely applied to the case where the dummy bumps 11 are formed at various other positions.

【0035】さらに上述の実施の形態においては、ダミ
ーバンプ11をバンプ2Bと同形状に形成するようにし
た場合について述べたが、本発明はこれに限らず、要は
バンプ2Bの高さと同寸法であればダミーバンプ11の
形状としては、この他例えば図1との対応部分に同一符
号を付した図4(A)に示すBGA20のダミーバンプ
21のようにバンプ2Bの高さと同寸法を有する立方体
等の種々の形状を用いて形成する場合においても広く適
用することができる。
Further, in the above-described embodiment, the case has been described where the dummy bumps 11 are formed in the same shape as the bumps 2B. However, the present invention is not limited to this, and the point is that the dummy bumps 11 have the same dimensions as the height of the bumps 2B. If there is, the shape of the dummy bump 11 is, for example, a cube having the same dimensions as the height of the bump 2B, such as the dummy bump 21 of the BGA 20 shown in FIG. The present invention can be widely applied to the case of forming using various shapes.

【0036】さらに上述の実施の形態においては、ダミ
ーバンプ11をスクリーン転写法を用いて形成するよう
にした場合について述べたが、本発明はこれに限らず、
ダミーバンプ11の形成方法としては、この他めつき法
等の種々の形成方法を用いて形成する場合においても広
く適用することができる。
Further, in the above-described embodiment, the case where the dummy bumps 11 are formed by using the screen transfer method has been described. However, the present invention is not limited to this.
The method for forming the dummy bumps 11 can be widely applied to the case where the dummy bumps 11 are formed by using various forming methods such as the plating method.

【0037】さらに上述の実施の形態においては、表面
実装型電子部品としてBGA10を用いるようにした場
合について述べたが、本発明はこれに限らず、要は一面
上に複数の電極が形成されるものであれば表面実装型電
子部品としては、この他例えば図4(B)に示すような
LGA(ランドグリツドアレイ)30等の種々の表面実
装型電子部品を適用することができる。
Further, in the above-described embodiment, a case has been described in which the BGA 10 is used as the surface-mounted electronic component. However, the present invention is not limited to this, and in other words, a plurality of electrodes are formed on one surface. In addition, various surface-mounted electronic components such as an LGA (land grid array) 30 as shown in FIG. 4B can be used as the surface-mounted electronic component.

【0038】さらに上述の実施の形態においては、リフ
ロー加熱後、各ダミーバンプ11とこれに対応するマザ
ー基板6の各ランド6Cとの間に僅かに隙間が形成され
ることによりリフロー加熱温度がBGA10の耐熱保証
温度未満か否かを確認できるようにした場合について述
べたが、本発明はこれに限らず、要は各ダミーバンプ1
1とこれに対応するマザー基板6の各ランド6Cとが接
触することにより、リフロー加熱温度がBGA10の耐
熱保証温度よりも高いことが確認できるようにすればそ
の構成としては、この他例えばダミーバンプを検査用バ
ンプとして当該各検査用バンプとこれに対応する各検査
用ランドとが接触することにより電流が流れ、この電流
によりリフロー加熱温度がBGA10の耐熱保証温度よ
りも高いことが確認できるようにする場合等の種々の構
成を広く適用することができる。
Further, in the above-described embodiment, after the reflow heating, a slight gap is formed between each dummy bump 11 and the corresponding land 6C of the mother substrate 6, so that the reflow heating temperature is lower than that of the BGA 10. Although the case in which it is possible to confirm whether the temperature is lower than the heat-resistance guaranteed temperature has been described, the present invention is not limited to this, and the point is that each dummy bump 1
1 and the corresponding lands 6C of the motherboard 6 contact with each other, so that it can be confirmed that the reflow heating temperature is higher than the heat resistance assurance temperature of the BGA 10; A current flows when each of the inspection bumps comes into contact with each of the inspection lands corresponding thereto as an inspection bump, and this current allows the reflow heating temperature to be confirmed to be higher than the heat resistance guaranteed temperature of the BGA 10. Various configurations such as cases can be widely applied.

【0039】[0039]

【発明の効果】上述のように本発明によれば、一面上に
第1の導電材料からなる複数の第1の突起電極が設けら
れた表面実装型電子部品の一面の同一直線上にのらない
少なくとも3ヶ所以上の位置に、第1の導電材料よりも
高融点の第2の導電材料を用いてそれぞれ各第1の突起
電極と同じ高さで複数の第2の突起電極を設けるように
したことにより、マザー基板に実装する際に第2の突起
電極によつて所定状態に安定させて実装することがで
き、かくして接続の信頼性を実用上十分に向上させ得る
表面実装型電子部品を実現することができる。
As described above, according to the present invention, a plurality of first projecting electrodes made of a first conductive material are provided on one surface of a surface-mounted electronic component. At least at three or more positions, a plurality of second projection electrodes are provided at the same height as each first projection electrode using a second conductive material having a higher melting point than the first conductive material. By doing so, it is possible to stably mount the semiconductor device in a predetermined state by the second protruding electrode when mounting it on the mother board, and thus a surface mount electronic component capable of sufficiently improving the reliability of connection practically. Can be realized.

【0040】また上述のように本発明によれば、一面上
に第1の導電材料からなる複数の第1の突起電極が設け
られた表面実装型電子部品の実装方法に、一面の同一直
線上にのらない少なくとも3ヶ所以上の位置に第1の導
電材料よりも高融点の第2の導電材料を用いてそれぞれ
各第1の突起電極と同じ高さで複数の第2の突起電極を
形成する第1のステツプと、一面上に第1及び第2の突
起電極にそれぞれ対応して複数の電極が設けられたマザ
ー基板の当該各電極と表面実装型電子部品の第1及び第
2の突起電極とをそれぞれ導通接続する第2のステツプ
とを設けるようにしたことにより、マザー基板に実装す
る際に第2の突起電極によつて所定状態に安定させて実
装することができ、かくして接続の信頼性を実用上十分
に向上させ得る表面実装型電子部品の実装方法を実現す
ることができる。
According to the present invention, as described above, a method of mounting a surface mount electronic component having a plurality of first protruding electrodes made of a first conductive material on one surface is provided on a surface of the same straight line. A plurality of second protruding electrodes are formed at at least three or more positions where the second protruding electrodes are at the same height as each first protruding electrode using a second conductive material having a higher melting point than the first conductive material. A first step to be performed, the respective electrodes of a mother board provided with a plurality of electrodes on one surface corresponding to the first and second projection electrodes, respectively, and the first and second projections of a surface mount type electronic component. By providing the second step for electrically connecting the electrodes to each other, it is possible to stably mount in a predetermined state by the second protruding electrodes when mounting on the mother board, and thus the connection can be established. Table that can sufficiently improve reliability in practical use Mounting method of mounting electronic components can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本実施の形態によるBGAの構成を示す断面図
である。
FIG. 1 is a sectional view showing a configuration of a BGA according to the present embodiment.

【図2】本実施の形態によるBGAの実装手順を示す断
面図である。
FIG. 2 is a cross-sectional view showing a procedure for mounting a BGA according to the present embodiment.

【図3】本実施の形態によるBGAとマザー基板との実
装の構成を示す部分的断面図である。
FIG. 3 is a partial cross-sectional view showing a configuration of mounting a BGA and a mother board according to the present embodiment.

【図4】他の実施の形態による表面実装型電子部品の構
成を示す部分的断面図である。
FIG. 4 is a partial cross-sectional view showing a configuration of a surface-mounted electronic component according to another embodiment.

【図5】従来のBGAの構成を示す断面図である。FIG. 5 is a cross-sectional view showing a configuration of a conventional BGA.

【図6】従来のBGAの実装手順を示す断面図である。FIG. 6 is a cross-sectional view showing a conventional BGA mounting procedure.

【図7】従来のBGAとマザー基板との実装の構成を示
す部分的断面図である。
FIG. 7 is a partial cross-sectional view showing a configuration of mounting a conventional BGA and a mother board.

【符号の説明】[Explanation of symbols]

1、10、20……BGA、2……プリント配線板、2
A……一面、2B……バンプ、2C……他面、2D……
パツド、3……半導体チツプ、4……ワイヤ、5……封
止樹脂、6……マザー基板、6A……実装面、6B、6
C……ランド、7……クリームはんだ、11、21、3
1……ダミーバンプ、30……LGA。
1, 10, 20 ... BGA, 2 ... printed wiring board, 2
A: One side, 2B: Bump, 2C: Other side, 2D:
Pad 3, semiconductor chip 4, wire 5, sealing resin 6, mother board 6A mounting surface 6B, 6
C: land, 7: cream solder, 11, 21, 3
1 ... Dummy bump, 30 ... LGA.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】一面上に第1の導電材料からなる複数の第
1の突起電極が設けられた表面実装型電子部品におい
て、 上記一面の同一直線上にのらない少なくとも3ヶ所以上
の位置に、上記第1の導電材料よりも高融点の第2の導
電材料を用いてそれぞれ各上記第1の突起電極と同じ高
さで複数の第2の突起電極が設けられたことを特徴とす
る表面実装型電子部品。
1. A surface-mounted electronic component provided with a plurality of first protruding electrodes made of a first conductive material on one surface, wherein at least three or more positions are not on the same straight line on the one surface. A plurality of second projecting electrodes each provided at the same height as each of the first projecting electrodes using a second conductive material having a higher melting point than the first conductive material. Mountable electronic components.
【請求項2】一面上に複数の第1の電極が設けられた半
導体チツプと、 一面側に上記半導体チツプの各上記第1の電極にそれぞ
れ対応させて複数の第2の電極が設けられると共に、他
面側に各上記第2の電極にそれぞれ対応させて各上記第
1の突起電極がそれぞれ対応する上記第2の電極と導通
するように設けられた変換基板と、 上記半導体チツプの各上記第1の電極及び上記変換基板
の対応する上記第2の電極をそれぞれ導通接続する導通
接続手段と、 上記半導体チツプ及び上記導通接続手段を一体に封止す
る封止樹脂とを具え、上記第2の導電材料は、上記封止
樹脂の融点と同等の融点でなることを特徴とする請求項
1に記載の表面実装型電子部品。
2. A semiconductor chip having a plurality of first electrodes provided on one surface thereof, and a plurality of second electrodes provided on one surface thereof respectively corresponding to the first electrodes of the semiconductor chip. A conversion substrate provided on the other surface so as to correspond to each of the second electrodes so that each of the first projection electrodes is electrically connected to the corresponding one of the second electrodes; A conductive connection means for conductively connecting the first electrode and the corresponding second electrode of the conversion substrate; and a sealing resin for integrally sealing the semiconductor chip and the conductive connection means. The surface-mounted electronic component according to claim 1, wherein the conductive material has a melting point equivalent to the melting point of the sealing resin.
【請求項3】上記第2の突起電極は、上記他面の四隅に
形成されたことを特徴とする請求項1に記載の表面実装
型電子部品。
3. The surface-mounted electronic component according to claim 1, wherein the second protruding electrodes are formed at four corners of the other surface.
【請求項4】一面上に第1の導電材料からなる複数の第
1の突起電極が設けられた表面実装型電子部品の実装方
法において、 上記一面の同一直線上にのらない少なくとも3ヶ所以上
の位置に、上記第1の導電材料よりも高融点の第2の導
電材料を用いてそれぞれ各上記第1の突起電極と同じ高
さで複数の第2の突起電極を形成する第1のステツプ
と、 一面上に上記第1及び第2の突起電極にそれぞれ対応し
て複数の電極が設けられたマザー基板の当該各電極と、
上記表面実装型電子部品の上記第1及び第2の突起電極
とをそれぞれ導通接続する第2のステツプとを具えるこ
とを特徴とする表面実装型電子部品の実装方法。
4. A method for mounting a surface-mounted electronic component having a plurality of first projecting electrodes made of a first conductive material on one surface, wherein at least three or more locations not on the same straight line on the one surface are provided. A first step of forming a plurality of second projection electrodes at the same height as each of the first projection electrodes using a second conductive material having a higher melting point than the first conductive material. And a plurality of electrodes on a mother substrate provided with a plurality of electrodes on one surface respectively corresponding to the first and second protruding electrodes;
A second step of electrically connecting the first and second protruding electrodes of the surface-mounted electronic component to each other.
【請求項5】上記表面実装型電子部品は、 一面上に複数の第1の電極が設けられた半導体チツプ
と、 一面側に上記半導体チツプの各上記第1の電極にそれぞ
れ対応させて複数の第2の電極が設けられると共に、他
面側に各上記第2の電極にそれぞれ対応させて各上記第
1の突起電極がそれぞれ対応する上記第2の電極と導通
するように設けられた変換基板と、 上記半導体チツプの各上記第1の電極及び上記変換基板
の対応する上記第2の電極をそれぞれ導通接続する導通
接続手段と、 上記半導体チツプ及び上記導通接続手段を一体に封止す
る封止樹脂とを具え、上記第1のステツプでは、上記第
2の導電材料として上記封止樹脂の融点と同等の融点の
導電材料を用いることを特徴とする請求項4に記載の表
面実装型電子部品の実装方法。
5. The surface-mounted electronic component according to claim 1, wherein a plurality of first electrodes are provided on one surface of the semiconductor chip, and a plurality of first electrodes of the semiconductor chip are provided on one surface corresponding to the first electrodes. A conversion substrate provided with a second electrode and provided on the other surface so that each of the first protruding electrodes is electrically connected to the corresponding second electrode in correspondence with each of the second electrodes. Conductive connecting means for conductively connecting each of the first electrodes of the semiconductor chip and the corresponding second electrode of the conversion substrate; and sealing for integrally sealing the semiconductor chip and the conductive connecting means. 5. The surface-mounted electronic component according to claim 4, wherein the first step uses a conductive material having a melting point equivalent to that of the sealing resin in the first step. How to implement.
【請求項6】上記第1のステツプでは、 上記第2の突起電極を上記他面の四隅に形成することを
特徴とする請求項4に記載の表面実装型電子部品の実装
方法。
6. The method according to claim 4, wherein in the first step, the second protruding electrodes are formed at four corners of the other surface.
JP7209598A 1998-03-20 1998-03-20 Surface mount electronic component and mounting method thereof Expired - Fee Related JP3862120B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7209598A JP3862120B2 (en) 1998-03-20 1998-03-20 Surface mount electronic component and mounting method thereof

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170924A (en) * 2000-11-29 2002-06-14 Kyocera Corp Laminated type semiconductor device and mounting board
JP2013219170A (en) * 2012-04-09 2013-10-24 Yokogawa Electric Corp Substrate device
CN107592733A (en) * 2017-08-24 2018-01-16 深圳市华星光电半导体显示技术有限公司 Printed circuit board (PCB) for mount ball-grid array encapsulation chip and preparation method thereof
JP2021048330A (en) * 2019-09-20 2021-03-25 株式会社村田製作所 Connection structure of substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170924A (en) * 2000-11-29 2002-06-14 Kyocera Corp Laminated type semiconductor device and mounting board
JP2013219170A (en) * 2012-04-09 2013-10-24 Yokogawa Electric Corp Substrate device
CN107592733A (en) * 2017-08-24 2018-01-16 深圳市华星光电半导体显示技术有限公司 Printed circuit board (PCB) for mount ball-grid array encapsulation chip and preparation method thereof
JP2021048330A (en) * 2019-09-20 2021-03-25 株式会社村田製作所 Connection structure of substrate

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