JPH1187906A - Semiconductor device and packaging method therefor - Google Patents
Semiconductor device and packaging method thereforInfo
- Publication number
- JPH1187906A JPH1187906A JP9240721A JP24072197A JPH1187906A JP H1187906 A JPH1187906 A JP H1187906A JP 9240721 A JP9240721 A JP 9240721A JP 24072197 A JP24072197 A JP 24072197A JP H1187906 A JPH1187906 A JP H1187906A
- Authority
- JP
- Japan
- Prior art keywords
- package
- solder bumps
- semiconductor device
- printed wiring
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その実装方法に関し、特に、ＢＧＡ（ＢａｌｌＧｒｉｄ
Ａｒｒａｙ）やＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃ
ｋａｇｅ）などの実装に適用して有効な技術に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for mounting the same, and more particularly, to a BGA (Ball Grid).
Array) and CSP (Chip Size Pac)
The present invention relates to a technology that is effective when applied to implementation such as kage).
【０００２】[0002]
【従来の技術】本発明者が検討したところによれば、表
面実装形パッケージの一種であるＢＧＡやＣＳＰなどの
球形のはんだであるはんだボールをアレイ状に並べ、リ
ードの代わりとする半導体装置においては、実装基板で
あるプリント基板から半導体装置を取り外すなどのリペ
ア作業を行う場合、エアヒータによってパッケージ上方
から約４００℃程度の熱風を吹き付けて加熱を行い、は
んだボールを溶融することによって行っている。2. Description of the Related Art According to studies made by the present inventor, a semiconductor device in which solder balls, which are spherical solders such as BGA and CSP, which are a kind of surface mount type package, are arranged in an array and used instead of leads, has been proposed. When performing a repair operation such as removing a semiconductor device from a printed circuit board, which is a mounting board, the air is heated by blowing hot air at about 400 ° C. from above the package to melt the solder balls.
【０００３】なお、この種の半導体装置について詳しく
述べてある例としては、１９９５年１月１６日、株式会
社日経ＰＢ社発行、「日経エレクトロニクス」Ｐ７９〜
Ｐ８６があり、この文献には、ＣＳＰの半導体装置にお
ける構成などが記載されている。[0003] As an example describing this type of semiconductor device in detail, see "Nikkei Electronics", P79-Jan.
P86, and this document describes the configuration of a CSP semiconductor device.
【０００４】[0004]
【発明が解決しようとする課題】ところが、上記のよう
な表面実装形の半導体装置では、次のような問題点があ
ることが本発明者により見い出された。However, the present inventor has found that the above-mentioned surface-mount type semiconductor device has the following problems.
【０００５】すなわち、パッケージ上方より熱風を吹き
付け加熱を行うため、はんだボールに熱が効率よく伝わ
らず、はんだボールが溶融する頃にはパッケージが約３
００℃程度の高温となり、パッケージクラックに至って
しまう恐れが生じている。In other words, since heating is performed by blowing hot air from above the package, heat is not efficiently transmitted to the solder balls.
The temperature becomes as high as about 00 ° C., which may cause a package crack.
【０００６】本発明の目的は、パッケージにダメージを
与えることなく、効率よく容易に半導体装置のリペア作
業を行うことのできる半導体装置およびその実装方法を
提供することにある。An object of the present invention is to provide a semiconductor device capable of easily and efficiently repairing a semiconductor device without damaging a package, and a mounting method thereof.
【０００７】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【０００９】すなわち、本発明の半導体装置は、プリン
ト配線基板の表面に半導体チップを載せ、裏面にはんだ
バンプをアレイ状に並べて外部端子としたパッケージ
と、当該パッケージとはんだバンプに対応した電極が設
けられたプリント配線実装基板との間に介在され、該は
んだバンプに対応した複数の貫通孔を有するシート基材
と、当該シート基材に設けられ、はんだバンプを加熱す
る加熱線とを備えるリペアシートとよりなり、加熱線を
加熱することによりはんだバンプを溶融させ、パッケー
ジをプリント配線実装基板から自在に着脱するものであ
る。That is, the semiconductor device of the present invention is provided with a package in which a semiconductor chip is mounted on the front surface of a printed wiring board, solder bumps are arranged in an array on the rear surface to form external terminals, and electrodes corresponding to the package and the solder bumps are provided. Repair sheet including a sheet base material interposed between the printed wiring board and a plurality of through holes corresponding to the solder bumps, and a heating wire provided on the sheet base material and heating the solder bumps By heating the heating wire to melt the solder bumps, the package can be freely attached to and detached from the printed wiring board.
【００１０】また、本発明の半導体装置は、前記加熱線
が高抵抗材料からなる電熱線よりなるものである。Further, in the semiconductor device according to the present invention, the heating wire is a heating wire made of a high-resistance material.
【００１１】さらに、本発明の半導体装置は、前記加熱
線が銅よりなることを特徴とする半導体装置。Further, in the semiconductor device according to the present invention, the heating wire is made of copper.
【００１２】また、本発明の半導体装置の実装方法は、
プリント配線基板の表面に半導体チップを載せ、裏面に
はんだバンプをアレイ状に並べて外部端子としたパッケ
ージを準備する工程と、はんだバンプに対応した複数の
貫通孔を有するシート基材と、当該シート基材に設けら
れ、はんだバンプを加熱する加熱線とを備えるリペアシ
ートを準備する工程と、該はんだバンプに対応した電極
が設けられたパッケージを実装するプリント実装基板を
準備する工程と、当該プリント実装基板上にリペアシー
トを搭載する工程と、リペアシートが搭載されたプリン
ト配線実装基板の電極と対応するはんだバンプを溶融す
ることにより電気的な接続を行う工程とを有するもので
ある。Further, a method of mounting a semiconductor device according to the present invention
A step of preparing a package in which semiconductor chips are mounted on the front surface of a printed wiring board and external terminals are arranged by arranging solder bumps on the back surface; a sheet substrate having a plurality of through holes corresponding to the solder bumps; A step of preparing a repair sheet provided on the material and having a heating wire for heating the solder bumps; a step of preparing a printed mounting board for mounting a package provided with electrodes corresponding to the solder bumps; The method includes a step of mounting a repair sheet on a substrate, and a step of performing electrical connection by melting solder bumps corresponding to the electrodes of the printed wiring board on which the repair sheet is mounted.
【００１３】さらに、本発明の半導体装置の実装方法
は、プリント配線基板の表面に半導体チップを載せ、裏
面に設けられた電極部にはんだバンプをアレイ状に並べ
て外部端子としたパッケージを準備する工程と、該はん
だバンプに対応した複数の貫通孔を有するシート基材
と、当該シート基材に設けられ、はんだバンプを加熱す
る加熱線とを備えるリペアシートを準備する工程と、は
んだバンプに対応した電極が設けられたパッケージを実
装するプリント配線実装基板を準備する工程と、パッケ
ージの裏面にリペアシートを搭載する工程と、プリント
配線実装基板にリペアシートが搭載されたパッケージを
実装し、前記はんだバンプを溶融することにより電気的
な接続を行う工程とを有するものである。Further, in the method of mounting a semiconductor device according to the present invention, a semiconductor chip is mounted on a front surface of a printed wiring board, and solder bumps are arranged in an array on electrode portions provided on the back surface to prepare a package having external terminals. And a step of preparing a repair sheet including a sheet base having a plurality of through holes corresponding to the solder bumps, and a heating wire provided on the sheet base and heating the solder bumps. A step of preparing a printed wiring board on which the package provided with the electrodes is mounted; a step of mounting a repair sheet on the back of the package; and mounting the package on which the repair sheet is mounted on the printed wiring board; And a step of making an electrical connection by melting.
【００１４】以上のことにより、はんだボールのみに効
率よく熱が伝導するので、パッケージにダメージを与え
ることなく、パッケージの取り外しや取り付けができる
ので、半導体装置のリペア作業を容易に短時間で行うこ
とができる。As described above, since heat is efficiently conducted only to the solder balls, the package can be removed or attached without damaging the package, so that the repair work of the semiconductor device can be easily performed in a short time. Can be.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。Embodiments of the present invention will be described below in detail with reference to the drawings.
【００１６】図１は、本発明の一実施の形態によるプリ
ント実装基板に実装された半導体装置の断面図、図２
は、本発明の一実施の形態による半導体装置に設けられ
るリペアシートの説明図である。FIG. 1 is a sectional view of a semiconductor device mounted on a printed circuit board according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram of a repair sheet provided in the semiconductor device according to one embodiment of the present invention.
【００１７】本実施の形態において、表面実装基板の一
種であるＢＧＡ形の半導体装置１は、たとえば、ＢＴ材
（ビスマレイミド系樹脂）からなるキャリア基板（プリ
ント配線基板）２が設けられている。In the present embodiment, a BGA type semiconductor device 1 which is a kind of a surface mount substrate is provided with a carrier substrate (printed wiring substrate) 2 made of, for example, a BT material (bismaleimide resin).
【００１８】そして、このキャリア基板２の表面にエポ
キシ系銀ペーストなどの接着材３を介して半導体チップ
４が接着され、キャリア基板２の裏面には、電極部５が
所定のピッチでアレイ状に並べられており、それぞれの
電極部５にはんだボール６が電気的に接続されている。A semiconductor chip 4 is adhered to the surface of the carrier substrate 2 via an adhesive 3 such as an epoxy-based silver paste. On the back surface of the carrier substrate 2, electrode portions 5 are arrayed at a predetermined pitch. The solder balls 6 are electrically connected to the respective electrode portions 5.
【００１９】また、キャリア基板２の表面には、半導体
チップ４の周辺部近傍に電極部５ａが形成されており、
このキャリア基板２に形成された電極部５ａが半導体チ
ップ４に形成された電極部と、たとえば、金（Ａｕ）線
などのボンディングワイヤ７により電気的に接続されて
いる。On the surface of the carrier substrate 2, an electrode portion 5a is formed near the periphery of the semiconductor chip 4,
The electrode portion 5a formed on the carrier substrate 2 is electrically connected to the electrode portion formed on the semiconductor chip 4 by, for example, a bonding wire 7 such as a gold (Au) wire.
【００２０】さらに、キャリア基板２は、それぞれの電
極部５ａが、所定の電極部５と電気的に接続されるよう
に信号配線パターンがサーキット状に配線形成されてい
る。そして、キャリア基板２の上部には、半導体チップ
４を覆うようにして、たとえば、セラミック製のリッド
８が設けられている。Further, in the carrier substrate 2, a signal wiring pattern is formed in a circuit shape so that each electrode portion 5 a is electrically connected to a predetermined electrode portion 5. A lid 8 made of, for example, ceramic is provided on the upper part of the carrier substrate 2 so as to cover the semiconductor chip 4.
【００２１】次に、半導体装置１は、電子部品などが実
装されるプリント実装基板（プリント配線実装基板）Ｐ
に形成された電極Ｄとはんだボール６を介して電気的に
接続されている。Next, the semiconductor device 1 has a printed mounting board (printed wiring mounting board) P on which electronic components and the like are mounted.
Are electrically connected to the electrodes D formed through the solder balls 6.
【００２２】そして、これら半導体チップ４が接着材３
によって接着され、ワイヤボンディング７によって電極
部５ａと半導体チップ４の電極部とが電気的に接続され
たキャリア基板２、はんだバンプ６およびリッド８によ
ってパッケージＨＰが形成されている。The semiconductor chips 4 are bonded to the adhesive 3
The package HP is formed by the carrier substrate 2, the solder bumps 6, and the lid 8, which are bonded by the wire bonding 7 and the electrode portions 5 a and the electrode portions of the semiconductor chip 4 are electrically connected by the wire bonding 7.
【００２３】また、半導体装置１には、リペアシート９
が設けられており、パッケージＨＰとプリント実装基板
Ｐとの間にリペアシート９が挟み込まれた構造となって
いる。The semiconductor device 1 has a repair sheet 9.
Is provided, and a repair sheet 9 is sandwiched between the package HP and the printed circuit board P.
【００２４】さらに、このリペアシート９は、図２に示
すように、パッケージＨＰの外形と同じ大きさ程度の形
状からなる、たとえば、ポリイミドテープなどの樹脂シ
ート（シート基材）９ａが設けられている。Further, as shown in FIG. 2, the repair sheet 9 is provided with a resin sheet (sheet base material) 9a, such as a polyimide tape, having a shape approximately the same size as the outer shape of the package HP. I have.
【００２５】また、樹脂シート９ａには、半導体装置
（図１）に設けられたはんだボール６が位置する部分
に、はんだボール６よりも少し大きい程度の円形の孔
（貫通孔）Ｈが形成されており、その樹脂シート９ａの
中心部には、熱伝導のよい金属、たとえば、銅からなる
加熱線９ｂが格子状に挟み込まれている。In the resin sheet 9a, a circular hole (through hole) H slightly larger than the solder ball 6 is formed at a portion where the solder ball 6 provided on the semiconductor device (FIG. 1) is located. In the center of the resin sheet 9a, a heating wire 9b made of a metal having good thermal conductivity, for example, copper, is sandwiched in a lattice shape.
【００２６】また、加熱線９ｂは、樹脂シート９ａの周
辺部近傍にも挟み込まれており、格子状に挟み込まれた
加熱線９ｂと樹脂シート９ａの周辺部近傍に挟み込まれ
た加熱線９ｂは接続されている。そして、加熱線９ｂの
一部は、加熱端子９ｂ1 として樹脂シート９ａのコーナ
部近傍から突出して設けられている。The heating wire 9b is also sandwiched in the vicinity of the periphery of the resin sheet 9a, and the heating wire 9b sandwiched in a lattice and the heating wire 9b sandwiched in the vicinity of the periphery of the resin sheet 9a are connected. Have been. Then, part of the heating wire 9b is projected from the corner regions of the resin sheet 9a is provided as a heating pin 9b 1.
【００２７】次に、本実施の形態の作用について図１、
図２を用いて説明する。Next, the operation of this embodiment will be described with reference to FIGS.
This will be described with reference to FIG.
【００２８】たとえば、プリント実装基板Ｐに半導体装
置１を実装する場合について説明する。For example, a case where the semiconductor device 1 is mounted on the printed circuit board P will be described.
【００２９】まず、プリント実装基板Ｐに形成された電
極Ｄにスクリーン印刷などによりはんだペースト印刷を
行う。そして、自動搬送機構などによってリペアシート
９がプリント実装基板Ｐ上に実装される。First, solder paste printing is performed on the electrodes D formed on the printed circuit board P by screen printing or the like. Then, the repair sheet 9 is mounted on the printed circuit board P by an automatic transport mechanism or the like.
【００３０】また、このリペアシート９は、前述したよ
うにプリント実装基板Ｐの電極Ｄの位置にはんだボール
６よりも少し大きい程度の孔Ｈが形成されているので、
リペアシート９をプリント実装基板Ｐ上に実装しても電
極Ｄは露出することになる。Further, since the repair sheet 9 has the hole H slightly larger than the solder ball 6 at the position of the electrode D of the printed circuit board P as described above,
Even if the repair sheet 9 is mounted on the printed circuit board P, the electrodes D will be exposed.
【００３１】その後、パッケージＨＰに設けられたはん
だボール６がそれぞれの電極Ｄと重合するようにプリン
ト実装基板Ｐに搭載され、パッケージＨＰとプリント実
装基板Ｐとによってリペアシート９を挟み込んだまま、
たとえば、はんだリフロー炉を通すことによってはんだ
付けが行われ、半導体装置１の電極部５とプリント実装
基板Ｐの電極Ｄが電気的に接続されることになる。Thereafter, the solder balls 6 provided on the package HP are mounted on the printed circuit board P so as to overlap with the respective electrodes D, and the repair sheet 9 is sandwiched between the package HP and the printed circuit board P.
For example, soldering is performed by passing through a solder reflow furnace, and the electrode portion 5 of the semiconductor device 1 and the electrode D of the printed circuit board P are electrically connected.
【００３２】次に、プリント実装基板Ｐに実装された半
導体装置１の取り外しのリペア作業を行う場合について
説明する。Next, a case will be described in which a repair operation for removing the semiconductor device 1 mounted on the printed circuit board P is performed.
【００３３】まず、取り外す半導体装置１のパッケージ
ＨＰ下部に位置しているリペアシート９の加熱端子９ｂ
1 をホットプレートなどのヒータによって加熱を行う。
そして、加熱線９ｂがパッケージＨＰに設けられたはん
だボール６が溶融する温度、たとえば、約２００℃程度
まで加熱されるとはんだボール６が溶融するので、作業
者がパッケージＨＰをプリント実装基板Ｐから取り外
す。First, the heating terminals 9b of the repair sheet 9 located below the package HP of the semiconductor device 1 to be removed
1 is heated by a heater such as a hot plate.
When the heating wire 9b is heated to a temperature at which the solder balls 6 provided on the package HP are melted, for example, about 200 ° C., the solder balls 6 are melted. Remove.
【００３４】また、パッケージＨＰを取り外したプリン
ト実装基板Ｐの所定の位置に、新たにパッケージＨＰを
取り付ける場合には、リペアシート９をプリント実装基
板Ｐ上に実装し、その上から電極部５と電極Ｄとが重合
するようにパッケージＨＰをプリント実装基板Ｐに実装
する。When a new package HP is to be attached to a predetermined position of the printed circuit board P from which the package HP has been removed, the repair sheet 9 is mounted on the printed circuit board P, and the electrode section 5 is connected to the repair sheet 9 from above. The package HP is mounted on the printed circuit board P such that the electrodes D overlap with each other.
【００３５】そして、再び、リペアシート９の加熱端子
９ｂ1 をヒータによって加熱し、加熱線９ｂを加熱する
ことによってはんだボール６を溶融させ、電極部５と電
極Ｄとを電気的に接続させる。[0035] Then, again, the heating terminal 9b 1 of the repair sheet 9 is heated by a heater, to melt the solder balls 6 by heating the heating wire 9b, thereby electrically connecting the electrode D electrode portion 5.
【００３６】ここで、パッケージＨＰとプリント実装基
板Ｐとの間には、前述したようにリペアシート９が介在
して設けられているので、半導体装置１の取り付けのリ
ペア作業時には、リペアシート９の厚さによって一定の
高さが保たれることになり、はんだボール６の高さばら
つきを安定させることができる。また、リペアシート９
がダムの役目をし、はんだボール６の溶融時のはんだ流
れを防止することができる。Here, since the repair sheet 9 is provided between the package HP and the printed circuit board P as described above, the repair sheet 9 is attached when the semiconductor device 1 is repaired. A certain height is maintained by the thickness, and the height variation of the solder ball 6 can be stabilized. Repair sheet 9
Can serve as a dam, and can prevent solder flow when the solder balls 6 are melted.
【００３７】それにより、本実施の形態によれば、半導
体装置１にリペアシート９を設けることにより、半導体
装置１のはんだボール６近傍を効率よく加熱することが
できるので、パッケージＨＰにダメージを与えることな
く、容易に効率よく半導体装置のリペア作業を行うこと
ができる。Thus, according to the present embodiment, by providing the repair sheet 9 on the semiconductor device 1, the vicinity of the solder balls 6 of the semiconductor device 1 can be efficiently heated, thereby damaging the package HP. Thus, the semiconductor device can be easily and efficiently repaired.
【００３８】また、半導体装置１の取り付け時にも、実
装時のはんだボール６の高さばらつきを安定させること
ができる。In addition, even when the semiconductor device 1 is mounted, the height variation of the solder balls 6 during mounting can be stabilized.
【００３９】さらに、本実施の形態では、熱伝導のよい
銅などの金属からなる加熱線９ｂ（図２）をリペアシー
ト９の中心部に設けたが、図３に示すように、たとえ
ば、ニッケル−クロム合金などの高抵抗材料からなる電
熱線を加熱線９ｃとして用いるようにしてもよい。Further, in the present embodiment, the heating wire 9b (FIG. 2) made of a metal such as copper having good heat conductivity is provided at the center of the repair sheet 9. However, as shown in FIG. -A heating wire made of a high resistance material such as a chromium alloy may be used as the heating wire 9c.
【００４０】この場合、樹脂シート９ａの対向するコー
ナ部に電圧を印加するための端子である電圧端子９
ｃ1 ，９ｃ2 を設け、それぞれの電圧端子９ｃ1 ，９ｃ
2 に所定の電圧を印加することによって半導体装置１
（図１）のはんだボール６を加熱溶融させ、半導体装置
１の取り外しや取り付けを行う。In this case, a voltage terminal 9 for applying a voltage to the opposite corner of the resin sheet 9a.
c 1 and 9c 2 are provided, and respective voltage terminals 9c 1 and 9c
2 by applying a predetermined voltage to the semiconductor device 1
The solder ball 6 (FIG. 1) is heated and melted, and the semiconductor device 1 is removed or attached.
【００４１】また、本実施の形態においては、格子状に
形成された加熱線９ｂ（図２）はそれぞれ接続固定され
ていたが、たとえば、図４に示すように、帯状の加熱線
９ｄを樹脂シート９ａの横の辺方向および縦の辺方向に
格子状に配置させ、それぞれの加熱線９ｄの一方の端部
は、加熱端子９ｄ1 として樹脂シート９ａから突出する
ように設けてもよい。Further, in the present embodiment, the heating wires 9b (FIG. 2) formed in a lattice shape are respectively connected and fixed. For example, as shown in FIG. the transverse sides and longitudinal sides direction of the sheet 9a is arranged in a grid, one end of each heating wire 9d may be provided so as to protrude from the resin sheet 9a as a heating pin 9d 1.
【００４２】この場合、加熱線９ｄが直交する部分の接
続固定がされていないので、たとえば、加熱端子９ｄ1
をヒータなどにより加熱し、半導体装置をプリント配線
基板に取り付けるリペア作業を行った後に、樹脂シート
９ａから加熱線９ｃを引き抜くことができ、他の電子部
品との電気的な接触などを防止することができる。In this case, since the portions where the heating wires 9d are orthogonal to each other are not connected and fixed, for example, the heating terminals 9d 1
After the heater is heated by a heater or the like and the semiconductor device is mounted on the printed circuit board, the heating wire 9c can be pulled out from the resin sheet 9a to prevent electrical contact with other electronic components. Can be.
【００４３】以上、本発明者によってなされた発明を発
明の実施の形態に基づき具体的に説明したが、本発明は
前記実施の形態に限定されるものではなく、その要旨を
逸脱しない範囲で種々変更可能であることはいうまでも
ない。Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.
【００４４】[0044]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下のとおりである。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.
【００４５】（１）本発明によれば、リペアシートによ
ってはんだボールのみに効率よく加熱を行うことができ
るので、パッケージにダメージを与えることなく、パッ
ケージの取り外しや取り付けを行うことができる。(1) According to the present invention, only the solder balls can be efficiently heated by the repair sheet, so that the package can be removed or attached without damaging the package.
【００４６】（２）また、本発明では、パッケージとプ
リント配線実装基板との間に介在して設けられたリペア
シートにより半導体装置の取り付け時にリペアシートの
厚さによってはんだボールの高さばらつきを安定して、
実装することができる。(2) According to the present invention, the height variation of the solder balls is stabilized by the thickness of the repair sheet at the time of mounting the semiconductor device by the repair sheet provided between the package and the printed wiring board. do it,
Can be implemented.
【００４７】（３）さらに、本発明においては、上記
（１），（２）により、半導体装置のリペア作業を容易
に短時間で行うことができる。(3) Further, in the present invention, the repair operation of the semiconductor device can be easily performed in a short time by the above (1) and (2).
【図１】本発明の一実施の形態によるプリント実装基板
に実装された半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device mounted on a printed circuit board according to an embodiment of the present invention.
【図２】本発明の一実施の形態による半導体装置に設け
られるリペアシートの説明図である。FIG. 2 is an explanatory diagram of a repair sheet provided in the semiconductor device according to one embodiment of the present invention;
【図３】本発明の他の実施の形態による半導体装置に設
けられるリペアシートの説明図である。FIG. 3 is an explanatory diagram of a repair sheet provided in a semiconductor device according to another embodiment of the present invention.
【図４】本発明の他の実施の形態による半導体装置に設
けられるリペアシートの説明図である。FIG. 4 is an explanatory diagram of a repair sheet provided in a semiconductor device according to another embodiment of the present invention.
１ 半導体装置 ２ キャリア基板（プリント配線基板） ３ 接着材 ４ 半導体チップ ５ 電極部 ５ａ 電極部 ６ はんだボール ７ ボンディングワイヤ ８ リッド ９ リペアシート ９ａ 樹脂シート（シート基材） ９ｂ 加熱線 ９ｂ1 加熱端子 ９ｃ 加熱線 ９ｃ1 ，９ｃ2 電圧端子 ９ｄ 加熱線 ９ｄ1 加熱端子 Ｐ プリント実装基板（プリント配線実装基板） Ｄ 電極部 ＨＰ パッケージ Ｈ 孔（貫通孔）DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Carrier board (printed wiring board) 3 Adhesive material 4 Semiconductor chip 5 Electrode part 5a Electrode part 6 Solder ball 7 Bonding wire 8 Lid 9 Repair sheet 9a Resin sheet (sheet base material) 9b Heating wire 9b 1 Heating terminal 9c Heating wire 9c 1 , 9c 2 Voltage terminal 9d Heating wire 9d 1 Heating terminal P Printed mounting board (printed wiring mounting board) D Electrode part HP package H hole (through hole)
Claims (5)
を載せ、裏面にはんだバンプをアレイ状に並べて外部端
子としたパッケージと、 前記パッケージと前記はんだバンプに対応した電極が設
けられたプリント配線実装基板との間に介在され、前記
はんだバンプに対応した複数の貫通孔を有するシート基
材と、前記シート基材に設けられ、前記はんだバンプを
加熱する加熱線とを備えるリペアシートとよりなり、前
記加熱線を加熱することにより前記はんだバンプを溶融
させ、前記パッケージを前記プリント配線実装基板から
自在に着脱することを特徴とする半導体装置。1. A package in which a semiconductor chip is mounted on a front surface of a printed wiring board and solder bumps are arranged in an array on the rear surface to form external terminals, and a printed wiring board on which electrodes corresponding to the package and the solder bumps are provided. A sheet base having a plurality of through holes corresponding to the solder bumps, and a repair sheet provided on the sheet base and having a heating wire for heating the solder bumps, A semiconductor device, wherein a heating wire is heated to melt the solder bumps, and the package is freely attached to and detached from the printed wiring board.
記加熱線が、高抵抗材料からなる電熱線よりなることを
特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein said heating wire comprises a heating wire made of a high-resistance material.
記加熱線が、銅よりなることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein said heating wire is made of copper.
を載せ、裏面にはんだバンプをアレイ状に並べて外部端
子としたパッケージを準備する工程と、 前記はんだバンプに対応した複数の貫通孔を有するシー
ト基材と、前記シート基材に設けられ、前記はんだバン
プを加熱する加熱線とを備えるリペアシートを準備する
工程と、 前記はんだバンプに対応した電極が設けられた前記パッ
ケージを実装するプリント配線実装基板を準備する工程
と、 前記プリント配線実装基板上に前記リペアシートを搭載
する工程と、 前記リペアシートが搭載された前記プリント配線実装基
板の電極と対応する前記はんだバンプを溶融することに
より電気的な接続を行う工程とを有することを特徴とす
る半導体装置の実装方法。4. A step of mounting a semiconductor chip on a front surface of a printed wiring board and arranging solder bumps on the back surface in an array to prepare a package as an external terminal, and a sheet base having a plurality of through holes corresponding to the solder bumps. Preparing a repair sheet provided with a material and a heating wire provided on the sheet base material for heating the solder bumps; and a printed wiring board for mounting the package provided with electrodes corresponding to the solder bumps. Preparing, and mounting the repair sheet on the printed wiring board, and electrically melting the solder bumps corresponding to the electrodes of the printed wiring board on which the repair sheet is mounted. Performing a connection.
を載せ、裏面に設けられた電極部にはんだバンプをアレ
イ状に並べて外部端子としたパッケージを準備する工程
と、 前記はんだバンプに対応した複数の貫通孔を有するシー
ト基材と、前記シート基材に設けられ、前記はんだバン
プを加熱する加熱線とを備えるリペアシートを準備する
工程と、 前記はんだバンプに対応した電極が設けられた前記パッ
ケージを実装するプリント配線実装基板を準備する工程
と、 前記パッケージの裏面に前記リペアシートを搭載する工
程と、 前記プリント配線実装基板に前記リペアシートが搭載さ
れた前記パッケージを実装し、前記はんだバンプを溶融
することにより電気的な接続を行う工程とを有すること
を特徴とする半導体装置の実装方法。5. A step of mounting a semiconductor chip on a front surface of a printed wiring board and arranging solder bumps on an electrode portion provided on the back surface in an array to prepare a package as an external terminal; A step of preparing a repair sheet including a sheet base having a through hole and a heating wire provided on the sheet base and heating the solder bumps; and the package provided with electrodes corresponding to the solder bumps. Preparing a printed wiring board to be mounted; mounting the repair sheet on the back surface of the package; mounting the package with the repair sheet mounted on the printed wiring board; melting the solder bumps And a step of making electrical connection by performing the method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9240721A JPH1187906A (en) | 1997-09-05 | 1997-09-05 | Semiconductor device and packaging method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9240721A JPH1187906A (en) | 1997-09-05 | 1997-09-05 | Semiconductor device and packaging method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1187906A true JPH1187906A (en) | 1999-03-30 |
Family
ID=17063722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9240721A Pending JPH1187906A (en) | 1997-09-05 | 1997-09-05 | Semiconductor device and packaging method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1187906A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005268473A (en) * | 2004-03-18 | 2005-09-29 | Ricoh Microelectronics Co Ltd | Manufacturing method of member for extension boards |
| US7500308B2 (en) | 1999-09-01 | 2009-03-10 | Fujitsu Limited | Method of detaching electronic component from printed circuit board |
| JP2010129967A (en) * | 2008-12-01 | 2010-06-10 | Alps Electric Co Ltd | Electronic circuit module |
| JP2012195452A (en) * | 2011-03-16 | 2012-10-11 | Fujitsu Ltd | Electronic component and electronic component assembly apparatus |
-
1997
- 1997-09-05 JP JP9240721A patent/JPH1187906A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7500308B2 (en) | 1999-09-01 | 2009-03-10 | Fujitsu Limited | Method of detaching electronic component from printed circuit board |
| JP2005268473A (en) * | 2004-03-18 | 2005-09-29 | Ricoh Microelectronics Co Ltd | Manufacturing method of member for extension boards |
| JP2010129967A (en) * | 2008-12-01 | 2010-06-10 | Alps Electric Co Ltd | Electronic circuit module |
| JP2012195452A (en) * | 2011-03-16 | 2012-10-11 | Fujitsu Ltd | Electronic component and electronic component assembly apparatus |
| US9307686B2 (en) | 2011-03-16 | 2016-04-05 | Fujitsu Limited | Electronic component and electronic component assembly apparatus |
| US9545044B2 (en) | 2011-03-16 | 2017-01-10 | Fujitsu Limited | Electronic component assembly apparatus |
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