JPH07226455A - Semiconductor package and its manufacturing method - Google Patents

Abstract

PURPOSE:To provide a manufacturing method capable of manufacturing the semiconductor package and assuring thin and compact form at low cost with high reliability and high yield. CONSTITUTION:The semiconductor package is provided with a substrate 7 having wiring circuit including a connecting part, a semiconductor chip 8 packaged in facedown mode on one main surface of the substrate 7, a resin layer 11 filling up the gap between the lower surface of the semiconductor chip 8 and the upper surface of the substrate 7 as well as a planar outer connecting terminal 9 electrically connecting to the semiconductor chip 8 so as to be led out and exposed in the other main surface side of the substrate 7. On the other hand, the manufacturing method is composed of the four steps as follows, i.e., the first step of aligning and arranging step of the connecting part 7a of the substrate 7 corresponding to the electrode terminal part 8a of the semiconductor chip 8 with one main surface of the substrate 7 having a wiring circuit including the connecting part, the second step of fixing and connecting the connected parts of the connecting part 7a of the corresponded and aligned substrate 7 surface and that of electrode terminal part 8a of the semiconductor chip 8 to be assembled, the third step of filling the gap between the assembled substrate 7 surface and the lower surface of the semiconductor chip 8 and the fourth step of setting the filled up resin 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a thin or compact semiconductor package suitable for a card type external storage medium and a manufacturing method thereof.

[0002]

2. Description of the Related Art For example, various memory cards are known as a storage device capable of recording and storing various data. In the configuration of this type of card, there are restrictions on the size and thickness of the card, so that, for example, a semiconductor chip (such as an IC element) that contributes to a memory function or the like.
The thin mounting is required, and it is desired that the package be made as thin and compact as possible.

To meet such demands for thin mounting, for example, mounting in a space of 1 mm or less in the thickness direction, TAB (Tape Automated Bonding) method, flip chip mounting, COB (Chip on Board) The law is known. Further, as an example of a thin package, for example, as shown in a cross-sectional view of a main part configuration in FIG. 7, a circuit board 2 on which a required semiconductor chip 1 or the like is mounted and mounted on one main surface, and a through hole 3 are used to form A module having a configuration including an external connection terminal 4 led out to the other main surface side of the circuit board 2 and a mold resin layer 5 for sealing and covering the mounting area surface of the semiconductor chip 1 or the like is known. ing. In addition, in FIG. 7, 6 is a bonding wire.

[0004]

However, the above-mentioned T
In the case of the AB method, in addition to the relatively high manufacturing cost of the carrier tape, a dedicated die and a bonding tool are required according to the package size in the mounting process, so that the assembly cost is relatively high. It is economically problematic as a practical means.

On the other hand, in the case of flip-chip mounting and the COB method, how to secure KGN (Known Good Die) is a problem. Although it is necessary to develop burn-in in a chip state, it is difficult to perform burn-in on the semiconductor chip 1 that is normally used, and thus there is a reliability problem. In other words, this type of semiconductor chip (IC chip) 1
Since it is not possible to perform so-called burn-in, which detects defects even if they appear in the semiconductor chip itself in the near future, it has the potential to cause trouble at the initial stage of practical use after mounting and modularization. , It can be said that there is a problem in terms of reliability. The reliability problem can be dealt with by means of attachment / detachment / replacement of the mounted semiconductor chip 1 or the like, that is, repair or rework, but as a result, the assembly cost will be further increased. At the same time, it is often technically difficult. In particular, when the semiconductor chip 1 having the increased number of electrode terminals is mounted by the COB method, it takes a lot of time to assemble, resulting in an increase in cost.

Further, in terms of compactness, the TAB method and the COB method require a larger mounting area than the flip-chip mounting, which hinders the compactness. Also, in the case of the packaged module by the one-sided mold, a general (normal)
In the transfer molding process, the flow of the bonding wire 6 and the disconnection of the connecting portion are likely to occur, which is problematic in terms of reliability and yield. in addition,
At present, it is difficult to control the height of the bonding wire 6 to 0.1 mm or less, which is an obstacle to forming a thin package. Further, when connecting the bonding wire 6 to the external connection terminal, an extra space is required outside the semiconductor chip 1, which hinders the compactness.

The present invention has been made in view of the above circumstances, and is a thin and compact semiconductor package capable of ensuring low cost and high reliability, and the semiconductor package can be manufactured at low cost and high yield. The purpose is to provide a manufacturing method.

[0008]

A semiconductor package according to the present invention includes a substrate having a wiring circuit including a connecting portion, a semiconductor chip mounted face down on one main surface of the substrate, and the semiconductor chip. A resin layer filling the space between the lower surface and the upper surface of the substrate, and a flat type external connection terminal electrically connected to the semiconductor chip via a connection portion and led out and exposed to the other main surface side of the substrate. Further, if necessary, the electrode terminal portion of the semiconductor chip and the connecting portion of the substrate are solid-phase diffusion bonded, and the first semiconductor package manufacturing method according to the present invention has one main surface. A wiring circuit including a connection portion (connection pad), and the electrode terminal portion of the semiconductor chip is connected to the contact portion on the one main surface of the substrate in which the planar type external connection terminal is led out and exposed on the other main surface. Correspond,
A step of aligning and arranging semiconductor chips, a step of assembling a module body by fixedly connecting the corresponding and aligned substrate surfaces and connected parts of the semiconductor chips, and a top surface of the substrate of the assembled module body and a semiconductor The method is characterized by comprising a step of filling a gap formed by the lower surface of the chip with a sealing resin and a step of curing the filled resin.

A second method of manufacturing a semiconductor package according to the present invention is provided with a wiring circuit including a connection portion (connection pad) on one main surface and deriving and exposing a flat type external connection terminal on the other main surface. A step of aligning and arranging the semiconductor chip with the electrode terminal portion of the semiconductor chip corresponding to the connecting portion on the one main surface of the substrate, and connecting the substrate and the semiconductor chip arranged in the corresponding / alignment A step of assembling the main body by solid-phase diffusion / bonding of the parts to each other, and a step of filling a sealing resin in a gap formed by the upper surface of the substrate and the lower surface of the semiconductor chip in which the connected parts are solid-phase diffused / bonded, And a step of curing the filling resin. Further, a third method for manufacturing a semiconductor package according to the present invention includes a wiring circuit including a connecting portion (connection pad) made of gold on one main surface and deriving a flat type external connection terminal on the other main surface. A step of aligning and arranging the semiconductor chip on the one main surface of the exposed substrate, in which a gold bump provided on an electrode terminal portion of the semiconductor chip is made to correspond to the connecting portion, and the corresponding / position is arranged. A step of applying a load to the substrate and the semiconductor chip to bring the connected portions into close contact with each other; and a step of filling a gap formed by the upper surface of the substrate and the lower surface of the semiconductor chip in which the connected portions are brought into close contact with a sealing resin, And a step of curing the filled resin while applying a load in a state of being filled with the resin to prevent displacement of the connected portion.

According to the present invention, a resin-based substrate or a ceramic-based substrate is provided on one main surface (one surface) of a soldering chip (IC).
Chips, etc. are mounted, and the mold sealing resin layer on the upper surface side of the mounted components is omitted to achieve thinness, compactness, and cost reduction. The essence is that the external connection terminals are led out to the non-mounting surface side so that the semiconductor package can be simply formed. That is, the mold sealing resin layer on the upper surface side is omitted, and the semiconductor package is made thinner accordingly. In other words, silicon (S
i) It was made paying attention to the fact that the mold sealing resin layer on the upper surface side can be eliminated by utilizing the fact that the surface of the semiconductor chip is dense and robust.

In the manufacturing process of the semiconductor package, when the corresponding and aligned connection terminals (connected portions) of the substrate surface and the semiconductor chip are fixedly connected and assembled, the connection terminals (connection portions) on the substrate surface are connected. In addition, for example, a relatively simple means such as a structure in which a conductive paste is formed and the corresponding connection terminals of the semiconductor chip are press-fitted / connected may be adopted. In addition, the fixed connection between the connected parts,
It is also possible to adopt a method in which so-called solid phase diffusion is caused to join between the connection portion on the substrate surface and the electrode terminal portion of the semiconductor chip. That is, the connection part of the substrate and the corresponding electrode terminal part of the semiconductor chip are heated to a required temperature at which solid phase diffusion is possible, and the metals forming the connection target part, for example, the connection pad (connection part) made of gold and the gold. It is possible to adopt a means for performing solid-phase diffusion with the bumps (electrode terminal portions) made of metal to electrically and mechanically bond them. In this solid-phase diffusion / bonding method, the connection pads (connecting portions) of the substrate, the bumps (electrode terminal portions) of the semiconductor chip, or both of them are required in advance before the positioning and arrangement of the substrate and the semiconductor chip. A method of heating to a temperature at which solid phase diffusion is possible is adopted.

[0012]

The semiconductor package according to the present invention is closely sealed by the mounted and mounted semiconductor chip itself, and in addition to being protected and stabilized by the fine sealing, the semiconductor package is thin. Compactness and compactness are easily achieved. In other words, since the characteristics are stable and the reliability is high, it exhibits a function as a thin and compact semiconductor package suitable for mounting cards, for example.

Further, according to the method of manufacturing a semiconductor package of the present invention, a condition that the filling (sealing) resin exhibits appropriate fluidity between the assembled substrate surface and the semiconductor chip lower surface (gap). Alternatively, liquid resin (for example, epoxy resin) is used, and is poured and cured by, for example, a capillary phenomenon so that the semiconductor chip previously assembled is not damaged, for example, the terminal connection portion is peeled off, and the yield is improved. It is possible to obtain a highly reliable semiconductor package. In particular, when solid-phase diffusion of the connected parts is applied to the mounting of the semiconductor chip on the substrate, the reliability of electrical connection can be further improved.

[0014]

EXAMPLES Below, FIGS. 1 (a), (b), FIG. 2, FIG. 3, and FIG.
An embodiment of the present invention will be described with reference to (a), (b), FIG. 5, and FIGS. 6 (a), (b).

Embodiment 1 FIG. 1 (a) is a perspective view of the upper surface side of an example of the configuration of the essential parts of a semiconductor package according to the present invention, and FIG. 1 (b) is an example of the configuration of the essential parts of a semiconductor package according to the present invention. 3 is a perspective view of the lower surface side of FIG. Here, 7 is a region for mounting and mounting a semiconductor chip on one main surface (a wiring circuit including a connecting portion)
A circuit board 8 including a required semiconductor chip (IC chip or the like) mounted and mounted on one main surface of the circuit board 7,
Reference numeral 9 denotes a flat type external connection terminal led out to the other main surface side of the circuit board 7 through a through hole (not shown) of the circuit board 7. A resin layer is filled and formed in the gap between the surface of the circuit board 7 and the lower surface of the mounted / mounted semiconductor chip 8 to reinforce the joint.

Next, an example of manufacturing the semiconductor package having the above structure will be described.

FIG. 2 is a sectional view schematically showing a mode of module assembly. First, a wiring circuit including a connection portion (connection pad) for flip-chip mounting is provided on one surface (on one main surface), and From the wiring circuit including the connection part to the through hole
Flat type external connection terminal 9 on the back surface (other main surface) via 10
A resin-based circuit board 7 having a configuration derived from is prepared. This resin-based circuit board 7 has, for example, a length of 17 mm, a width of 7 mm, and a thickness.
A semiconductor chip (IC chip) 8 having a length of 0.2 mm, a length of 15 mm, a width of 5 mm and a thickness of 0.25 to 0.30 mm is mounted and mounted.

Next, the resin-based circuit board 7 is fixed on a stage of a screen printing machine equipped with a vacuum suction mechanism, for example, and the connection terminals on the board 7 corresponding to the electrode pads of the semiconductor chip 8 are connected. The pad 7a is formed. That is, using a metal mask having openings (for example, 150 × 150 μm) corresponding to the electrode pads (for example, 100 × 100 μm) of the semiconductor chip 8 to be mounted / mounted, silver paste is applied to one main surface of the resin-based circuit board 7. (For example, silver particle size 1μm, viscosity 1000ps) is screen-printed and the connection pad 7a has a diameter of 150μm and a height of about 80μm on the surface of the connection terminal.
To form. On the other hand, a gold bump for connection on the electrode pad surface of the semiconductor chip 8 by electroplating or a gold ball bump (for example, height
A semiconductor chip 8 on which 30 μm, 100 × 100 μm) 8a is formed is prepared.

On the one main surface of the resin-based substrate 7, the connection pads 7a and the gold bumps 8a for connection of the semiconductor chip 8 are aligned and arranged, and the resin-based substrate 7 is formed.
Corresponding and aligned connected parts of semiconductor chip 8
By pressing between 7a and 8a, at least the tip of the connection bump 8a is embedded in the connection pad 7a and fixedly connected to assemble the module. In this state, the so-called flip chip bonding is completed by thermosetting the silver paste forming the connection pad 7a,
Electrical connection is achieved for both fixing and holding to the resin substrate 7. In addition, in this step, when warping may occur on the resin-based substrate 7, an appropriate amount (for example, 0.1 mm ³ or less) of thermosetting resin (thermosetting is applied) on the area surface where the connection pad 7a is not formed. It is desirable to apply a mold adhesive). However, in this case, it is necessary to heat and preliminarily cure at the time of pressurizing the flip chip bonding.

After that, a treatment with a sealing resin is performed. That is, the sealing resin is poured and filled into the gap between the lower surface of the semiconductor chip 8 and the upper surface of the resin substrate 7 from one end side of the gap by utilizing what is called a capillary phenomenon. In this selective resin treatment, it is preferable that a sufficient amount of resin is filled in the gap portion and that a part of the side surface portion of the semiconductor chip 8 goes around. In this way, after the required resin treatment is performed, the filled resin is cured (solidified) by heat or the like to obtain a semiconductor package having a configuration as shown in a sectional view in FIG. Here, the semiconductor chip 8 of the semiconductor package is not only better fixed to the surface of the resin substrate 7 by the filled resin layer 11, but also insulated from the surface of the resin substrate 7 of the semiconductor chip 8. Protection etc. are also aimed at. On the other hand, although the upper surface of the semiconductor chip 8 is exposed, the exposed surface of the semiconductor chip 8 is surface-protected because silicon, which is a material, is dense and robust, so that reliability or the like due to this point does not matter. confirmed.

Example 2 In the semiconductor chip 8 of Example 1, so-called selective plating or vapor deposition (using a solder mask)
By using solder (for example, 63Sn-37Pb) with connection bumps 8a having a height of 100 μm formed on the electrode pad surface (100 × 100 μm), as the resin-based substrate 7, the connection pads 7a on the main surface are soldered. A semiconductor chip 8 is positioned and temporarily fixed on one main surface of the resin-based substrate 7 by using a frib chip bonder by using a paste screen-printed product, and then the semiconductor chip 8 is passed through a reflow furnace to carry out the soldering. It was fixed by heating above the melting temperature (183 ° C).

Next, a resin was selectively filled under the same conditions as in Example 1 to obtain a semiconductor package. This semiconductor package was thin and compact, had high characteristic reliability, and had a good yield, as in the case of Example 1.

Embodiment 3 FIGS. 4 (a) and 4 (b) schematically show an embodiment of this embodiment. First, a flip including a connecting portion (connection pad) 7a made of gold on one main surface. Equipped with a wiring circuit for chip mounting,
Alumina-based substrate (or aluminum-nitride-based substrate or resin-based substrate) with flat type external connection terminals led out and arranged on the other main surface
7 and gold bumps 8b (height) on the electrode terminal (electrode pad) surface by electroplating (or ball bonding)
A semiconductor chip 8 having a size of 30 μm and a size of 100 × 100 μm) was prepared.

Next, the substrate 7 and the semiconductor chip 8
As shown schematically in FIG. 4 (a), positioning, positioning and bonding were performed on the stage 12 surface of the flip chip bonder.
In this positioning / arrangement / bonding, first, in order to prevent the warp of the substrate 7 and to lay it flat, the substrate 7 is vacuum-sucked on the surface of the stage 12, and at least the gold connection pads 7a of the substrate 7 are used.
Was heated to a predetermined temperature, for example, in the range of 350 ° C to 450 ° C. Then, gold bumps 8b formed on at least the electrode pad 8a surface of the semiconductor chip 8 fixed to the pickup head 13 of the flip chip bonder by vacuum suction.
Was heated to a predetermined temperature, for example, in the range of 350 ° C to 450 ° C. After that state, the gold bumps 8b formed on the surface of the electrode pads 8a of the semiconductor chip 8 are aligned and arranged on the gold connection pads 7a of the substrate 7, and then the connection pads 7a and the gold bumps 8b are formed. In order to perform solid phase diffusion connection between the connected parts, a predetermined load (pressurization) in the range of, for example, 10 g to 100 g is applied to one bump (height 30 μm, size 100 × 100 μm) from above the semiconductor chip 8. It was

The solid-phase diffusion connection referred to here is to give plastic deformation to a boundary surface between metals of the same kind or different kinds,
It means that the destruction of the oxide film at the joint and the activation of the surface are promoted, and that when the new surfaces come into contact with each other, both metals diffuse and join.

In that sense, in the present embodiment, the solid-phase diffusion connection of the connection pad 7a and the gold bump 8b made of gold is made, but as long as they are metals capable of solid-phase diffusion connection, they are limited to the examples. Instead, various metals can be connected to each other without departing from the spirit of the invention. For example, there are combinations of tin-made connecting portions (connection pads) and gold-made electrode terminal portions (gold bumps), and combinations of aluminum-made connecting portions (connection pads) and gold-made electrode terminal portions (gold bumps). .

Also, in the above embodiment, a flip chip. Both the gold-made connection pads 7a of the substrate 7 placed on the stage 12 surface of the bonder and the gold bumps 8b formed on the semiconductor chip 8 mounted on the pickup head 13 were heated to a predetermined temperature, but solid-phase diffusion connection is possible. In that case, it is also possible to heat only one of them to a predetermined temperature. Furthermore, if solid phase diffusion connection is possible without applying temperature by using ultrasonic vibration, for example, there is no need to heat.

Next, taking out from the surface of the stage 12,
The space between the substrate 7 and the semiconductor chip 8 was filled with the sealing resin under the same conditions as in the case of the first embodiment. In the resin filling process, when the temperature is appropriately raised, the capillary phenomenon is promoted, and the resin filling process can be performed more easily. Thus, after the required resin filling process is performed, the solid resin diffusion connection portion (connection pad 7a and gold bump 8b) is cured by curing the filling resin 111, as schematically shown in FIG. 4 (b). A semiconductor package was manufactured in which the fixing of the above was made firm.

Embodiment 4 FIGS. 5 (a), 5 (b) and 5 (c) schematically show an embodiment of this embodiment. First, a connecting portion (connection pad) 7a made of gold on one main surface is used. Equipped with a wiring circuit for flip chip mounting, including
Resin-based board (or alumina-based board or aluminum-nitride-based board) with flat type external connection terminals led out and arranged on the other main surface
7 and the electrode terminal portion (gold bump) 8b (height on the electrode pad surface by electroplating (or ball bonding))
A semiconductor chip 8 having a size of 30 μm and a size of 100 × 100 μm) was prepared. The resin substrate 7 and the semiconductor chip 8
As shown in Fig. 5 (a), the flip chip bonder was positioned and placed on the stage 12 surface. In this positioning / arrangement, first, in order to prevent warping of the resin-based substrate 7 and to lay it flat, the resin-based substrate 7 is vacuum-sucked, and then the gold-made connection pads 7a of the resin-based substrate 7 are connected to the electrodes of the semiconductor chip 8. Formed on the surface of the pad 8a and aligning the gold bump 8b.
After the arrangement, a load (pressurization) was applied from above the semiconductor chip 8 in order to bring the connection pads 7a and the gold bumps 8b into close contact with the connected portions.

Next, while maintaining the pressure applied, a sealing resin was filled between the resin-based substrate 7 and the semiconductor chip 8 under the same conditions as in the case of the first embodiment. In the resin filling process, when the temperature is appropriately raised, the capillary phenomenon is promoted, and the resin filling process can be performed more easily.
Thus, after performing the required resin filling process, as schematically shown in FIG. 5B, the heating process was performed while maintaining the required load on the semiconductor chip 8 side, for example. By this heat treatment, the filling resin 11 is cured to avoid the positional displacement of the connected parts (the connection pads 7a and the gold bumps 8b) while ensuring close contact, while the semiconductor chip 8 is attached to the surface of the resin-based substrate 7. A fixed and held semiconductor package was manufactured. Figure 5
(c) is a cross-sectional view of the structure of this semiconductor package.

In the case of this manufacturing method, high-temperature heating associated with solid phase diffusion / connection (bonding) is not required, so that the substrate 7
When connecting the semiconductor chip 8 and the semiconductor chip 8, the stress strain due to thermal expansion does not exist in the joint. This provides an advantageous reliability guarantee in a reliability test such as a high-low temperature thermal cycle which is performed later as a semiconductor package.

FIG. 6 is a plan view showing a structural example of the semiconductor package manufactured (manufactured) by the manufacturing means from the side of the flat type external connection terminal 9 in a perspective view. In this structural example, the size is 7 × 7 mm. When a semiconductor chip 8 having a size of 5 × 5 mm is combined with the substrate 7, the substrate 7 has a margin of 1 mm on each side in consideration of the wraparound of the filling resin 11. In addition, the planar external connection terminals 9 that are led out and arranged on the other main surface of the substrate 7 are, for example, LGA (Land Grid Arra
y) and BGA (Ball Grid Array) with a pin pitch of 1 m
The pins are arranged in a zigzag pattern with m and a grid diameter of 0.5 mm, and one corner of the substrate 7 is cut to show the pin position. When this configuration is adopted, since solder is not used in the connected portion, there is no obstacle to solder reflow when mounting / mounting the semiconductor package on a substrate or the like.

Although a configuration example using a resin-based circuit board as the circuit board has been described above, the present invention is not limited to this example, and various modifications can be made without departing from the spirit of the invention. It can be taken. For example, an alumina-based circuit board or an aluminum nitride-based circuit board may be used.
The size thereof is also selected according to the size of the semiconductor chip to be mounted / mounted. Further, the identification mark of the semiconductor package may be printed on the exposed surface of the semiconductor chip.

Further, according to this configuration, the thickness of the substrate 7
0.2-0.25mm, semiconductor chip thickness 0.25 0.3mm, substrate 7
If the gap between the surface and the semiconductor chip is 0.03 mm, a semiconductor package having a total thickness of 0.5 to 0.6 mm can be realized.

[0035]

As can be seen from the above description, in the semiconductor package according to the present invention, since the so-called mold resin layer is omitted or eliminated, the semiconductor package is made thin and compact at least by that amount, and the reliability of the characteristics or functions is improved. Since it is high, it can be said that it is suitable as a functional component for a card, for example. In particular, the reduction in thickness means that the thickness of the resin substrate and the selection / setting range of the thickness of the IC chip to be mounted / mounted can be expanded, and the characteristics or characteristics corresponding to the application can be obtained. It can be said to contribute to the expansion of applications because it allows adjustment of functions. Furthermore, since the electrical connection between the semiconductor chip and the substrate side is not made by wire bonding, it is possible to improve the mounting efficiency, and in addition, because the inductance can be reduced in terms of the circuit, the signal speed can be increased. obtain.

Further, when the conventional semiconductor chip is connected by wire bonding, the position of the electrode pad is restricted, but in the case of the semiconductor package connection structure of the present invention,
It is also possible to arbitrarily select the setting position of the electrode pad of the semiconductor chip. And this will revolutionize the design concept of semiconductor chips.

Further, according to the method of manufacturing a semiconductor package of the present invention, the semiconductor package having the excellent function as described above can be manufactured with high yield and in mass production, which leads to cost reduction. Together, they can bring many practical advantages. In the COB method and the flip-chip mounting in which a plurality of chips are directly mounted on the substrate, it is difficult to guarantee the reliability of each chip because burn-in cannot be performed as pointed out above. On the other hand, since the semiconductor package according to the present invention can be subjected to burn-in after resin sealing, when mounted on a substrate or the like, a highly reliable mounted circuit device without using a so-called defective product repair technique. Can be configured. In other words, by mounting and mounting the semiconductor package according to the present invention, high reliability can be guaranteed, and as a result, yield can be improved and manufacturing cost can be reduced.

[Brief description of drawings]

1A and 1B show an example of a main part configuration of a semiconductor package according to the present invention, where FIG. 1A is a perspective view of an upper surface side, and FIG. 1B is a perspective view of a lower surface side.

FIG. 2 is a sectional view showing a configuration example of a main part of a semiconductor module in a manufacturing process of a semiconductor package according to the present invention.

FIG. 3 is a sectional view showing a configuration example of a main part of a semiconductor package according to the present invention.

FIG. 4 is a view showing an example of a main part configuration of a semiconductor module in another manufacturing process of a semiconductor package according to the present invention,
(a) is a cross-sectional view showing a state in which a semiconductor chip is positioned and arranged on one main surface of a substrate and is pressed, and (b) is a cross-sectional view of a semiconductor package manufactured by filling and curing a resin in a pressed state.

FIG. 5 is a diagram showing a configuration example of a main part of a semiconductor module in another manufacturing process of a semiconductor package according to the present invention,
(a) is a sectional view showing a state where a semiconductor chip is positioned and disposed on one main surface of a substrate and is pressed, (b) is a sectional view showing a state where resin is filled in a pressed state, (c) is a manufactured semiconductor package Sectional view of.

FIG. 6 is a plan view perspectively showing a configuration example of a semiconductor package according to the present invention.

FIG. 7 is a cross-sectional view showing a configuration of a main part of a conventional semiconductor package.

[Explanation of symbols]

1, 8 ... IC chip 2, 7 ... Resin-based circuit board
3, 10 ... Through hole 4, 9 ... Planar external connection terminal 5 ... Mold resin layer 6 ... Bonding wire 7a ... Connection part (connection pad) 8a ... Electrode terminal 8b ... Connection bump 11 ... Sealing resin layer

Claims (7)

[Claims] 1. A substrate provided with a wiring circuit including a connection portion,
A semiconductor chip mounted face down on one main surface of the substrate, a resin layer filling a space between the lower surface of the semiconductor chip and the upper surface of the substrate, and the other main surface of the substrate electrically connected to the semiconductor chip. A semiconductor package comprising: a flat type external connection terminal that is led out and exposed on the surface side. 2. A substrate provided with a wiring circuit including a connection portion,
A semiconductor chip mounted face down on one main surface of the substrate, a resin layer filling a space between the lower surface of the semiconductor chip and the upper surface of the substrate, and the other main surface of the substrate electrically connected to the semiconductor chip. A semiconductor characterized by comprising a planar type external connection terminal that is led out and exposed on the surface side, and the connection part of the substrate and the corresponding electrode terminal part of the semiconductor chip are solid-phase diffusion-connected. package. 3. A wiring circuit including a connecting portion on one main surface,
A step of aligning and arranging the semiconductor chip on the one main surface of the substrate where the flat type external connection terminal is led out and exposed on the other main surface, the electrode terminal portion of the semiconductor chip is made to correspond to the connecting portion, A step of assembling by fixing and connecting the corresponding and aligned substrate surfaces and the connected portions of the semiconductor chips, and a step of filling a gap formed by the upper surface of the substrate of the assembled module body and the lower surface of the semiconductor chip with a sealing resin. And a step of curing the filled resin, the method for manufacturing a semiconductor package. 4. A wiring circuit including a connecting portion on one main surface,
A step of aligning and arranging the semiconductor chip on the one main surface of the substrate where the flat type external connection terminal is led out and exposed on the other main surface, the electrode terminal portion of the semiconductor chip is made to correspond to the connecting portion, The step of assembling the corresponding and aligned substrate surfaces and the connected portions of the semiconductor chips by solid-phase diffusion connection, and filling the gap formed by the upper surface of the substrate of the assembled module body and the lower surface of the semiconductor chip with a sealing resin. And a step of curing the filled resin, the method for manufacturing a semiconductor package. 5. A wiring circuit including a connecting portion is provided on one main surface,
At least one of the bumps provided on the connection part of the one main surface of the substrate where the planar type external connection terminal is led out / exposed on the other main surface and the electrode terminal part of the semiconductor chip to be mounted / mounted at a predetermined temperature. And a step of aligning and arranging the semiconductor chips by associating bumps provided on the electrode terminal portions of the semiconductor chips with the connecting portions on the one main surface of the substrate, and aligning and arranging the semiconductor chips. A step of applying a load to the formed substrate and the semiconductor chip to perform solid phase diffusion bonding of the connected parts, and filling a sealing resin in a gap formed by the upper surface of the substrate and the lower surface of the semiconductor chip in which the connected parts are diffused and bonded. And a step of curing the filled resin, the method for manufacturing a semiconductor package. 6. A connection part made of gold on the one main surface of a substrate having a wiring circuit including a connection part made of gold on one main surface and having a flat type external connection terminal led out and exposed on the other main surface. And a step of heating at least one of the gold bumps provided on the electrode terminal part of the semiconductor chip to a predetermined temperature, and the step of providing the electrode terminal part of the semiconductor chip on the connection part made of gold on one main surface of the substrate. And aligning and arranging the semiconductor chips with the corresponding gold bumps, and applying a load to the substrate and the semiconductor chips arranged correspondingly and aligned to perform solid-phase diffusion bonding between the gold and gold connected parts. And a step of filling a sealing resin in a gap formed by the upper surface of the substrate and the lower surface of the semiconductor chip in which the connected portions are diffused and bonded together, and the step of curing the filled resin. Characterized by a half Method of manufacturing a body package. 7. A connecting portion made of gold on the one main surface of a substrate having a wiring circuit including a connecting portion made of gold on one main surface, and a flat type external connection terminal being led out and exposed on the other main surface. Corresponds to the gold bumps provided on the electrode terminals of the semiconductor chip,
A step of aligning and arranging the semiconductor chips; a step of applying a load to the substrates and the semiconductor chips arranged in correspondence and alignment to bring the connected parts into close contact; and an upper surface of the substrate having the connected parts in close contact with each other. And a step of filling a gap formed by the lower surface of the semiconductor chip with a sealing resin, and a step of applying a load in a state where the resin is filled and curing the filled resin while preventing positional displacement of the connected portion. A method of manufacturing a semiconductor package, comprising: