JP3332555B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To provide a manufacturing method capable of manufacturing the semiconductor package and assuring thin and compact form at low cost with high reliability and high yield. CONSTITUTION:The semiconductor package is provided with a substrate 7 having wiring circuit including a connecting part, a semiconductor chip 8 packaged in facedown mode on one main surface of the substrate 7, a resin layer 11 filling up the gap between the lower surface of the semiconductor chip 8 and the upper surface of the substrate 7 as well as a planar outer connecting terminal 9 electrically connecting to the semiconductor chip 8 so as to be led out and exposed in the other main surface side of the substrate 7. On the other hand, the manufacturing method is composed of the four steps as follows, i.e., the first step of aligning and arranging step of the connecting part 7a of the substrate 7 corresponding to the electrode terminal part 8a of the semiconductor chip 8 with one main surface of the substrate 7 having a wiring circuit including the connecting part, the second step of fixing and connecting the connected parts of the connecting part 7a of the corresponded and aligned substrate 7 surface and that of electrode terminal part 8a of the semiconductor chip 8 to be assembled, the third step of filling the gap between the assembled substrate 7 surface and the lower surface of the semiconductor chip 8 and the fourth step of setting the filled up resin 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a thin or compact semiconductor package suitable for a card-type external storage medium and a method of manufacturing the same.

[0002]

2. Description of the Related Art For example, various memory cards are known as storage devices capable of recording and storing various data. In the configuration of this kind of cards, since the size and thickness of the card are restricted, for example, a semiconductor chip (such as an IC element) contributing to a memory function or the like
It is required to mount as thin as possible, and it is desired to make the package as thin and compact as possible.

In order to meet such requirements for thin mounting, for example, mounting in a space of 1 mm or less in the thickness direction, TAB (Tape Automated Bonding), flip chip mounting, COB (Chip on Board) The law is known. As an example of a thin package, as shown in a sectional view of a main part in FIG. 7, for example, a circuit board 2 for mounting and mounting a required semiconductor chip 1 and the like on one main surface and the through hole 3 A module having a configuration including an external connection terminal 4 led to the other main surface side of the circuit board 2 and a mold resin layer 5 for sealing and covering a mounting area surface such as the semiconductor chip 1 is known. ing. In FIG. 7, reference numeral 6 denotes a bonding wire.

[0004]

However, the above-mentioned T
In the case of the AB method, in addition to the relatively high manufacturing cost of the carrier tape, a special mold and a bonding tool are required according to the package size in the mounting process, so that the assembly cost is relatively high. Practical means are economically problematic.

On the other hand, in the case of the flip chip mounting and the COB method, there is a problem how to secure KGN (Known Good Die). It is necessary, but difficult, to develop a burn-in in a chip state. Normally, it is not possible to perform a burn-in in advance on a semiconductor chip 1 to be used. That is, this kind of semiconductor chip (IC chip) 1
Cannot detect burn-in defects that will appear in the near future as semiconductor chips themselves, so it is not possible to perform burn-in, so there is a possibility that trouble will occur at the early practical stage after mounting and modularization. It can be said that there is a problem in terms of reliability. This reliability problem can be dealt with by means of attaching / detaching / exchanging the mounted semiconductor chip 1 or the like, that is, repair or rework, but as a result, the assembly cost is further increased. At the same time, it is often technically difficult. In particular, when the semiconductor chip 1 having the increased number of electrode terminals is mounted by the COB method, a large amount of time is required for assembly, which increases the cost.

Further, in terms of compactness, the TAB method and the COB method require a larger mounting area than the flip-chip mounting method, which hinders compactness. In the case of a packaged module using the single-sided mold, a general (normal)
In the transfer molding process, a flow of the bonding wire 6 and a detachment of the connection portion are apt to occur, which causes problems in reliability and yield. in addition,
At present, it is difficult to control the height of the bonding wire 6 to 0.1 mm or less, which is an obstacle to forming a thin package. Further, when connecting the bonding wires 6 to the terminals for external connection, an extra space is required outside the semiconductor chip 1, which hinders downsizing.

The present invention has been made in view of the above circumstances, and is a thin and compact semiconductor package which can guarantee low cost and high reliability, and can manufacture the semiconductor package at low cost and high yield. The purpose is to provide a manufacturing method.

[0008]

A semiconductor package according to the present invention includes a substrate provided with a wiring circuit including a connection portion, a semiconductor chip mounted face-down on one main surface of the substrate, and the semiconductor chip. A resin layer filling between the lower surface and the upper surface of the substrate, and a planar external connection terminal electrically connected to the semiconductor chip via a connection portion and led out and exposed to the other main surface of the substrate. If necessary, the electrode terminal portion of the semiconductor chip and the connection portion of the substrate are solid-phase diffusion-bonded, and the first method of manufacturing a semiconductor package according to the present invention is characterized in that one principal surface is provided. A wiring circuit including a connection portion (connection pad), and an electrode terminal portion of a semiconductor chip on the one main surface of the substrate on which a planar external connection terminal is led out and exposed on the other main surface. Corresponding,
A step of aligning and arranging the semiconductor chip, a step of fixing and connecting the corresponding and aligned substrate surfaces and the connected portions of the semiconductor chip to assemble a module body, and an upper surface and a semiconductor of the assembled module body. The method is characterized by comprising a step of filling the gap formed by the lower surface of the chip with a sealing resin, and a step of curing the filled resin.

According to a second method of manufacturing a semiconductor package according to the present invention, a wiring circuit including a connection portion (connection pad) is provided on one main surface, and a planar external connection terminal is led out and exposed on the other main surface. Aligning and arranging the semiconductor chip on the one main surface of the substrate with the electrode terminal portion of the semiconductor chip corresponding to the connection portion, and connecting the substrate and the semiconductor chip with the corresponding and aligned alignment. A step of assembling a main body by solid-phase diffusion and bonding of the parts, and a step of filling a sealing resin in a gap formed by the upper surface of the substrate and the lower surface of the semiconductor chip where the connected parts are solid-phase diffused and bonded, Curing the filling resin. Furthermore, a third method of manufacturing a semiconductor package according to the present invention includes a wiring circuit including a connection portion (connection pad) made of gold on one main surface, and leading out a flat external connection terminal on the other main surface. A step of aligning and arranging a semiconductor chip on the one main surface of the exposed substrate by associating a gold bump provided on an electrode terminal of a semiconductor chip with the connection section; A step of applying a load to the substrate and the semiconductor chip to bring the connected parts into close contact with each other, and filling a gap formed by the upper surface of the substrate and the lower surface of the semiconductor chip with the connected parts to each other with sealing resin, Curing the filled resin while applying a load while the resin is filled to prevent displacement of the connected portion.

According to the present invention, a chip (IC) is mounted on one main surface (one surface) of a resin-based substrate or a ceramic-based substrate.
Chip, etc.), and by omitting the mold sealing resin layer on the upper surface of the mounted component to achieve a thinner, more compact and lower cost. The outline is that the external connection terminals are led out to the (non-mounting surface side) and the semiconductor package can be easily formed. That is, the mold sealing resin layer on the upper surface side is omitted, and the thickness of the semiconductor package is reduced accordingly. In other words, silicon (S
i) The purpose of the present invention is to pay attention to the fact that the surface of the semiconductor chip is kept dense and robust, so that the mold sealing resin layer on the upper surface side can be eliminated.

In the process of manufacturing the semiconductor package, when connecting and assembling connection terminals (connected portions) of the substrate surface and the semiconductor chip corresponding to each other and aligned, when assembling the terminals, the connection terminals (connection portions) on the substrate surface are assembled. Alternatively, for example, a relatively simple means such as a structure in which a connection terminal of a corresponding semiconductor chip is press-fitted and connected may be employed, for example, by using a conductive paste. Further, the fixed connection between the connected parts is as follows.
It is also possible to adopt a method of causing a so-called solid phase diffusion to join between the connection part on the substrate surface and the electrode terminal part of the semiconductor chip. In other words, the connection portion of the substrate and the electrode terminal portion of the corresponding semiconductor chip are heated to a required temperature at which solid phase diffusion is possible, and the metals forming the connection portion, such as a connection pad (connection portion) made of gold and gold, are formed. And electric and mechanical joining means by solid-phase diffusion with a metal bump (electrode terminal portion). In this solid-phase diffusion / bonding method, prior to the positioning and arrangement of the substrate and the semiconductor chip, connection pads (connection parts) of the substrate, bumps (electrode terminal parts) of the semiconductor chip, or both of them are required in advance. A method of heating to a temperature at which solid phase diffusion is possible is employed.

[0012]

In the semiconductor package according to the present invention, the semiconductor chip itself mounted and mounted is densely sealed and the like, and not only is the protection and stabilization achieved with this dense sealing, but also a thin package. And compactness can be easily achieved. In other words, since the semiconductor device is stable in characteristics and has high reliability, it has a function as a thin and compact semiconductor package suitable for mounting cards, for example.

Further, according to the method of manufacturing a semiconductor package of the present invention, the filling (sealing) resin exhibits a suitable fluidity or the like between the assembled substrate surface and the lower surface of the semiconductor chip (gap). Alternatively, by using a liquid resin (for example, epoxy resin) and pouring it by, for example, capillary action, and hardening it, the semiconductor chip assembled in advance, such as breakage of the terminal connection portion, does not occur, and the yield is improved. A highly reliable semiconductor package can be obtained. In particular, when solid-phase diffusion between connected parts is applied to the mounting of the semiconductor chip on the substrate, the reliability of electrical connection can be further improved.

[0014]

FIG. 1A, FIG. 1B, FIG. 2, FIG. 3 and FIG.
An embodiment of the present invention will be described with reference to (a), (b), FIG. 5, and FIGS. 6 (a), (b).

Embodiment 1 FIG. 1 (a) is a perspective view of an upper surface side of an example of a main part configuration of a semiconductor package according to the present invention, and FIG. 1 (b) is an example of a main part configuration of a semiconductor package according to the present invention. Are perspectively shown on the lower surface side of FIG. Here, 7 is a region for mounting and mounting a semiconductor chip on one principal surface (a wiring circuit including a connection portion, etc.).
A required semiconductor chip (such as an IC chip) mounted and mounted on one main surface of the circuit board 7;
Reference numeral 9 denotes a planar external connection terminal led out to the other main surface side of the circuit board 7 through a through hole (not shown) of the circuit board 7. A gap between the surface of the circuit board 7 and the lower surface of the mounted and mounted semiconductor chip 8 is filled and formed with a resin layer and reinforced by joining and integrating.

Next, an example of manufacturing a semiconductor package having the above configuration will be described.

FIG. 2 is a cross-sectional view schematically showing a mode of assembling the module. First, a wiring circuit including a connection part (connection pad) for flip-chip mounting on one surface (one main surface) is provided. From the wiring circuit including the connection part to the through hole
A flat external connection terminal 9 is provided on the back (other main surface) through
A resin-based circuit board 7 having a configuration derived from the above is prepared. This resin-based circuit board 7 has, for example, a length of 17 mm, a width of 7 mm, and a thickness of 17 mm.
A semiconductor chip (IC chip) 8 of 0.2 mm, length 15 mm, width 5 mm, and thickness 0.25 to 0.30 mm is mounted and mounted.

Next, the resin-based circuit board 7 is fixed on, for example, a stage of a screen printing machine equipped with a vacuum suction mechanism, and connection on connection terminals on the board 7 corresponding to the electrode pads of the semiconductor chip 8 is performed. The pad 7a is formed. That is, using a metal mask having an opening (for example, 150 × 150 μm) corresponding to an electrode pad (for example, 100 × 100 μm) of the semiconductor chip 8 to be mounted / mounted, a silver paste is applied to one main surface of the resin-based circuit board 7. (For example, silver particle size 1μm, viscosity 1000ps) is screen printed, and connection pad 7a of 150μm in diameter and about 80μm in height is formed on the connection terminal surface.
To form On the other hand, a gold bump for connection is formed on the electrode pad surface of the semiconductor chip 8 by electroplating or a gold ball bump (for example, height
A semiconductor chip 8 having 30 μm, 100 × 100 μm) 8a is prepared.

On one main surface of the resin-based substrate 7, the connection pads 7a and the connection gold bumps 8a corresponding to the semiconductor chips 8 are aligned and arranged.
And corresponding connected parts of semiconductor chip 8
The modules 7a and 8a are press-fitted to each other so that at least the tip of the connection bump 8a is buried in the connection pad 7a and fixedly connected, thereby assembling a module. In this state, the so-called flip-chip bonding is completed by thermosetting the silver paste forming the connection pad 7a,
Both the fixing and the holding to the resin-based substrate 7 achieve the electrical connection. In this step, if there is a possibility that warpage may occur in the resin-based substrate 7, an appropriate amount (for example, 0.1 mm ³ or less) of a thermosetting resin (thermosetting resin) is applied to the surface of the region where the connection pads 7a are not formed. It is desirable to apply a mold adhesive). In this case, however, it is necessary to heat the flip chip bonding and to cure the flip chip bonding in advance.

Thereafter, a treatment with a sealing resin is performed. That is, the sealing resin is poured and filled into the gap between the lower surface of the semiconductor chip 8 and the upper surface of the resin substrate 7 from one end of the gap by using a so-called capillary phenomenon. In this selective resin treatment, it is preferable that the gap be filled with a sufficient amount of resin, and at the same time, a part of the space bend around the side surface of the semiconductor chip 8. After the required resin treatment is performed in this way, the filled resin is cured (solidified) by heat or the like, whereby a semiconductor package having a configuration as shown in a cross section in FIG. 3 is obtained. Here, the semiconductor chip 8 of the semiconductor package is not only better fixed to the surface of the resin-based substrate 7 by the filled resin layer 11, but also insulated from the surface of the resin-based substrate 7 of the semiconductor chip 8. Protection is also achieved. On the other hand, the upper surface of the semiconductor chip 8 is exposed. However, the exposed surface of the semiconductor chip 8 is protected because the material silicon is dense and robust, and the reliability is not a problem. confirmed.

Embodiment 2 In the semiconductor chip 8 in Embodiment 1, so-called selective plating or vapor deposition (using a solder mask)
Thus, a solder (for example, 63Sn-37Pb) having a connection bump 8a having a height of 100 .mu.m formed on an electrode pad surface (100.times.100 .mu.m) is used. As the resin-based substrate 7, the connection pad 7a on the main surface is soldered. After the semiconductor chip 8 is positioned and temporarily fixed to one main surface of the resin-based substrate 7 by a flip chip bonder by using a paste provided by screen printing of the paste, the semiconductor chip 8 is passed through a reflow furnace and the solder It was heated and fixed above the melting temperature (183 ° C).

Next, a resin was selectively filled under the same conditions as in Example 1 to obtain a semiconductor package. As in the case of the first embodiment, this semiconductor package was thin and compact, had high characteristic reliability, and had a good yield.

Embodiment 3 FIGS. 4 (a) and 4 (b) schematically show an embodiment of the present embodiment. First, a flip including a connection portion (connection pad) 7a made of gold on one main surface. Equipped with a wiring circuit for chip mounting,
Alumina-based substrate (or aluminum nitride-based substrate or resin-based substrate) with flat external connection terminals led out and arranged on the other main surface
7 and gold bumps 8b (height) on the electrode terminals (electrode pads) by electroplating (or ball bonding)
A semiconductor chip 8 having a size of 30 μm and a size of 100 × 100 μm) was prepared.

Next, the substrate 7 and the semiconductor chip 8
Was positioned, arranged, and bonded on the surface of the stage 12 of the flip chip bonder, as schematically shown in FIG.
In this positioning, arrangement, and bonding, first, the substrate 7 is vacuum-adsorbed on the surface of the stage 12 in order to prevent warpage of the substrate 7 and place the substrate 7 flat.
Was heated to a predetermined temperature in the range of, for example, 350 ° C to 450 ° C. Then, the gold bump 8b formed on at least the electrode pad 8a surface of the semiconductor chip 8 fixed to the pickup head 13 of the flip chip bonder by vacuum suction
Was heated to a predetermined temperature in the range of, for example, 350 ° C to 450 ° C. In this state, the gold bump 8b formed on the surface of the electrode pad 8a of the semiconductor chip 8 is positioned and arranged on the gold connection pad 7a of the substrate 7, and then the connection pad 7a and the gold bump 8b are formed. A predetermined load (pressurization) in the range of, for example, 10 g to 100 g is applied to one bump (height: 30 μm, size: 100 × 100 μm) from above the semiconductor chip 8 in order to perform solid phase diffusion connection between the connected portions. Was.

The solid phase diffusion connection referred to here is to give plastic deformation to the interface between the same or different metals,
It promotes destruction of the oxide film at the joint and activation of the surface, and means that both metals are diffused and joined when the new surfaces come into contact with each other.

In this sense, in the present embodiment, the solid-state diffusion connection of the gold connection pads 7a and the gold bumps 8b is used. Instead, various metal-to-metal connections may be employed without departing from the spirit of the invention. For example, there are combinations of a connection part (connection pad) made of tin and an electrode terminal part (gold bump) made of gold, and a connection part (connection pad) made of aluminum and an electrode terminal part (gold bump) made of gold. .

In the above embodiment, a flip chip is used. Both the gold connection pads 7a of the substrate 7 placed on the surface of the bonder stage 12 and the gold bumps 8b formed on the semiconductor chip 8 mounted on the pickup head 13 are heated to a predetermined temperature, but solid-phase diffusion connection is possible. Then, it is also possible to heat only one of them to a predetermined temperature. Further, for example, if solid-phase diffusion connection is possible without using temperature by using ultrasonic vibration, there is no need for heating.

Next, the stage is taken out from the surface of the stage 12, and
A sealing resin was filled between the substrate 7 and the semiconductor chip 8 under the same conditions as in the first embodiment. In the resin filling process, when the temperature is appropriately increased, the capillary phenomenon is promoted, and the resin filling process can be performed more easily. After the required resin filling process is performed in this way, as shown schematically in FIG. 4B, the filling resin 111 is cured to form the solid-phase diffusion connection portions (the connection pads 7a and the gold bumps 8b). A semiconductor package with a firm fixation was manufactured.

Embodiment 4 FIGS. 5 (a), 5 (b) and 5 (c) schematically show an embodiment of this embodiment. First, a connection portion (connection pad) 7a made of gold is formed on one main surface. Includes a wiring circuit for flip chip mounting, including
Resin-based board (or alumina-based board or aluminum nitride-based board) with flat external connection terminals led out and arranged on the other main surface
7 and the electrode terminals (gold bumps) 8b (height) on the electrode pad surface by electroplating (or ball bonding)
A semiconductor chip 8 having a size of 30 μm and a size of 100 × 100 μm) was prepared. The resin substrate 7 and the semiconductor chip 8
Was positioned and arranged on the surface of the stage 12 of the flip chip bonder as schematically shown in FIG. In order to prevent the warpage of the resin-based substrate 7 and place the resin-based substrate 7 flat, the positioning and the arrangement are performed by vacuum-absorbing the resin-based substrate 7 and then applying the electrodes of the semiconductor chip 8 to the gold connection pads 7a of the resin-based substrate 7. Align the gold bump 8b formed on the pad 8a surface.
After the placement, a load (pressure) was applied from above the semiconductor chip 8 in order to bring the connection portions of the connection pads 7a and the gold bumps 8b into close contact.

Next, a sealing resin was filled between the resin substrate 7 and the semiconductor chip 8 under the same conditions as in the first embodiment while maintaining the pressure. In the resin filling process, when the temperature is appropriately increased, the capillary phenomenon is promoted, and the resin filling process can be performed more easily.
After the required resin filling process was performed in this way, as shown schematically in FIG. 5B, a heat treatment was performed while maintaining a required load on the semiconductor chip 8 side, for example. By this heat treatment, the filling resin 11 is hardened to avoid the positional displacement of the connected parts (the connection pads 7a and the gold bumps 8b), while the semiconductor chip 8 is attached to the surface of the resin-based substrate 7 while ensuring the close contact. A fixed and held semiconductor package was manufactured. FIG.
(c) shows a cross section of the structure of the semiconductor package.

In the case of this manufacturing method, since high-temperature heating accompanying solid-phase diffusion and connection (joining) is not required, the substrate 7
When the semiconductor chip 8 is connected, no stress distortion due to thermal expansion is present in the joint. This provides an advantageous reliability guarantee in a reliability test of a semiconductor package, such as a high-low temperature thermal cycle, which is performed later.

FIG. 6 is a plan view showing an example of the structure of a semiconductor package manufactured (manufactured) by the manufacturing means as seen from the side of the planar type external connection terminal 9 side. In this example, the size is 7 × 7 mm. When the semiconductor chip 8 having a size of 5 × 5 mm is combined with the substrate 7, the substrate 7 has a margin of 1 mm on each side in consideration of the wraparound of the filling resin 11. The planar external connection terminals 9 led out and arranged on the other main surface of the substrate 7 are, for example, LGA (Land Grid Arra).
y) or BGA (Ball Grid Array) with a pin pitch of 1m
The pins are arranged in a houndstooth check pattern having a grid diameter of 0.5 mm and a grid diameter of 0.5 mm, and one corner of the substrate 7 is cut to indicate the pin positions. In the case where this configuration is adopted, no solder is used for the connected portion, so that there is no obstacle to the solder reflow performed when the semiconductor package is mounted and mounted on a substrate or the like.

Although a configuration example using a resin-based circuit board as the circuit board has been described above, the present invention is not limited to this example, and various modifications may be made without departing from the spirit of the invention. Can be taken. For example, an alumina circuit board or an aluminum nitride circuit board may be used.
The size and the like are also selected according to the size of the semiconductor chip to be mounted and mounted. Further, the identification mark of the semiconductor package may be printed on the exposed surface of the semiconductor chip.

According to this configuration, the thickness of the substrate 7 is
0.2 to 0.25mm, semiconductor chip thickness 0.25 0.3mm, substrate 7
If the gap between the surface and the semiconductor chip is 0.03 mm, a semiconductor package having a thickness of 0.5 to 0.6 mm as a whole can be realized.

[0035]

As can be seen from the above description, the semiconductor package according to the present invention is characterized by omitting or eliminating the so-called mold resin layer, so that the semiconductor package is at least thinner and more compact, and at the same time, has higher reliability in characteristics and functions. Therefore, it can be said that it is suitable as a functional component for a card, for example. In particular, the fact that the above-mentioned thinning is possible means that, on the other hand, the selection and setting range of the thickness of the resin-based substrate and the thickness of the IC chip to be mounted and mounted can be expanded. Since the function can be adjusted, it can be said that it also contributes to the expansion of applications. Furthermore, since the electrical connection between the semiconductor chip and the substrate side is not made by wire bonding, it is possible to improve the mounting efficiency, etc. In addition, since the inductance can be reduced also in the circuit, the signal speed can be increased. obtain.

Furthermore, when the conventional semiconductor chip is connected by wire bonding, the position of the electrode pad is restricted, but in the case of the connection configuration of the semiconductor package of the present invention,
It is also possible to arbitrarily select the setting positions of the electrode pads of the semiconductor chip. This will greatly change the design concept of the semiconductor chip.

Further, according to the method of manufacturing a semiconductor package according to the present invention, a semiconductor package having excellent functions as described above can be manufactured with high yield and mass production. It can be said that they bring many advantages in practical use. In the COB method and the flip-chip mounting method in which a plurality of chips are directly mounted on a substrate, as described above, since it is impossible to perform burn-in, it is difficult to guarantee the reliability of each chip. On the other hand, the semiconductor package according to the present invention can be burn-in after resin sealing, so that when mounted on a substrate or the like, a highly reliable mounting circuit device can be used without using a so-called defective product repair technique. Is possible. That is, by mounting and mounting the semiconductor package according to the present invention, high reliability can be guaranteed, and as a result, yield can be improved and manufacturing cost can be reduced.

[Brief description of the drawings]

1A and 1B show an example of a configuration of a main part of a semiconductor package according to the present invention, wherein FIG. 1A is a perspective view of an upper surface side, and FIG.

FIG. 2 is a sectional view showing an example of a configuration of a main part of a semiconductor module in a semiconductor package manufacturing process according to the present invention.

FIG. 3 is a sectional view showing an example of a configuration of a main part of a semiconductor package according to the present invention.

FIG. 4 shows an example of a main configuration of a semiconductor module in another manufacturing process of the semiconductor package according to the present invention;
(a) is a cross-sectional view in which a semiconductor chip is positioned and arranged on one main surface of a substrate and pressed, and (b) is a cross-sectional view of a semiconductor package manufactured by filling and curing a resin in a pressed state.

FIG. 5 shows an example of a configuration of a main part of a semiconductor module in another manufacturing process of the semiconductor package according to the present invention.
(a) is a cross-sectional view of a state where a semiconductor chip is positioned and arranged on one main surface of a substrate and is pressed, (b) is a cross-sectional view of a state where a resin is filled under a pressed state, and (c) is a manufactured semiconductor package. FIG.

FIG. 6 is a plan view perspectively showing a configuration example of a semiconductor package according to the present invention.

FIG. 7 is a cross-sectional view showing a main part configuration of a conventional semiconductor package.

[Explanation of symbols]

1,8 ... IC chip 2,7 ... Resin circuit board
3, 10 ... through hole 4, 9 ... flat external connection terminal 5 ... mold resin layer 6 ... bonding wire 7a ... connection part (connection pad) 8a ... electrode terminal 8b ... connection pump 11 ... sealing resin layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 23/12

Claims (7)

(57) [Claims] A substrate provided with a wiring circuit including a connection portion on one main surface; a semiconductor chip mounted face-down type with an electrode terminal portion corresponding to the connection portion on one main surface of the substrate;
A sealing resin layer filling the lower surface of the semiconductor chip and one main surface of the substrate, and electrically connected to the semiconductor chip;
And an external connection terminal led out and exposed on the other main surface side of the substrate, wherein a connection portion of the substrate and an electrode terminal portion of the corresponding semiconductor chip are connected by solid phase diffusion connection. Semiconductor device. 2. The semiconductor device according to claim 1, wherein said electrode terminal portion has a bump made of gold. 3. The semiconductor device according to claim 1, wherein said external connection terminal is of a planar type. 4. A wiring circuit including a connection portion on one main surface,
An electrode terminal portion of a semiconductor chip corresponding to the connection portion on the one main surface of the substrate on which the external connection terminals are led out and exposed to the other main surface, and positioning and arranging the semiconductor chip; Connecting the connected substrate surface and the connected portions of the semiconductor chip by solid-phase diffusion to assemble, and filling the gap formed by the upper surface of the substrate of the assembled module body and the lower surface of the semiconductor chip with a sealing resin And a step of curing the filled resin. 5. A wiring circuit including a connection portion on one main surface,
Heating, to a predetermined temperature, at least one of a connection portion on the one main surface of the substrate on which the external connection terminals are led out and exposed on the other main surface and a bump provided on an electrode terminal portion of the semiconductor chip to be mounted and mounted. And a step of aligning and arranging the semiconductor chip with the bumps provided on the electrode terminals of the semiconductor chip corresponding to the connection portion on one main surface of the substrate; and A step of applying a load to the semiconductor chip to perform solid-phase diffusion bonding of the connected parts; and a step of filling a gap formed by an upper surface of the substrate and a lower surface of the semiconductor chip in which the connected parts are diffused and bonded with sealing resin. Curing the filled resin. A method for manufacturing a semiconductor device, comprising: 6. A connecting portion made of gold on one main surface of a substrate provided with a wiring circuit including a connecting portion made of gold on one main surface, and having external connection terminals led out and exposed on another main surface, and a semiconductor chip. Heating at least one of the gold bumps provided on the electrode terminal portion of the substrate to a predetermined temperature; and connecting the gold bump provided on the electrode terminal portion of the semiconductor chip to the connection portion made of gold on one main surface of the substrate. Corresponding bumps, a step of aligning and arranging the semiconductor chip, and a step of applying a load to the substrate and the semiconductor chip arranged and correspondingly aligning and aligning the solid portions of the gold and gold connected parts, A step of filling a gap formed by an upper surface of a substrate and a lower surface of a semiconductor chip in which the connected parts are diffused and joined together with a sealing resin, and a step of curing the filled resin. Of semiconductor devices Production method. 7. The terminal said external connection, a method of manufacturing a semiconductor device according to any one of claims 4 to 6, characterized in that a flat.