JP2008021710A - Semiconductor module, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor module in which passive components can be mounted with excellent reliability and space saving on an interposer and miniaturization of the semiconductor module can be achieved, and to provide a manufacturing method thereof. <P>SOLUTION: In the semiconductor module 1 in which an IC chip 12 is mounted on the interposer 10, the IC chip 12 has IC chip side connection pads 18 formed on a rear surface 12b and an inter-pad wiring 17, the interposer 10 has bonding pads 21 formed on its main surface 10a, the passive components 14' are mounted on the IC chip side connection pads 18 of the rear surface 12b of the IC chip 12, and the IC chip side connection pads 18 of the IC chip 12 are electrically connected to the bonding pads 21 of the interposer 10 via the bonding wires 25. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor module and a manufacturing method thereof.

  A conventional semiconductor module has a configuration in which passive components such as an IC chip (IC chip), a resistor, a capacitor, and a coil are planarly arranged on an interposer. In addition, the IC chip is miniaturized by forming a plurality of IC chips in a laminated structure. As an electrical connection method between the IC chip and the interposer, wire bonding or through electrodes can be used. It was a commonly used method.

Patent Document 1 discloses a method in which a passive component having a bare chip semiconductor and a bonding-compatible electrode is mounted on a module base material and connected to a mother board by bumps provided on the electrodes of these chips.

  Patent Document 2 discloses a configuration in which each IC chip can be bonded to a carrier with each connection pad by providing solder bumps on the carrier.

Patent Document 3 discloses that electrical connection between a semiconductor device and a wiring board on which the semiconductor device is mounted is performed by a through electrode formed on the wiring board.
Japanese Patent Laid-Open No. 11-220089 Japanese Patent Laid-Open No. 5-206379 JP 2002-359341 A

However, the above-described conventional technology has the following problems.
In recent years, along with the high integration of IC chips and passive components, external connection terminals such as IC chips tend to be narrowed and narrowed, and accordingly, the wiring pattern formed on the interposer is also narrowed. There is a tendency. In such a configuration, it is difficult to reduce the size of the semiconductor module, and there is also a problem of quality reliability because there is a possibility of short circuit between wirings.

  For the purpose of high-density mounting of IC chips, a system in package (SiP) in which a plurality of IC chips are three-dimensionally housed in one IC package has been put into practical use. This SIP technology is rapidly spreading mainly in mobile products such as mobile phones and digital cameras that require ultra-miniaturization. By enabling mixed mounting of different types of chips and mounting of large-capacity memory, etc. The device can be reduced in size and weight.

Recently, a form in which a plurality of passive components are mounted on an IC chip by applying SIP technology has begun to be proposed. In this configuration, the electrode of the mounted passive component and the electrode of the interposer are connected by wire bonding. However, since the bonding wire is directly arranged on the electrode provided on the upper part of the passive component, the thickness of the semiconductor module is increased by the loop height of the bonding wire. Also, when the profile of the bonding wire is lowered, that is, when the height of the wire loop is to be kept low, the bonding wire may contact the end of the IC chip to cause a short circuit or the bonding wire may be broken. there were.
For this reason, it has been a challenge to reduce the thickness (downsize) of the semiconductor module while ensuring the reliability of quality.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor capable of mounting passive components with excellent reliability, saving space on an interposer and reducing the size of a semiconductor module. It is to provide a module and a manufacturing method thereof.

  In order to solve the above problems, the semiconductor module of the present invention is a semiconductor module in which an IC chip mounted with an active surface facing the interposer is mounted on an interposer. The interposer has a conductive connection part formed on the front surface side, and a passive component is mounted on the connection pad on the back surface of the IC chip. The connection pad and the conductive connection portion of the interposer are electrically connected by a bonding wire.

According to such a structure, electrical conduction between the IC chip and the interposer is performed by wire bonding between the connection pad and the conductive connection portion. By connecting from the connection pad instead of from the electrode of the passive component, the entire semiconductor module can be made thinner as compared with the conventional configuration in which the bonding wire protrudes from the passive component. Further, the loop height of the bonding wire is lower in the embodiment of the present invention in which the bonding wire is bonded to the connection pad formed on the back surface of the IC chip than in the conventional embodiment in which the bonding wire is directly bonded to the electrode of the passive component. Therefore, the semiconductor module can be further reduced in thickness. In addition, since the passive component is mounted on the IC chip, it is possible to reduce the size of the semiconductor module to save space on the interposer and to reduce the wiring around the interposer. be able to.
From the above, since the degree of freedom in the wiring design of the interposer is increased, it is possible to improve the design compatibility.

  Further, since the IC chip and the interposer are connected by wire bonding, they can be electrically connected without using a through electrode. Therefore, it is not necessary to form a hole for the through electrode in the IC chip, and the number of work steps can be reduced and the cost can be reduced.

Further, it is also preferable that a wiring electrically connected to the connection pad is provided on the back surface of the IC chip, and the wiring is made of one or more materials of gold, silver, copper, and nickel.
By using these materials, it is possible to form wiring that is inexpensive and excellent in connection reliability.

It is also preferable that an insulating layer be formed on the surface of the wiring.
According to such a structure, a short circuit between wirings can be prevented by forming an insulating layer on the surface of the wiring.

In addition, an electrode terminal is provided on the active surface of the IC chip, the electrode terminal is constituted by a gold bump or a solder bump, and the electrode terminal is connected to the IC chip connection electrode on the interposer side. It is also preferable to flip-chip mount the IC chip.
According to such a structure, the flip chip mounting technique can reduce the size and facilitate the mounting. Further, since the bare chip (IC chip) is mounted as it is, it can be produced in a short time and can be excellent in the ability to cope with low cost.

Moreover, it is also preferable that the IC chip and the interposer are bonded by a first bonding material made of any one of an anisotropic conductive film, an anisotropic conductive paste, and a non-conductive paste.
According to such a structure, since the IC chip is flip-chip mounted on the interposer, the IC chip is placed on the interposer via the first bonding material made of these resin-based bonding materials (ACF, ACP, NCP). Closely fixed. Therefore, the bonding strength of the IC chip to the interposer can be improved. ACF and ACP containing conductive particles are thermocompression bonded at the time of flip-chip mounting, so that conductivity is exhibited in the direction of connection at the crimped portion, that is, the connecting portion between the IC chip and the interposer. An electric anisotropy of insulating property is exhibited with respect to a direction perpendicular to the direction. Electrical anisotropy is made possible by the presence of at least one conductive particle between the electrode terminals of the IC chip and the interposer. From these things, not only can the electrode terminals of the IC chip and the interposer facing each other be electrically connected, but also the connection portion can be mechanically fixed. On the other hand, since NCP is non-conductive, insulation protection between the electrode of the interposer that should not be connected and the electrode terminal of the IC chip can be achieved.

It is also preferable that a first bonding material made of an underfill material is filled between the IC chip and the interposer.
According to such a structure, by using the first bonding material made of the underfill material for bonding the IC chip and the interposer, the stress generated by the difference in thermal expansion coefficient generated between the IC chip and the interposer is absorbed. be able to. Thereby, the connection reliability with respect to thermal stress such as a heat cycle can be improved, and the connection reliability with respect to physical stress such as impact or bending can be improved.

Moreover, it is also preferable that a passive component is joined via the 2nd joining material supplied on a connection pad.
According to such a structure, since the passive components are mounted on the connection pads via the second bonding material, these passive components are firmly fixed on the connection pads. Therefore, the bonding strength of the passive component to the IC chip can be improved.

The second bonding material is also preferably made of lead-free solder or conductive resin.
According to such a structure, by using the second bonding material made of lead-free solder or conductive resin, the passive component can be satisfactorily bonded onto the connection pad, and electrical conduction with the connection pad is obtained. be able to. If lead-free solder is used, the environment can be considered.

In addition, the connection pad is preferably formed from gold or aluminum.
According to such a structure, at the time of wire bonding, the bonding reliability with a general bonding wire made of Au (Al) is good, and processing is also easy.

Moreover, it is preferable that the surface of the electrode of the passive component is gold-plated.
According to such a configuration, since the surface of the passive component is gold-plated, the bonding of wire bonding made of gold or aluminum can be improved. Thereby, stable electrical connection can be ensured.

Moreover, it is also preferable that the IC chip and the passive component are sealed with a molding material.
According to such a structure, since the IC chip and the passive component are packaged by sealing with a molding material, mechanical or chemical protection for the IC chip and the passive component is obtained, and handling is also easy. It becomes.

According to the method for manufacturing a semiconductor module of the present invention, in a method for manufacturing a semiconductor module in which an IC chip is mounted on an interposer, a step of forming connection pads on the back side of the IC wafer, and dicing the IC wafer A step of forming a plurality of IC chips, a step of mounting an IC chip on the interposer sheet, a step of mounting passive components on the connection pads of the IC chip, and a conductive connection between the connection pads of the IC chip and the interposer sheet And a step of sealing the IC chip and the passive component with a molding material, and a step of dicing the interposer sheet to form a plurality of interposers. .
According to such a manufacturing method, the semiconductor module can be reduced in size by forming the IC chip and the passive component in a laminated structure.

Further, in the step of forming the connection pad on the back side of the IC wafer, wiring is formed simultaneously with the connection pad, and the connection pad and the wiring are any one of a plating method, a printing method, an inkjet method, a sputtering method, and a dispensing method. It is also preferable to form them.
According to such a manufacturing method, the wiring and the connection pad portion can be formed at the same time by forming the wiring and the connection pad portion arranged on the back side of the IC chip in the wafer state. Reduced production efficiency. In addition, since the wiring is formed by using any one of a plating method, a printing method, an ink jet method, a sputtering method, and a dispensing method, it can be appropriately set based on conditions such as a wiring material.

In the process of mounting the passive component on the connection pad of the IC chip, the passive component may be bonded to the connection pad by the second bonding material supplied onto the connection pad by any one of the printing method, the dispensing method, and the ink jet method. preferable.
According to such a manufacturing method, the supply method can be set according to the material of the second bonding material. Further, by mounting the passive component on the connection pad via the second bonding material, the passive component and the connection pad can be reliably bonded.

It is also preferable to use lead-free solder or conductive resin as the second bonding material and to bond the passive component to the connection pad by heating.
According to such a manufacturing method, the electrical conduction between the passive component and the connection pad can be obtained, and the passive component can be satisfactorily fixed on the connection pad.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the film thicknesses and dimensional ratios of the respective components are appropriately changed in order to make the drawings easy to see.
FIG. 1 is a perspective view showing a configuration of a semiconductor module in the present embodiment, and FIG. 2 is a side sectional view showing a schematic configuration of the semiconductor module. FIG. 3 is an enlarged plan view showing an aspect of wire bonding.

  As shown in FIG. 1, the semiconductor module 1 of the present embodiment embeds an interposer 10, an IC chip 12, a plurality of passive components 14 and 14 ′, and further the IC chip 12 and the passive components 14 and 14 ′. In this manner, a system in package (SiP) structure including the molding material 16 formed on the entire main surface 10a of the interposer 10 is formed. The passive component 14 ′ mounted on the IC chip 12 is electrically connected to the interposer 10 by a wire bonding method.

  The interposer 10 has a rectangular shape in plan view, and an IC chip 12 is mounted in the approximate center of the main surface 10a with the active surface 12a facing the main surface 10a. The IC chip 12 has a rectangular shape in plan view having a long side shorter than the long side of the interposer 10, and is mounted in a direction in which the long side is along the long side of the interposer 10. As described above, the IC chip 12 is flip-chip mounted with its active surface 12a opposed to the main surface 10a of the interposer 10, and the interfacing material 15 interposed between the active surface 12a and the main surface 10a is used for the interfacing. It is fixed on the positioner 10.

  In addition to the IC chip 12, a plurality of passive components 14 are mounted on the main surface 10 a of the interposer 10. These passive components 14 are arranged on the periphery of the IC chip 12 and are arranged along each side of the interposer 10. Further, an oscillation element 24 such as a crystal resonator is mounted at a position where it does not interfere with the IC chip 12 and the passive component 14. By forming an oscillation circuit using such an oscillation element 24, the oscillation operation of the semiconductor module 1 is stabilized.

  A plurality of passive components 14 ′ are mounted on the back surface 12 b of the IC chip 12. The passive component 14 ′ mounted on the IC chip 12 is arranged along the two long sides of the IC chip 12 and is configured to be electrically connected to the interposer 10 side via the bonding wires 25. .

  Here, the passive components 14 and 14 'are, for example, resistors such as pull-down resistors and pull-up resistors, capacitors such as coupling capacitors, coils, and inductors. These passive components 14 and 14' are shown in FIG. Thus, it has a pair of electrodes 14a, 14a. In particular, the surface of each electrode 14a in the passive component 14 'is plated with Au, thereby improving the bondability with a bonding wire 25 described later.

Next, the configuration of the semiconductor module will be described in more detail with reference to FIGS.
The interposer 10 is a wiring board mainly composed of a general-purpose resin such as an epoxy resin (glass / epoxy resin) containing glass fiber, and functions as a relay board when mounted on a motherboard of various electronic devices. To do.

  As shown in FIG. 2, on the back surface 10b side of the interposer 10, a predetermined interposer side connection pad portion 19 on the main surface 10a side described later and an electrode portion 27 connected to the bonding pad 21 are formed. A plurality of electrode terminals 26 configured by connecting bump balls or the like are provided on each electrode portion 27. The electrode terminal 26 of the interposer 10 functions as an external connection terminal of the semiconductor module 1.

  On the main surface 10a (upper surface) of the interposer 10, wiring (not shown) and an IC chip connection electrode 22 are formed. Further, the interposer-side connection pad portion 19 (connection pad) for mounting the passive component 14 is electrically connected to the IC chip 12 by wire bonding so as to avoid the IC chip connection electrode 22. Bonding pads 21 (conductive connection portions) are formed.

  As shown in FIG. 1, the interposer-side connection pad portions 19 are arranged on the periphery of the main surface 10a according to the number of passive components 14 to be mounted. The interposer-side connection pad portion 19 is constituted by a pair of electrode pads 19a, 19a formed in a rectangular shape in plan view from Al (aluminum), Au (gold), or the like. And each electrode pad 19a, 19a is arrange | positioned at predetermined intervals mutually in the state in which the arrangement direction was along each side of the interposer 10. FIG. About the constituent material of this interposer side connection pad part 19, it can change suitably according to the electrical property and physical characteristic which are required for the interposer side connection pad part 19. FIG. Further, it can be appropriately changed depending on the material of the bonding wire 25.

  The passive component 14 is mounted on such an interposer-side connection pad portion 19. At this time, the passive component 14 has its electrodes 14 a and 14 a connected to the pair of electrode pads 19 a and 19 a, respectively. Arranged in different directions. For this reason, the arrangement interval of the electrode pads 19a, 19a is appropriately set according to the position of the electrodes 14a, 14a of the passive component 14.

  As shown in FIG. 2, the passive component 14 is mounted via an adhesive 5 (second bonding material) supplied onto the interposer-side connection pad portion 19. As the adhesive 5, lead-free solder, conductive resin, or the like is used, and is supplied onto the interposer-side connection pad portion 19 by any one of a printing method, a dispensing (quantitative discharge), and an inkjet method. By using such a material, the electrodes 14 a and 14 a of the passive component 14 are electrically connected to the electrode pads 19 a and 19 a of the interposer-side connection pad 19, respectively, and are connected to the interposer 10. The passive component 14 is mechanically fixed. The adhesive 5 is preferably lead-free solder from the viewpoint of environmental considerations.

  As shown in FIGS. 1 and 2, the bonding pad 21 is formed of Al or Au, for example, in a rectangular shape in plan view, and extends along the two long sides of the main surface 10 a of the interposer 10 and at least the interposer-side connection pad portion. It is arranged on the inner side (near the IC chip 12) than 19. The bonding pad 21 in this embodiment is preferably made of the same material as the bonding wire 25 described later.

The interposer 10 is provided with an insulating layer 2 that covers the entire main surface 10a so as to expose the IC chip connection electrode 22, the interposer side connection pad portion 19, and the bonding pad 21. The insulating layer 2 in the present embodiment is formed with a thickness of about 0.1 μm to 1.0 μm by SiO 2 or the like.
The IC chip 12 is mounted on the main surface 10a of the interposer 10 having such a configuration.

  As shown in FIGS. 1 and 2, the IC chip 12 has a predetermined thickness made of silicon and is formed in a rectangular shape in plan view, and is integrated on the active surface 12a side with transistors, a memory unit, and other electronic components. A circuit (not shown) is formed. A plurality of electrode terminals 13 are formed on the active surface 12a. The electrode terminal 13 is configured by forming gold bumps, solder bumps, or the like at predetermined positions on an electrode (not shown) formed on the active surface 12a, and has a circular shape or a square shape in a sectional view. An integrated circuit is not formed below these electrode terminals 13.

  On the other hand, on the surface (back surface 12b) opposite to the active surface 12a of the IC chip 12, a plurality of IC chip side connection pad portions 18 (connection pads) and inter-pad wirings 17 are formed on the periphery. Yes. The IC chip side connection pad portion 18 has the same configuration as the interposer side connection pad portion 19 described above. The inter-pad wiring 17 is formed so as to connect any one of the plurality of IC chip side connection pad portions 18.

  The IC chip side connection pad portion 18 has a pair of electrode pads 18a, 18a formed in a rectangular shape in plan view from Al (aluminum), Au (gold), etc., and the arrangement direction of the electrode pads 18a, 18a Are arranged along the two long sides of the back surface 12b. The constituent material of the IC chip side connection pad portion 18 can be appropriately changed according to the electrical characteristics and physical characteristics required for the IC chip side connection pad portion 18, and the bonding wires 25 described later can be used. It can be changed as appropriate depending on the material.

  The passive component 14 ′ is mounted on the IC chip side connection pad portion 18 through the adhesive 5 supplied onto the IC chip side connection pad portion 18. At this time, as shown in FIG. 3, the electrodes 14 a and 14 a of the passive component 14 ′ are arranged so as to be connected to the electrode pads 18 a and 18 a of the IC chip side connection pad portion 18, respectively.

Further, as shown in FIG. 1, inter-pad wiring 17 is formed on the back surface 12 b of the IC chip 12 so as to connect the predetermined IC chip-side connection pad portions 18. The inter-pad wiring 17 is composed of any one of gold, silver, copper, nickel, or a combination of two or more, and can be any one of a plating method, a printing method, an ink jet method, a sputtering method, and a dispensing method. It is formed by. Here, for example, when the constituent material of the inter-pad wiring 17 is nickel-gold, in the present embodiment, nickel is formed with a thickness of about 5.0 μm and gold with a thickness of about 0.2 to 1.0 μm. . By using such a material, it is possible to form a wiring that is inexpensive and excellent in connection reliability.
If necessary, a resist (insulating layer) may be provided on the surface of the inter-pad wiring 17, thereby preventing current leakage and erosion due to oxygen, moisture, and the like, thereby enabling stable connection. Become.

  Such an IC chip 12 is mounted on the interposer 10 so that the electrode terminal 13 is connected to the IC chip connecting electrode 22 on the interposer 10 side. The IC chip 12 is electrically connected to the interposer 10 side by connecting the electrode terminal 13 formed on the active surface 12a side and the IC chip connecting electrode 22 on the interposer 10 side. The IC chip 12 is fixed to the interposer 10 via a bonding material 15 (first bonding material) filled in a gap between the active surface 12a of the IC chip 12 and the main surface 10a of the interposer 10. It has become.

  The bonding material 15 includes an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP) and a non-conductive paste (NCP), and an underfill material. Either of these is used.

  Here, when ACF or ACP is used, the conductive particles contained therein are conductive in the connection direction at the connection portion between the electrode terminal 13 of the IC chip 12 and the IC chip connection electrode 22 of the interposer 10. On the other hand, an electric anisotropy of insulation is exhibited in the direction orthogonal to the connecting portion. Electrical anisotropy is made possible by the presence of at least one conductive particle between the electrode terminal 13 of the IC chip 12 and the IC chip connection electrode 22 of the interposer 10. Therefore, not only the electrode terminals 13 and the IC chip connection electrodes 22 that face each other are electrically connected to each other, but also the connection portion is mechanically fixed.

  When NCP and an underfill material are used as the bonding material 15, the IC chip 12 and the interposer 10 can be fixed while maintaining the connection between the electrode terminal 13 and the IC chip connection electrode 22. Further, since the NCP and the underfill material are non-conductive, it is possible to achieve insulation protection between the electrode on the interposer 10 side and the electrode on the IC chip 12 side that should not be connected.

  In this way, the IC chip 12 is flip-chip mounted on the interposer 10, whereby the active surface 12a of the IC chip 12 is electrically connected to the interposer 10 side.

  As shown in FIGS. 2 and 3, the back surface 12 b of the IC chip 12 and the interposer 10 are electrically connected by a bonding wire 25 that connects the IC chip side connection pad portion 18 and the bonding pad 21. As the bonding wire 25, a metal material such as Al (aluminum) or Au (gold), for example, having a thickness of about 5.0 μm is used. Al and Au have very small electrical resistance and are easy to process. Further, since the surfaces of the electrodes 14a and 14a of the passive component 14 'are gold-plated, the bondability between the electrodes 14a and 14a and the bonding wire 25 made of the above material is good. Furthermore, since the bonding pad 21 is also formed of the same material as that of the bonding wire 25 (Al, Au, or the like), the bondability between the bonding pad 21 and the bonding wire 25 is good. Thereby, a stable connection can be ensured.

  As described above, the bonding property of the bonding wire 25 to the IC chip side connection pad portion 18 and the bonding pad 21 is good by configuring the IC chip side connection pad portion 18 and the bonding pad 21 with the same material as the bonding wire 25. It will be a thing. Thereby, the connection reliability of wire bonding can be improved.

  The molding material 16 is formed on the main surface 10 a of the interposer 10 so as to embed all of the IC chip 12, the passive components 14, 14 ′, and the oscillation element 24. As the molding material 16, a material made of a thermosetting epoxy resin in which silica having a predetermined particle diameter is dispersed is used. Thus, by sealing the IC chip 12, the passive components 14, 14 ′, and the oscillation element 24 with the molding material 16, mechanical or chemical with respect to the IC chip 12, the passive components 14, 14 ′, and the oscillation element 24. Protection can be obtained.

  The semiconductor module 1 having such a configuration is mounted on the motherboard of various electronic devices via the electrode terminals 26 connected to the interposer 10.

  In the IC chip connection electrode 22 and the electrode portion 27, part of the rearrangement wiring routed from the electrode elements formed in the peripheral portions of the main surface 10a and the back surface 10b functions as electrodes. In the present embodiment, descriptions of the electrode elements and the rearrangement wiring are omitted, but this is a conventionally known configuration.

Next, the manufacturing method of the semiconductor module of this embodiment is demonstrated.
FIG. 4 is a perspective view showing a silicon IC wafer that is a base (substrate body) of an IC chip and a wiring board that is a base of an interposer. 5 and 6 are process diagrams showing the manufacturing procedure of the semiconductor module in the present embodiment.
In order to manufacture the semiconductor module 1, first, the IC chip 12 must be manufactured. Therefore, first, a method for manufacturing the IC chip 12 will be described with reference to FIG. 4, and FIG.

  The IC chip 12 uses a W-CSP (Wafer Level Chip Scale Package) technique in which wiring, IC chip side connection pad portions 18, bumps and the like are formed in a wafer state and then separated into individual IC chips. Formed using.

  In manufacturing the IC chip 12, first, a silicon IC wafer 4 made of single crystal silicon as shown in FIG. 4 is prepared. Then, an integrated circuit and an electrode are formed on the main surface 4a (corresponding to the active surface 12a of the IC chip 12), and then a passivation film is formed over the silicon IC wafer 4 so as to cover the integrated circuit and the electrode. . This silicon IC wafer 4 has a plurality of IC chip forming regions 3 partitioned by dicing lines L. A predetermined number of electrode terminals 13 (see FIG. 2) exist for each IC chip formation region 3 on the back surface 4b. In FIG. 4, the illustration of the integrated circuit, the electrodes, and the passivation film is omitted.

  Then, as shown in FIGS. 2 and 4, the electrode terminals 13 are formed on the electrodes (not shown) located in the periphery of each IC chip formation region 3 on the main surface 4a by using a known method such as gold bumps or solder bumps. Batch formation to a predetermined height. Further, the height is set as appropriate, but all bumps are formed in a predetermined pattern with a uniform height.

  Next, on the back surface 4b (corresponding to the back surface 12b of the IC chip 12) side of the silicon IC wafer 4, the inter-pad wiring 17 and the IC chip side connection pad portion 18 are formed for each IC chip forming region 3, and as necessary. A resist is formed on the inter-pad wiring 17. Then, the adhesive 5 is supplied to a predetermined location on the IC chip side connection pad portion 18 to mount and fix the passive component 14. Thereafter, by dicing (cutting) the silicon IC wafer 4 along the dicing line L, a plurality of IC chips 12 as shown in FIG. 2 are formed. In this way, the IC chip 12 is prepared.

  Next, in order to manufacture the semiconductor module 1, the above-described IC chip 12 and the plurality of passive components 14 and 14 ′ are aligned, and a wiring board capable of taking a plurality of interposers 10 as shown in FIG. 4. Prepare 30 (interposer sheet).

  The wiring board 30 has a plurality of interposer regions 31 partitioned by dicing lines L. A predetermined number of bonding pads and interposer-side connection pads are provided on the main surface 30a for each interposer region 31. The part is formed. On the other hand, it is assumed that electrode terminals are already formed on the back surface 30b. In FIG. 4, illustration of electrode terminals, bonding pads, and interposer-side connection pads is omitted.

  In the following description, in order to make the description of the manufacturing process of the semiconductor module 1 easier to understand, referring to FIGS. 5 and 6 together with FIG. 4, focusing on the configuration in one interposer region 31 on the wiring substrate 30 will be described. I will decide. Here, the process diagrams shown in FIGS. 5 and 6 are illustrated with a focus on the configuration of one interposer region 31 on the wiring board 30.

  First, as shown in FIG. 4 and FIG. 5A, the IC chip 12 is mounted in a predetermined position of each interposer region 31 on the main surface 30a of the wiring board 30 by the flip chip method, and the electrode terminals 13 of the IC chip 12 are mounted. And the IC chip connecting electrode 22 of the wiring board 30 are connected. Thereafter, as shown in FIG. 5B, in the present embodiment, the bonding material 15 made of an underfill resin (underfill material) is filled in the gap between the IC chip 12 and the wiring board 30. Subsequently, by heating and curing, the electrode terminal 13 on the IC chip 12 side and the IC chip connection electrode 22 on the wiring board 30 side are joined to obtain conduction. By using an underfill resin as the bonding material 15, connection reliability is maintained against thermal stress and physical stress. Further, since it can be cured at a low temperature and in a short time, the influence on other electronic components can be kept low.

In addition, the electrode terminal 13 and the IC chip connection electrode 22 are connected by previously applying a bonding material made of an anisotropic conductive resin or a non-conductive resin on the wiring board 30 and heating the bonding material. Alternatively, it can be achieved by melting. At this time, by applying heat and pressure and ultrasonic vibration, the bonding material on which the electrode terminal 13 of the IC chip 12 is on the predetermined IC chip connection electrode 22 on the wiring board 30 side is eliminated, and the IC chip 12 side The electrode terminal 13 is joined or brought into contact with the IC chip connecting electrode 22 on the wiring board 30 side, whereby conduction is obtained.
In this case, the step of filling the bonding material 15 with the underfill resin is not necessary.

  Next, as shown in FIG. 5C, the adhesive 5 is supplied onto the IC chip side connection pad portion 18 of the IC chip 12 and the interposer side connection pad portion 19 of the wiring substrate 30. As a method for supplying the adhesive 5, it is assumed that the adhesive 5 is supplied onto the IC chip side connection pad portion 18 and the interposer side connection pad portion 19 by any one of the printing method, the dispensing (quantitative discharge) and the ink jet method. Then, by mounting and fixing the passive components 14 and 14 ′ on the adhesive 5, the passive component 14 ′ and the IC chip side connection pad portion 18, the passive component 14 and the interposer side connection pad portion 19 are bonded to each other. 5 to be electrically connected.

  For mounting the passive components 14 and 14 ′, an existing SMT (Surface Mounting Technology) mounter or die bonder can be used.

  Thereafter, as shown in FIG. 6A, the IC chip side connection pad portion 18 of the IC chip 12 and the bonding pad 21 of the wiring substrate 30 are connected by the bonding wire 25. Bonding of the bonding wire 25 is performed using, for example, a wire bonder that uses both ultrasonic vibration and thermocompression bonding.

  Further, the connection between the IC chip side connection pad portion 18 and the bonding pad 21 on the wiring substrate 30 can be performed before the passive component 14 ′ is mounted on the IC chip 12.

  Further, plasma processing may be performed before the bonding wire 25 is formed. As a result, the IC chip side connection pad portion 18 of the IC chip 12 and the bonding pad 21 of the wiring substrate 30 are cleaned. Although not shown here, the passive component 14 ′ and another passive component 14 ′ may be connected via the bonding wire 25.

  Next, the wiring board 30 is mounted on a mold die (not shown), and the IC chip 12 and the passive components 14 and 14 'are embedded as shown in FIG. The surface 30 a is sealed with the molding material 16. The method of injecting the molding material 16 into the mold is generally a transfer mold method in which the molding material 16 is poured while being melted from a passage called a side gate. By using such a method, the IC chip 12 and the passive components 14 and 14 are used. 'Is sealed with a molding material 16 and packaged. As the molding material 16, a material made of a thermosetting epoxy resin in which silica having a predetermined particle diameter is dispersed is used.

  The molding material 16 may be formed by a method other than the above-described mold mold, such as film formation by spin coating or affixing a dry film or the like.

  Thereafter, the wiring board 30 is diced along the dicing line L. Specifically, cutting is performed using a diamond blade 40, and a plurality of semiconductor modules 1 as shown in FIGS. 1 and 2 are obtained by dicing the wiring board 30 into pieces.

  Note that sealing with the molding material 16 may be performed after the wiring substrate 30 is diced.

  In this way, the active surface 12a of the IC chip 12 and the interposer are configured by mounting the passive component 14 'by providing the IC chip side connection pad portion 18 and the inter-pad wiring 17 on the back surface 12b side of the IC chip 12. 10 is performed by joining the electrode terminal 13 and the IC chip connecting electrode 22 by a flip-chip method. Therefore, the connection by wire bonding is only conduction between the passive component 14 ′ and the interposer 10, so there is no need to route a large number of bonding wires 25, and the configuration on the substrate can be simplified. Therefore, since the degree of freedom in wiring design of the interposer 10 is increased, the design compatibility can be improved.

  By adopting such a flip-chip mounting technique, it is possible to produce in a short time and to have excellent ability to cope with low cost.

  Further, by performing wire bonding from the IC chip side connection pad portion 18 to the bonding pad 21 instead of from the electrodes 14a and 14a of the passive component 14 ', the connection distance to the interposer 10 can be shortened. Therefore, the length of the bonding wire 25 can be shortened. As a result, resistance between the connections can be suppressed, and signal deterioration can be reduced. Therefore, the quality of the semiconductor module 1 can be ensured.

  Furthermore, since the loop of the bonding wire 25 can be prevented from projecting from the passive component 14 ′, the semiconductor module 1 can be thinned and the bonding wire 25 can be reduced in profile. As a result, the resistance between the IC chip side connection pad portion 18 and the bonding pad 21 can be reduced, or signal deterioration can be prevented. As a result, the performance of the semiconductor module 1 can be maintained satisfactorily.

  Further, since the passive component 14 ′ is mounted on the IC chip 12, the narrow pitch due to the high integration of the mounting components on the interposer 10 is eliminated. Therefore, it is possible to reduce the size of the semiconductor module 1.

  Further, by using the bonding material 15 made of an underfill material for bonding the IC chip 12 and the interposer 10, it is possible to absorb the stress caused by the difference in thermal expansion coefficient generated between the IC chip 12 and the interposer 10. . Thereby, the connection reliability with respect to thermal stress such as a heat cycle can be improved, and the connection reliability with respect to physical stress such as impact or bending can be improved.

  Further, since the IC chip 12 and the interposer 10 are connected by wire bonding, they can be electrically connected without using a through electrode. Therefore, it is not necessary to form a hole for the through electrode in the IC chip 12, and the number of work steps can be reduced and the cost can be reduced.

  The passive component 14 may be arranged at any position on the interposer 10 as long as it does not hinder the operation and electrical connection of the IC chip 12. In addition, as shown in FIG. 7, the adhesive layer 50 may be formed in advance on the bottom surface of the passive component 14. In this case, the adhesive layer 50 is formed on the entire bottom surface of the passive component 14. The adhesive layer 50 is formed by applying a conductive adhesive on the back surface of the assembly of the plurality of passive components 14 or pasting a film-like adhesive tape or the like before the passive components 14 are separated into individual pieces. A plurality of passive components 14 having an adhesive layer 50 are obtained by dicing them. Thereby, a manufacturing process can be simplified. Further, since the adhesive layer 50 is formed to be approximately the same size as the passive component 14, the workability is improved because the adhesive layer 50 is not provided on the IC chip 12 except for the region where the passive component 14 is mounted. good. The adhesive layer 50 can also be applied to the passive component 14 '.

It is a perspective view which shows schematic structure of the semiconductor module which concerns on this embodiment. It is A-A 'sectional drawing of FIG. It is an enlarged plan view which shows the principal part of the semiconductor module which concerns on this embodiment. It is a perspective view which shows the silicon IC wafer and wiring board which concern on this embodiment. It is a manufacturing process figure of the semiconductor module concerning this embodiment. It is a manufacturing process figure of the semiconductor module concerning this embodiment. It is explanatory drawing which shows the other mounting method of the passive component which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor module, 2 ... Insulating layer, 3 ... Formation area, 4 ... Silicon IC wafer, 4a ... Main surface, 4b ... Back surface, 5 ... Adhesive material (2nd joining material), L ... Dicing line, 10 ... Interposer DESCRIPTION OF SYMBOLS 10a ... Main surface, 10b ... Back surface, 12 ... Chip, 12a ... Active surface, 12b ... Back surface, 13 ... Electrode terminal, 14, 14 '... Passive component, 14a ... Electrode, 15 ... Bonding material (1st bonding material) , 16 ... Mold material, 17 ... Inter-pad wiring, 18 ... IC chip side connection pad portion, 18a ... Electrode pad, 19 ... Interposer side connection pad portion, 21 ... Bonding pad (conductive connection portion), 22 ... IC chip connection Electrode part, 24 ... oscillation element, 25 ... bonding wire, 26 ... electrode terminal, 27 ... electrode part, 30 ... wiring substrate, 30a ... main surface, 30b ... back surface, 31 ... interposer region, 4 ... diamond blade, 50 ... adhesive layer

Claims (15)

In a semiconductor module comprising an IC chip mounted on an interposer so that the active surface faces the interposer side,
The IC chip has a connection pad formed on the back side thereof,
The interposer has a conductive connection portion formed on the surface side thereof,
Passive components are mounted on the connection pads on the back surface of the IC chip,
The semiconductor module, wherein the connection pad of the IC chip and the conductive connection part of the interposer are electrically connected by a bonding wire. A wiring electrically connected to the connection pad is provided on the back surface of the IC chip,
2. The semiconductor module according to claim 1, wherein the wiring is made of one or more materials of gold, silver, copper, and nickel.    The semiconductor module according to claim 2, wherein an insulating layer is formed on a surface of the wiring.    An electrode terminal is provided on an active surface of the IC chip, the electrode terminal is constituted by a gold bump or a solder bump, and the electrode terminal is connected to the IC chip connection electrode on the interposer side. 4. The semiconductor module according to claim 1, wherein the IC chip is flip-chip mounted on an interposer.    The IC chip and the interposer are bonded by a first bonding material made of any one of an anisotropic conductive film, an anisotropic conductive paste, and a non-conductive paste. Item 5. The semiconductor module according to any one of Items 1 to 4.    5. The semiconductor module according to claim 1, wherein a first bonding material made of an underfill material is filled between the IC chip and the interposer.    The semiconductor module according to claim 1, wherein the passive component is bonded through a second bonding material supplied on the connection pad.    The semiconductor module according to claim 7, wherein the second bonding material is made of lead-free solder or conductive resin.    The semiconductor module according to claim 1, wherein the connection pad is made of gold or aluminum.     The semiconductor module according to claim 1, wherein the passive component has a surface plated with gold.    The semiconductor module according to claim 1, wherein the IC chip and the passive component are sealed with a molding material. In a method for manufacturing a semiconductor module in which an IC chip is mounted on an interposer,
Forming a connection pad on the back side of the IC wafer;
Dicing the IC wafer to form a plurality of IC chips;
Mounting the IC chip on the interposer sheet;
Mounting passive components on the connection pads of the IC chip;
Wire bonding the connection pads of the IC chip and the conductive connection portions of the interposer sheet;
Sealing the IC chip and the passive component with a molding material;
And a step of dicing the interposer sheet to form a plurality of interposers. In the step of forming connection pads on the back side of the IC wafer,
A wiring is formed simultaneously with the connection pad,
12. The method of manufacturing a semiconductor module according to claim 11, wherein the connection pad and the wiring are formed using any one of a plating method, a printing method, an ink jet method, a sputtering method, and a dispensing method. In the step of mounting passive components on the connection pads of the IC chip,
The semiconductor module according to claim 11, wherein the passive component is bonded to the connection pad by a second bonding material supplied onto the connection pad by any one of a printing method, a dispensing method, and an inkjet method. Method. 14. The method of manufacturing a semiconductor module according to claim 13, wherein lead-free solder or conductive resin is used as the second bonding material, and the passive component is bonded to the connection pad by heating.

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