JP2007150346A - Semiconductor device and method of manufacturing same, circuit board, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which forms a plurality of semiconductor chips in one package by positively performing wire bonding, its manufacturing method, a circuit board, and an electronic apparatus. <P>SOLUTION: On a substrate 70 formed with a circuit pattern 72, a first semiconductor chip 10 is mounted facing a surface having electrodes 12. On the first semiconductor chip 10, a second semiconductor chip 20 is mounted and its electrodes 22 are electrically connected with the circuit pattern 72 with wires 26. A first resin 74 provided between the substrate 70 and the first semiconductor chip 10 differs from a second resin 90 sealing the first and second semiconductor chips 10, 20. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.

  With the miniaturization of electronic devices, development of multi-chip modules in which a plurality of semiconductor chips are incorporated at high density is in progress. One form is Stacked-CSP (Chip Scale / Size Package) in which a plurality of semiconductor chips are stacked to form a single package.

For example, in a semiconductor device disclosed in Japanese Patent Laid-Open No. 9-260441, a second semiconductor chip smaller than the outer shape of the first semiconductor chip is mounted on the first semiconductor chip to form a single package. . According to this, since the first semiconductor chip located on the lower side is not stable, it may be difficult to perform wire bonding on the semiconductor chip located on the upper side.
JP-A-11-219984 Japanese Patent Laid-Open No. 05-047998 JP-A-63-084128

  The present invention solves this problem, and an object of the present invention is to provide a semiconductor device, a method of manufacturing the same, a circuit board, and an electronic apparatus in which a plurality of semiconductor chips are made into one package by reliably performing wire bonding. There is.

(1) A semiconductor device according to the present invention includes:
A first semiconductor chip mounted on a substrate on which a wiring pattern is formed with a surface having a plurality of electrodes facing each other, and the electrodes are electrically connected to the wiring pattern;
Mounted on the first semiconductor chip, a surface having a plurality of electrodes faces away from the first semiconductor chip, and the plurality of electrodes are electrically connected to the wiring pattern by wires. A second semiconductor chip;
A first resin provided between the substrate and the first semiconductor chip;
A second resin different from the first resin on the substrate and encapsulating the first and second semiconductor chips;
including.

  According to this, the physical properties of the first resin provided between the first semiconductor chip and the substrate are different from those of the second resin encapsulating the first and second semiconductor chips. According to this, the first resin and the second resin can be selected so as to have physical properties suitable for each of the member that is in close contact with the first resin and the member that is in close contact with the second resin. Therefore, for example, it is possible to sufficiently cope with vibration due to ultrasonic waves when wire bonding the second semiconductor chip by selecting the first resin. Therefore, wire bonding can be performed reliably and a semiconductor device with a high yield can be obtained.

  The first and second semiconductor chips mean any two semiconductor chips, and the present invention is not limited to two semiconductor chips, and can be applied to a plurality of semiconductor chips.

(2) In this semiconductor device,
The first resin is an anisotropic conductive material containing conductive particles,
The electrode of the first semiconductor chip may be electrically connected to the wiring pattern through the conductive particles.

  According to this, it is possible to simultaneously fix the first semiconductor chip and to electrically connect the first semiconductor chip and the wiring pattern. In addition, the anisotropic conductive material is disposed between the substrate having the wiring pattern and the first semiconductor chip, thereby providing a function of alleviating the difference in thermal stress between the first semiconductor chip and the substrate. Therefore, the reliability of the semiconductor device can be improved.

(3) In this semiconductor device,
A plurality of through holes are formed in the substrate, the wiring pattern is formed on one surface of the substrate and a part of the wiring pattern passes over the through hole,
A plurality of external terminals may be provided on the wiring pattern and projecting from the surface of the substrate opposite to the surface on the wiring pattern side through the through hole.

(4) In this semiconductor device,
You may have a some land part for providing the some external terminal electrically connected to the said wiring pattern.

(5) In this semiconductor device,
The substrate may be a glass epoxy substrate.

(6) In this semiconductor device,
The second semiconductor chip may be attached to the first semiconductor chip via an adhesive.

(7) In this semiconductor device,
The outer shape of the first semiconductor chip may be larger than that of the second semiconductor chip.

(8) In this semiconductor device,
The first resin may be provided until reaching a side surface of the first semiconductor chip.

  According to this, since the bonding area between the first semiconductor chip and the first resin is increased, the first semiconductor chip is more reliably fixed on the substrate. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip.

(9) In this semiconductor device,
The outer dimensions of the first and second semiconductor chips may be equal.

(10) In this semiconductor device,
The first resin may be provided up to at least a side surface of the first semiconductor chip among a side surface of the first semiconductor chip and a side surface of the second semiconductor chip.

  According to this, since the bonding area between the first semiconductor chip and the first resin is increased, the first semiconductor chip is more reliably fixed on the substrate. Furthermore, the first resin may be provided up to the side surface of the second semiconductor chip. In this case, even the second semiconductor chip can be fixed. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip. Therefore, even if the sizes of the first and second semiconductor chips are equal, wire bonding can be performed reliably, and a semiconductor device with a high yield can be obtained.

(11) In this semiconductor device,
The outer shape of the first semiconductor chip may be smaller than that of the second semiconductor chip.

(12) In this semiconductor device,
The first resin includes a side surface of the first semiconductor chip and a surface of the second semiconductor chip that faces the substrate and avoids facing the first semiconductor chip; May be provided.

  According to this, since the bonding area between the first semiconductor chip and the first resin is increased, the first semiconductor chip is more reliably fixed on the substrate. Further, the first resin may be provided up to a region of the second semiconductor chip on the side of the substrate that protrudes from the first semiconductor chip. In this case, even the second semiconductor chip is fixed. be able to. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip. Therefore, even if the outer shape of the first semiconductor chip is smaller than that of the second semiconductor chip, wire bonding can be performed reliably, and a semiconductor device with a high yield can be obtained.

  (13) A circuit board according to the present invention is mounted with the semiconductor device.

  (14) An electronic apparatus according to the present invention includes the semiconductor device.

(15) A method for manufacturing a semiconductor device according to the present invention includes:
Face-down bonding the first semiconductor chip to a substrate on which a wiring pattern is formed;
Mounting a second semiconductor chip on the first semiconductor chip;
Electrically connecting the second semiconductor chip and the wiring pattern with a wire;
Providing a first resin between the first semiconductor chip and the substrate;
Sealing the first and second semiconductor chips with a second resin different from the first resin;
including.

  According to this, the physical properties of the first resin provided between the first semiconductor chip and the substrate are different from those of the second resin encapsulating the first and second semiconductor chips. According to this, the first resin and the second resin can be selected so as to have physical properties suitable for each of the member that is in close contact with the first resin and the member that is in close contact with the second resin. Therefore, for example, it is possible to sufficiently cope with vibration due to ultrasonic waves when wire bonding the second semiconductor chip by selecting the first resin. Therefore, wire bonding can be performed reliably and a semiconductor device with a high yield can be manufactured.

(16) In this method of manufacturing a semiconductor device,
The first resin is an anisotropic conductive material containing conductive particles,
In the first step, the electrode of the first semiconductor chip may be electrically connected to the wiring pattern via the conductive particles.

  According to this, fixing of the first semiconductor chip and electrical connection between the first semiconductor chip and the wiring pattern can be achieved simultaneously, and the manufacturing process can be reduced.

(17) In this method of manufacturing a semiconductor device,
In the step of mounting the second semiconductor chip, the second semiconductor chip may be attached to the first semiconductor chip via an adhesive.

(18) In this method of manufacturing a semiconductor device,
The outer shape of the first semiconductor chip is larger than that of the second semiconductor chip,
At least after the step of mounting the first semiconductor chip and the step of providing the first resin,
Pressing at least one of the first semiconductor chip and the substrate toward the other;
The first resin may be provided up to the side surface of the first semiconductor chip.

  According to this, in addition to the mounting region of the first semiconductor chip on the substrate, the first resin is provided so as to protrude from the outer periphery and the side surface of the first semiconductor chip. As a result, the bonding area between the first semiconductor chip and the first resin is increased, so that the first semiconductor chip is more reliably fixed on the substrate. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip.

(19) In this method of manufacturing a semiconductor device,
The outer dimensions of the first and second semiconductor chips are equal,
At least after the step of mounting the first semiconductor chip and the step of providing the first resin,
Pressing at least one of the first semiconductor chip and the substrate toward the other;
The first resin may be provided up to at least the side surface of the first semiconductor chip among the side surface of the first semiconductor chip and the side surface of the second semiconductor chip.

  According to this, in addition to the mounting region of the first semiconductor chip on the substrate, the first resin is provided so as to protrude from the outer periphery and the side surface of the first semiconductor chip. As a result, the bonding area between the first semiconductor chip and the first resin is increased, so that the first semiconductor chip is more reliably fixed on the substrate. Further, the first resin may be provided up to the side surface of the second semiconductor chip. In this case, even the second semiconductor chip can be fixed. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip. Therefore, even if the sizes of the first and second semiconductor chips are equal, wire bonding can be reliably performed, and a semiconductor device with a high yield can be manufactured.

(20) In this method of manufacturing a semiconductor device,
The outer shape of the first semiconductor chip is smaller than that of the second semiconductor chip,
At least after the step of mounting the first semiconductor chip and the step of providing the first resin,
Pressing at least one of the first semiconductor chip and the substrate toward the other;
The first resin is provided up to a side surface of the first semiconductor chip and a region of the second semiconductor chip that faces the substrate and protrudes from the first semiconductor chip. May be.

  According to this, in addition to the mounting region of the first semiconductor chip on the substrate, the first resin is provided so as to protrude from the outer periphery and the side surface of the first semiconductor chip. As a result, the bonding area between the first semiconductor chip and the first resin is increased, so that the first semiconductor chip is more reliably fixed on the substrate. Further, the first resin may be provided up to a region on the substrate side of the second semiconductor chip and protruding from the first semiconductor chip. In this case, the second semiconductor chip is also fixed. Can do. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip. Therefore, even if the outer shape of the first semiconductor chip is smaller than that of the second semiconductor chip, wire bonding can be performed reliably, and a semiconductor device with a high yield can be obtained.

(21) In this method of manufacturing a semiconductor device,
In the step of connecting with the wire, the wire may be bonded using ultrasonic waves.

(22) In this method of manufacturing a semiconductor device,
In the step of connecting with the wire, the wire and the wiring pattern may be bonded after the electrode of the second semiconductor chip and the wire are bonded.

  According to this, wire bonding can be performed on the electrodes of the second semiconductor chip without forming bumps in a separate process.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a semiconductor device according to the first embodiment of the present invention. The semiconductor device 1 includes a first semiconductor chip 10, a second semiconductor chip 20, and a substrate 70.

A plurality of electrodes 12 are formed on one surface (active surface) of the first semiconductor chip 10. When the planar shape of the semiconductor chip 10 is a rectangle (square or rectangle), the plurality of electrodes 12 are formed along at least one side (including two opposite sides or all sides). Alternatively, it may be two-dimensionally formed in a matrix shape (area shape). The electrode 12 may be provided with bumps by solder balls, gold wire balls, gold plating, or the like, and the electrode 12 itself may have a bump shape. Nickel, chromium, titanium, or the like may be added as a bump metal diffusion prevention layer between the electrode 12 and the bump. By avoiding the electrode 12, a passivation film (not shown) such as SiN, SiO ₂ , or MgO may be formed on the first semiconductor chip 10. The passivation film is an electrical insulating film. The passivation film is not essential to the present invention, but is preferably formed.

  The second semiconductor chip 20 may have the same configuration as that of the first semiconductor chip 10, but in order to form the wire 26 suitably, the electrode 22 has at least one side (including two opposite sides or all sides). It is preferable to form along. In the present embodiment, the outer shape of the second semiconductor chip 20 is smaller than that of the first semiconductor chip 10.

  The substrate 70 may be formed of any organic or inorganic material, or may be a composite structure of these. The substrate 70 may be used in individual pieces, or may be used in a strip shape in which a plurality of regions on which semiconductor chips are mounted are formed in a matrix. In the case of a strip shape, it is punched into individual pieces in a separate process. An example of the substrate 70 formed of an organic material is a flexible substrate made of polyimide resin. A tape used in the TAB technology may be used as the flexible substrate. Examples of the substrate 70 formed from an inorganic material include a ceramic substrate and a glass substrate. An example of a composite structure of organic and inorganic materials is a glass epoxy substrate. The planar shape of the substrate 70 is not limited, but is preferably similar to the first and second semiconductor chips 10 and 20. Further, as the substrate 70, a substrate having a build-up multilayer structure configured by stacking an insulating resin and a wiring pattern, or a multilayer substrate in which a plurality of substrates are stacked may be used.

  A wiring pattern 72 is formed on the substrate 70. In the present embodiment, the wiring pattern 72 is formed on one surface of the substrate, but may be formed on both surfaces. The wiring pattern 72 is often composed of a plurality of layers. For example, the wiring pattern 72 can be formed by stacking any one of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti—W). For example, the wiring pattern 72 may be formed by applying photolithography, the wiring pattern 72 may be directly formed on the substrate 70 by sputtering, or the wiring pattern 72 may be formed by plating. Further, a part of the wiring pattern 72 may be a land portion (not shown) having a larger area than a portion to be a wiring. The land portion has a function of securing a sufficient electrical connection portion. Therefore, the land portion may be formed at the connection portion with the electrode 12 or may be formed at the connection portion with the wire 26.

  The plurality of external terminals 80 are electrically connected to the wiring pattern 72. In FIG. 1, external terminals 80 are provided on the wiring pattern 72 through through holes 82 formed in the substrate 70. In this case, a land portion may be formed on the through hole 82. More specifically, the external terminal 80 is provided on a land portion exposed from the through hole 82 and protrudes from the opposite side of the surface of the substrate 70 on which the wiring pattern 72 is formed. The external terminal 80 may be formed of solder, or solder that is a material for a solder ball may be filled in the through hole 82, and a conductive member integrated with the solder ball may be formed in the through hole 82. The external terminal 80 may be formed of a metal other than the above-described solder, a conductive resin, or the like. Alternatively, the external terminal 80 may be formed by bending a part of the wiring pattern 72 inside the through hole 82. For example, a part of the wiring pattern 72 is caused to enter the inside of the through hole 82 using a mold or the like, and protrudes from the surface of the substrate 70 opposite to the surface on which the wiring pattern 72 is formed. May be used as an external terminal.

  Further, the external terminals 80 may not be positively formed, but a solder cream applied to the mother board side when the mother board is mounted may be used to form the external terminals as a result of the surface tension at the time of melting. This semiconductor device is a so-called land grid array type semiconductor device having a land portion for forming an external terminal. A part of the wiring pattern 72 may be a land part, or a land part is formed on the surface of the substrate 70 opposite to the surface on which the wiring pattern 72 is formed, and the land part is formed via the through hole 82. And the wiring pattern 72 may be electrically connected. Alternatively, the through hole 82 may be filled with a conductive material, and the surface thereof may be a land portion.

  The first semiconductor chip 10 is mounted (face-down bonding) with the surface of the electrode 12 facing the substrate 70. In face-down bonding, there are forms such as those using conductive resin paste, metal bonding using Au—Au, Au—Sn, solder, etc., and those using the contraction force of insulating resin, and any of these forms may be used. It is essential that the first resin is provided between the first semiconductor chip 10 and the substrate 70. In the present invention, when the first resin is not the anisotropic conductive material 74, the first resin is placed between the first semiconductor chip 10 and the substrate 70 after the first semiconductor chip 10 is mounted. It may be filled. In the semiconductor device 1, the first resin is the anisotropic conductive material 74. The anisotropic conductive material 74 may be provided from the outer periphery of the first semiconductor chip 10 on the substrate 70 to the side surface of the first semiconductor chip 10, but this is not essential. That is, in the present invention, the first resin may be provided only in the mounting region of the first semiconductor chip 10 on the substrate 70.

  According to the present embodiment, the anisotropic conductive material 74 is provided between the first semiconductor chip 10 and the substrate 70, and the anisotropic conductive material 74 is also provided on the outer periphery of the first semiconductor chip 10. Is provided. According to this, since the bonding area between the first semiconductor chip 10 and the anisotropic conductive material 74 is increased, the first semiconductor chip 10 is reliably fixed on the substrate regardless of the size. Accordingly, for example, it is possible to sufficiently cope with vibration due to ultrasonic waves when the second semiconductor chip 20 is wire-bonded. Therefore, the semiconductor device 1 with a high yield can be obtained without being restricted by the outer shapes of the first and second semiconductor chips 10 and 20.

  The anisotropic conductive material 74 is obtained by dispersing conductive particles (filler) in an adhesive (binder), and a dispersant may be added. As the adhesive for the anisotropic conductive material 74, a thermosetting adhesive is often used. Further, as the anisotropic conductive material 74, an anisotropic conductive film previously formed in a sheet shape is often used, but a liquid material may be used. The anisotropic conductive material 74 is crushed between the electrode 12 and the wiring pattern 72 so as to achieve electrical conduction between the two by the conductive particles.

  The second semiconductor chip 20 is mounted on the first semiconductor chip 10 with the surface of the electrode 22 facing away from the first semiconductor chip 10. In other words, the second semiconductor chip 20 is face-up bonded to the first semiconductor chip 10, and the electrode 22 and the wiring pattern 72 are connected by wire bonding. The wire 26 is often composed of gold, copper, aluminum, or the like, but is not particularly limited as long as it is a conductive material. The second semiconductor chip 20 may be mounted via an adhesive 76. The adhesive 76 is preferably an insulating resin. In FIG. 1, the wire 26 is drawn from the electrode 22 of the second semiconductor chip 20 and connected to the wiring pattern 72 on the outer side of the anisotropic conductive material 74 on the outer side of the first semiconductor chip 10 in a plan view on the substrate. Is done. In other words, the wire 26 is connected to the wiring pattern 72 avoiding the region of the anisotropic conductive material 74 in a plan view on the substrate 70. The shape of the wire 74 is not limited, but a shape that does not contact the end portions of the first and second semiconductor chips 10 and 20 is preferable. For example, the wire can be formed in a three-dimensional loop as shown in FIG. Bumps may be provided on the electrodes 22 of the second semiconductor chip 20, but the bumps may not be provided depending on the manufacturing process (described later). Note that the mounting portions of the first and second semiconductor chips 10 and 20 are sealed with a second resin 90 such as potted epoxy resin.

  FIG. 1 shows the FAN-IN type semiconductor device 1 in which the external terminals 80 are provided only in the mounting region of the first semiconductor chip 10, but the present invention is not limited to this. . For example, the FAN-OUT type semiconductor device in which the external terminal 80 is provided only outside the mounting region of the first semiconductor chip 10 or the FAN-IN / OUT type semiconductor device in which this is combined with the FAN-IN type. The present invention can be applied.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described.

  The first semiconductor chip 10 is mounted on the substrate 70 via the anisotropic conductive material 74. More specifically, the surface on which the electrode 12 is formed in the first semiconductor chip 10 is mounted on the substrate 70 in a region where the anisotropic conductive material 74 is provided. According to the present embodiment, the electrode 12 and the wiring pattern 72 are electrically connected by the anisotropic conductive material 74, and at the same time, the underfill of the first semiconductor chip 10 and the substrate 70 can be performed simultaneously. And a semiconductor device can be manufactured by a method excellent in productivity. When the anisotropic conductive material 74 is thermosetting, the substrate 70 and the first semiconductor chip 10 can be bonded by being cured by heat after mounting the first semiconductor chip 10. it can.

  In the present embodiment, after the anisotropic conductive material 74 that is the first resin is provided on the substrate 70, the first semiconductor chip is mounted. However, the present invention is not limited to this, and the first resin may be provided between the two after the first semiconductor chip 10 is mounted on the substrate 70. Alternatively, the second semiconductor chip 20 may be mounted in advance on the first semiconductor chip 10 and both may be mounted on the substrate 70 at the same time. This is a matter common to all the embodiments.

  In the case where the first resin is provided in advance between the first semiconductor chip 10 and the substrate 70, the two may be bonded by pressing one of them to the other side. At this time, the first resin may be provided in advance so that the anisotropic conductive material 74 can protrude from the outer periphery of the first semiconductor chip 10 on the substrate 70. Even when the first resin is provided after the first semiconductor chip 10 is mounted, the first resin can be provided up to the outer periphery of the first semiconductor chip 10. Further, when the first semiconductor chip 10 has a similar shape to the substrate 70, it is preferable to mount the first semiconductor chip 10 in the center of the plane of the substrate 70.

  The second semiconductor chip 20 is mounted on the first semiconductor chip 10. More specifically, the surface of the second semiconductor chip 20 opposite to the surface on which the electrodes 22 are formed is mounted facing the first semiconductor chip 10. The second semiconductor chip 20 and the first semiconductor chip 10 may be bonded with an adhesive 76. According to the present embodiment, the first semiconductor chip 10 is larger than the second semiconductor chip 20. Therefore, when the second semiconductor chip 20 can be similar to the first semiconductor chip 10, the second semiconductor chip 20 is preferably mounted at the center of the first semiconductor chip 10. Alternatively, the adhesive 76 may be provided so as to protrude from the mounting surface of the first semiconductor chip 10 and reach the outer periphery of the second semiconductor chip 20 on the first semiconductor chip 10. By doing so, the second semiconductor chip 20 can be more strongly bonded onto the first semiconductor chip 10. Note that the adhesive 76 may be provided on at least one of the first semiconductor chip 10 and the second semiconductor chip 20 before mounting the second semiconductor chip 20.

  The electrode 22 of the second semiconductor chip 20 is wire bonded to the wiring pattern 72. For example, bonding can be performed using heat and ultrasonic waves. In the wire bonding, either the electrode 22 or the wiring pattern 72 may be performed first, but the step of forming bumps on the electrode 22 can be omitted by performing the bonding from the electrode 22.

  According to the present invention, the physical properties of the first resin provided between the first semiconductor chip 10 and the substrate 70 are different from those of the second resin 90 encapsulating the first and second semiconductor chips 10 and 20. . According to this, it is possible to select the first resin and the second resin 90 so as to have physical properties suitable for each of the member that adheres to the first resin and the member that adheres to the second resin 90. it can. Therefore, for example, it is possible to sufficiently cope with vibration due to ultrasonic waves when wire bonding the second semiconductor chip 20 by selecting the first resin. Therefore, wire bonding can be performed reliably and a semiconductor device with a high yield can be manufactured.

  The mounting portions of the first and second semiconductor chips 10 and 20 are sealed with a second resin 90. For example, a mold may be used for sealing. When a mold is used, the second resin 90 may be referred to as a mold resin. The second resin 90 can protect the first and second semiconductor chips 10 and 20 from the external environment.

  A plurality of external terminals 80 may be provided on the wiring pattern 72. When a plurality of through holes 82 are formed in the substrate 70, the external terminals 80 pass through the inside of the through holes 82. Specifically, the external terminal 80 is provided so as to pass through the through hole 82 from the portion exposed from the through hole 82 of the wiring pattern 72 and protrude from the substrate 70 toward the side opposite to the wiring pattern 82.

  In the present embodiment, the external terminal 80 is a solder ball. The solder balls are formed by a reflow process in which solder balls and flux or cream solder are provided and then heated to melt. Therefore, heating of the above-described anisotropic conductive material 74 (when thermosetting) is omitted, and in this reflow process, the anisotropic conductive material 74 may be heated simultaneously with the formation of the solder balls.

(Second Embodiment)
FIG. 2 shows a semiconductor device according to the second embodiment of the present invention. The semiconductor device 2 includes a first semiconductor chip 30, a second semiconductor chip 40, and a substrate 70.

  The first and second semiconductor chips 30 and 40 may be the same as the first and second semiconductor chips 10 and 20 described above, except that the outer dimensions of both are the same. As shown in FIG. 2, the anisotropic conductive material 74 is the mounting region of the first semiconductor chip 30 on the substrate 70 and the outer periphery thereof, and the side surfaces of the first semiconductor chip 30 and the second semiconductor chip 40. It may be provided up to the side.

  According to the present embodiment, in addition to the mounting region of the first semiconductor chip on the substrate, the first resin is provided on the outer periphery of the first semiconductor chip so as to protrude from the side surface. As a result, the bonding area between the first semiconductor chip and the first resin is increased, so that the first semiconductor chip is more reliably fixed on the substrate. Further, the first resin may be provided up to the side surface of the second semiconductor chip. In this case, even the second semiconductor chip can be fixed. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip. Therefore, even if the sizes of the first and second semiconductor chips are equal, wire bonding can be reliably performed, and a semiconductor device with a high yield can be manufactured.

  In the example shown in FIG. 2, the first resin such as the anisotropic conductive material 74 extends to the side surface of the upper second semiconductor chip 40. In many cases, the first semiconductor chip 30 is connected to the substrate 70 after the semiconductor chips 30 and 40 are connected. On the other hand, in order to provide the height of the first resin so as not to exceed the height of the lower first semiconductor chip 30, the lower first semiconductor chip 30 and the substrate 70 are connected first, and then The second semiconductor chip 40 may be mounted on the above.

(Third embodiment)
FIG. 3 is a diagram showing a semiconductor device according to the third embodiment of the present invention. The semiconductor device 3 includes a first semiconductor chip 50, a second semiconductor chip 60, and a substrate 70.

  The outer shape of the first semiconductor chip 50 is smaller than that of the second semiconductor chip 60. As shown in FIG. 3, the anisotropic conductive material 74 is provided on the substrate 70 in the mounting region of the first semiconductor chip 30 and its outer periphery so as to support the second semiconductor chip 60.

  According to the present embodiment, in addition to the mounting region of the first semiconductor chip on the substrate, the first resin is provided on the outer periphery of the first semiconductor chip so as to protrude from the side surface. As a result, the bonding area between the first semiconductor chip and the first resin is increased, so that the first semiconductor chip is more reliably fixed on the substrate. Further, the first resin may be provided up to a region on the substrate side of the second semiconductor chip and protruding from the first semiconductor chip. In this case, the second semiconductor chip is also fixed. Can do. Therefore, for example, it is possible to sufficiently cope with vibration caused by ultrasonic waves when wire bonding the second semiconductor chip. Therefore, even if the outer shape of the first semiconductor chip is smaller than that of the second semiconductor chip, wire bonding can be performed reliably, and a semiconductor device with a high yield can be obtained.

  In the present embodiment, when the first semiconductor chip 50 is thin (about 50 μm), the second semiconductor chip 60 can be supported by a small amount of the anisotropic conductive material 74. The second semiconductor chip 60 can be effectively fixed without unnecessarily widening the region of the material 74.

  The adhesive 76 may basically be anything as long as it has a function of bonding the semiconductor chips, but the upper second semiconductor chip 60 is larger than the lower first semiconductor chip 50. Therefore, a so-called solid adhesive in the form of a film is easier to manage in production than a paste-like adhesive.

  FIG. 4 shows a circuit board 100 on which the semiconductor device 1 according to the present embodiment is mounted. The circuit board 100 is generally an organic substrate such as a glass epoxy substrate. A wiring pattern made of, for example, copper or the like is formed on the circuit board 100 so as to form a desired circuit, and the wiring pattern and the external terminal 80 of the semiconductor device 1 are mechanically connected to electrically connect them. Ensuring continuity.

  As an electronic apparatus having the semiconductor device 1 to which the present invention is applied, FIG. 5 shows a notebook personal computer and FIG. 6 shows a mobile phone.

FIG. 1 is a diagram showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 shows a semiconductor device according to the second embodiment of the present invention. FIG. 3 is a diagram showing a semiconductor device according to the third embodiment of the present invention. FIG. 4 is a diagram showing a circuit board to which the present invention is applied. FIG. 5 is a diagram showing an electronic apparatus having a semiconductor device according to the present invention. FIG. 6 is a diagram showing an electronic apparatus having a semiconductor device according to the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... 1st semiconductor chip, 12 ... Electrode, 14 ... Bump, 20 ... 2nd semiconductor chip, 22 ... Electrode, 26 ... Wire, 70 ... Substrate, 72 ... Wiring pattern, 74 ... Anisotropic conductive material, 76 ... Adhesive, 80 ... External terminal, 82 ... Through hole, 90 ... Second resin

Claims (22)

A first semiconductor chip mounted on a substrate on which a wiring pattern is formed with a surface having a plurality of electrodes facing each other, and the electrodes are electrically connected to the wiring pattern;
Mounted on the first semiconductor chip, a surface having a plurality of electrodes faces away from the first semiconductor chip, and the plurality of electrodes are electrically connected to the wiring pattern by wires. A second semiconductor chip;
A first resin provided between the substrate and the first semiconductor chip;
A second resin different from the first resin on the substrate and encapsulating the first and second semiconductor chips;
A semiconductor device including: The semiconductor device according to claim 1,
The first resin is an anisotropic conductive material containing conductive particles,
The electrode of the first semiconductor chip is a semiconductor device electrically connected to the wiring pattern through the conductive particles. The semiconductor device according to claim 1 or 2,
A plurality of through holes are formed in the substrate, the wiring pattern is formed on one surface of the substrate and a part of the wiring pattern passes over the through hole,
A semiconductor device having a plurality of external terminals provided on the wiring pattern and projecting from the surface of the substrate opposite to the surface on the wiring pattern side through the through hole. The semiconductor device according to claim 1 or 2,
A semiconductor device having a plurality of land portions for providing a plurality of external terminals electrically connected to the wiring pattern. The semiconductor device according to claim 1 or 2,
The semiconductor device is a glass epoxy substrate. The semiconductor device according to claim 1 or 2,
The semiconductor device, wherein the second semiconductor chip is attached to the first semiconductor chip via an adhesive. The semiconductor device according to claim 1 or 2,
A semiconductor device in which an outer shape of the first semiconductor chip is larger than that of the second semiconductor chip. The semiconductor device according to claim 7.
The semiconductor device in which the first resin is provided to reach the side surface of the first semiconductor chip. The semiconductor device according to claim 1 or 2,
A semiconductor device in which the outer dimensions of the first and second semiconductor chips are equal. The semiconductor device according to claim 9.
The first resin is a semiconductor device provided up to at least a side surface of the first semiconductor chip among a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. The semiconductor device according to claim 1 or 2,
A semiconductor device in which an outer shape of the first semiconductor chip is smaller than that of the second semiconductor chip. The semiconductor device according to claim 11.
The first resin includes a side surface of the first semiconductor chip and a surface of the second semiconductor chip that faces the substrate and avoids facing the first semiconductor chip; A semiconductor device provided up to   A circuit board on which the semiconductor device according to claim 1 is mounted.   An electronic apparatus having the semiconductor device according to claim 1. Face-down bonding the first semiconductor chip to a substrate on which a wiring pattern is formed;
Mounting a second semiconductor chip on the first semiconductor chip;
Electrically connecting the second semiconductor chip and the wiring pattern with a wire;
Providing a first resin between the first semiconductor chip and the substrate;
Sealing the first and second semiconductor chips with a second resin different from the first resin;
A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 15,
The first resin is an anisotropic conductive material containing conductive particles,
A method of manufacturing a semiconductor device, wherein in the first step, the electrode of the first semiconductor chip is electrically connected to the wiring pattern via the conductive particles. In the manufacturing method of the semiconductor device according to claim 15,
Mounting the second semiconductor chip,
A method for manufacturing a semiconductor device, wherein the second semiconductor chip is attached to the first semiconductor chip via an adhesive. In the manufacturing method of the semiconductor device in any one of Claims 15-17,
The outer shape of the first semiconductor chip is larger than that of the second semiconductor chip,
At least after the step of mounting the first semiconductor chip and the step of providing the first resin,
Pressing at least one of the first semiconductor chip and the substrate toward the other;
A method of manufacturing a semiconductor device, wherein the first resin is provided so as to reach a side surface of the first semiconductor chip. In the manufacturing method of the semiconductor device in any one of Claims 15-17,
The outer dimensions of the first and second semiconductor chips are equal,
At least after the step of mounting the first semiconductor chip and the step of providing the first resin,
Pressing at least one of the first semiconductor chip and the substrate toward the other;
A method of manufacturing a semiconductor device, wherein the first resin is provided so as to reach at least a side surface of the first semiconductor chip among a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. In the manufacturing method of the semiconductor device in any one of Claims 15-17,
The outer shape of the first semiconductor chip is smaller than that of the second semiconductor chip,
At least after the step of mounting the first semiconductor chip and the step of providing the first resin,
Pressing at least one of the first semiconductor chip and the substrate toward the other;
The first resin is provided up to a side surface of the first semiconductor chip and a region of the second semiconductor chip that faces the substrate and protrudes from the first semiconductor chip. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device in any one of Claims 15-17,
The manufacturing method of the semiconductor device which bonds the said wire using an ultrasonic wave at the process of connecting with the said wire. In the manufacturing method of the semiconductor device according to claim 21,
A method of manufacturing a semiconductor device, wherein in the step of connecting with the wire, the electrode of the second semiconductor chip and the wire are bonded, and then the wire and the wiring pattern are bonded.

Images