JP3234062B2 - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof

Info

Publication number
JP3234062B2
JP3234062B2 JP21750393A JP21750393A JP3234062B2 JP 3234062 B2 JP3234062 B2 JP 3234062B2 JP 21750393 A JP21750393 A JP 21750393A JP 21750393 A JP21750393 A JP 21750393A JP 3234062 B2 JP3234062 B2 JP 3234062B2
Authority
JP
Japan
Prior art keywords
resin
mold
chip
semiconductor package
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP21750393A
Other languages
Japanese (ja)
Other versions
JPH0774194A (en
Inventor
秀夫 青木
博 岩崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21750393A priority Critical patent/JP3234062B2/en
Priority to EP94306204A priority patent/EP0644587B1/en
Priority to DE69431023T priority patent/DE69431023T2/en
Priority to KR1019940021753A priority patent/KR0172203B1/en
Publication of JPH0774194A publication Critical patent/JPH0774194A/en
Priority to US08/749,028 priority patent/US5866950A/en
Application granted granted Critical
Publication of JP3234062B2 publication Critical patent/JP3234062B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、半導体パッケージおよ
びその製造方法に係り、たとえば着脱・交換使用が可能
な外部記憶媒体などに適する薄形ないしコンパクトな半
導体パッケージおよびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a thin or compact semiconductor package suitable for an external storage medium which can be detached and replaced, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】各種データなどの記録・保存が可能な記
憶装置、ないしは記憶素子として、たとえばICカード
など各種のメモリカードが知られている。そして、この
種のカード類の構成においては、カードの大きさや厚さ
などに制約があるため、たとえばメモリ機能などに寄与
するIC素子の薄形実装が要求され、またパッケージ化
する場合も可及的な薄形,コンパクト化が望まれる。
2. Description of the Related Art Various types of memory cards such as IC cards are known as storage devices or storage elements capable of recording and storing various data. In the configuration of this kind of cards, the size and thickness of the card are limited, so that, for example, a thin mounting of an IC element contributing to a memory function or the like is required, and it is also possible to package the IC element. It is desired to achieve a compact and compact design.

【0003】このような薄形実装の要求、たとえば厚み
方向に対して 1mm以下のスペースに実装する必要性に対
しては、TAB(Tape Automated Bonding)法、フリッ
プチップ実装、COB(Chip on Board)法が知られてい
る。また、薄形パッケージの一例としては、たとえば図
6に要部構成を断面的に示すごとく、所要のICチップ
1などを一主面に搭載・実装する樹脂系回路基板2と、
スルホール3を介して樹脂系回路基板2の他主面側に導
出された外部接続用端子4と、前記ICチップ1などの
実装領域面を封止・被覆するモールド樹脂層5とを具備
した構成を採ったモジュールが知られている。なお、図
6において6はボンディングワイヤである。
In order to meet such requirements for thin mounting, for example, mounting in a space of 1 mm or less in the thickness direction, TAB (Tape Automated Bonding), flip chip mounting, COB (Chip on Board) The law is known. Further, as an example of a thin package, as shown in a sectional view of a main part in FIG. 6, for example, a resin-based circuit board 2 for mounting and mounting a required IC chip 1 and the like on one main surface;
A configuration including an external connection terminal 4 led out to the other main surface side of the resin circuit board 2 through the through hole 3 and a mold resin layer 5 for sealing and covering a mounting area surface of the IC chip 1 and the like. Modules are known. In FIG. 6, reference numeral 6 denotes a bonding wire.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、前記T
AB法の場合は、キャリアーテープの製造コストが比較
的高いことに加え、実装プロセスにおいてパッケージサ
イズに合わせて専用の金型や、ボンディングツールを必
要とするため、アッセンブリコストが相対的に高くな
り、実用的な手段として経済的に問題がある。
However, the above-mentioned T
In the case of the AB method, in addition to the relatively high manufacturing cost of the carrier tape, a special mold and a bonding tool are required according to the package size in the mounting process, so that the assembly cost is relatively high. There is an economic problem as a practical means.

【0005】一方、フリップチップ実装およびCOB法
の場合は、使用するICチップ1について予めバーンイ
ンテストを行い得ないので、信頼性上で問題がある。つ
まり、この種のICチップ1はチップ自体としては、近
い将来発現するであろ欠陥を検知するところの、いわゆ
るバーンインテストを行うことができないため、実装・
モジュール化後の実用初期段階でトラブルを起こす可能
性を秘めていることになり、信頼性の点で問題があると
いえる。この信頼性の問題に対しては、実装したICッ
プ1などの着脱・交換手段、すなわちリペアもしくはリ
ワークによって対応することも可能であるが、結果的に
アッセンブリコストのさらなる増大を招来することにな
る。特に、端子数が増大したICチップ1をCOB法で
実装する場合は、いずれにしてもアッセンブリに多くの
時間を要するので、コストアップを増長することにな
る。
On the other hand, in the case of the flip-chip mounting and the COB method, since a burn-in test cannot be performed on the IC chip 1 to be used in advance, there is a problem in reliability. In other words, this type of IC chip 1 cannot perform a so-called burn-in test for detecting a defect that will appear in the near future as a chip itself.
This has the potential to cause trouble at the early stage of practical use after modularization, and it can be said that there is a problem in terms of reliability. This reliability problem can be dealt with by mounting / dismounting / exchanging means such as the mounted IC chip 1, that is, repair or rework, but as a result, the assembly cost is further increased. Become. In particular, in the case where the IC chip 1 with the increased number of terminals is mounted by the COB method, in any case, a large amount of time is required for assembly, which increases the cost.

【0006】さらに、コンパクト化の点についてみる
と、TAB法およびCOB法の場合は、フリップチップ
実装の場合に較べて、広い実装面積を要するのでコンパ
クト化が阻害されるし、また前記片面側モールドによる
パッケージ化モジュールの場合は、一般的な(通常の)
トランスファーモールド工程において、ボンディングワ
イヤ6の流れ発生や接続部の離脱発生なども起こり易
く、信頼性および歩留まりの点で問題がある。また、ボ
ンディングワイヤの高さも現状では、 0.1mm以下に制御
することが困難で、薄型パッケージを形成する上で障害
になっている。
Further, in terms of compactness, the TAB method and the COB method require a larger mounting area than the flip-chip mounting method, which hinders compactness. For a packaged module by generic (regular)
In the transfer molding process, a flow of the bonding wire 6 and a detachment of the connection portion are apt to occur, which causes problems in reliability and yield. At present, it is difficult to control the height of the bonding wire to 0.1 mm or less, which is an obstacle to forming a thin package.

【0007】本発明は上記事情に対処してなされたもの
で、薄形・低コストで、かつ高い信頼性を保証し得る半
導体パッケージ、および前記半導体パッケージを低コス
ト・高歩留まりに製造し得る製造方法の提供を目的とす
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is a thin and low-cost semiconductor package capable of guaranteeing high reliability, and a manufacturing method capable of manufacturing the semiconductor package at low cost and high yield. The purpose is to provide a method.

【0008】[0008]

【課題を解決するための手段】 本発明に係る半導体パ
ッケージの製造方法は、配線回路を備えた樹脂系基板の
一主面に、少なくとも1個のICチップを含む電子部品
を樹脂系基板面の対応する接続用端子とフェースダウン
型に位置合わせ・配置する工程と、前記樹脂系基板面お
よび電子部品の対応・位置合わせした接続用端子同士を
フリップチップボンディングにより固定接続してモジュ
ールを組み立てる工程と、前記組み立てたモジュールを
真空・減圧化が可能な金型内に装着配置し、硬化型モー
ルド用樹脂を真空・減圧化した金型内に液状にて圧注入
して、モジュールの電子部品実装面側をモールドする工
程とを具備してなることを特徴とする。
According to a method of manufacturing a semiconductor package according to the present invention, an electronic component including at least one IC chip is provided on one main surface of a resin-based substrate having a wiring circuit. A step of aligning and arranging the corresponding connecting terminals and the face-down type, and a step of assembling a module by fixing and connecting the corresponding connecting terminals of the resin-based substrate surface and the electronic components by flip chip bonding. The assembled module is mounted and placed in a mold that can be evacuated and decompressed, and the hardening mold resin is injected in liquid form into the evacuated and depressurized mold, and the electronic component mounting surface of the module is mounted. Molding the side.

【0009】本発明は、樹脂系基板の一主面(片面)
に、ICチップを含む所要の電子部品を実装した構成
で、かつ前記実装電子部品を片面モールドによりモール
ド封止して、薄形・コンパクト・低コスト化を図り実現
したもので、要すれば樹脂系基板の他主面側(非モール
ド面側)に外部接続用端子を導出した構成とし、カード
化など簡略に形成し得るようにしたことを骨子とする。
According to the present invention, one principal surface (one side) of a resin substrate is provided.
In addition, the required electronic components including the IC chip are mounted, and the mounted electronic components are molded and sealed with a single-sided mold to achieve a thin, compact and low cost. The main point is that the external connection terminals are led out to the other main surface side (non-mold surface side) of the system substrate, and can be easily formed by carding.

【0010】なお、前記半導体パッケージの製造工程に
おいて、樹脂系基板面および電子部品の対応・位置合わ
せした接続用端子同士を固定接続してモジュールを組み
立てる際、樹脂系基板面の接続用端子をたとえば導電性
ペーストで形成しておき、対応する電子部品の接続用端
子を圧入・接続する構成など比較的簡便な手段を採って
もよい。
In the process of manufacturing the semiconductor package, when assembling a module by fixing and connecting the connection terminals corresponding to and aligned with the resin-based substrate surface and the electronic component, the connection terminals on the resin-based substrate surface may be, for example, A relatively simple means such as a structure in which a conductive paste is formed and a connection terminal of a corresponding electronic component is press-fitted and connected may be employed.

【0011】[0011]

【作用】本発明に係る半導体パッケージは、フリップチ
ップボンディングされたICチップを含む電子部品を硬
化型モールド用樹脂を用いた片面モールド化により、緻
密な封装に伴う保護・安定化などが図られるばかりでな
く、薄形化およびコンパクト化も容易に達成される。つ
まり、特性的に安定し、信頼性が高いので、たとえばカ
ード類構成に適する薄形でコンパクトな半導体パッケー
ジとしての機能を呈する。また、本発明に係る半導体モ
ジュールの製造方法によれば、片面モールドを真空・減
圧された金型内に、硬化型モールド用樹脂(たとえばエ
ポキシ樹脂)を金型内に液状で圧注入することによって
モールドを行って、先行して組み立てられたモジュール
の破損、たとえば端子接続部の剥離などを起こすことな
く、歩留まりよく信頼性の高い半導体パッケージを得る
ことが可能となる。
The semiconductor package according to the present invention has a flip chip.
Harden electronic components including chip-bonded IC chips.
The single-sided molding using the mold resin allows not only protection and stabilization associated with dense sealing, but also a reduction in thickness and size. That is, since the semiconductor device is stable in characteristics and has high reliability, the semiconductor device has a function as a thin and compact semiconductor package suitable for, for example, cards. Further, according to the method of manufacturing a semiconductor module according to the present invention, a resin for a hardening mold (for example, an epoxy resin) is injected in a liquid state into a mold in which a single-sided mold is vacuumed and decompressed. By performing the molding, it is possible to obtain a highly reliable semiconductor package with a high yield without breaking the previously assembled module, for example, without peeling off the terminal connection portion.

【0012】[0012]

【実施例】実施例1 以下図1〜図4を参照して本発明の実施例を説明する。Embodiment 1 An embodiment of the present invention will be described below with reference to FIGS.

【0013】図1は、本発明に係る半導体パッケージの
要部構成例を断面的に示したもので、7は一主面に電子
部品を搭載・実装する領域を備えた樹脂系回路基板、8
は前記樹脂系回路基板7の一主面に搭載・実装された所
要のICチップなどの電子部品、9は前記樹脂系回路基
板7のスルホール10を介して樹脂系回路基板7の他主面
側に導出された外部接続用端子、11は前記ICチップ8
などの実装領域面を封止・被覆するモールド樹脂層であ
る。そして、この構成例では、樹脂系回路基板7面の接
続端子(接続用パッド)7aは導電性ペーストで形成され
ており、搭載・実装されたICチップ8の対応する接続
用バンプ8aを圧入した後、導電性ペーストを硬化させて
固定接続した構成を採っている。
FIG. 1 is a sectional view showing an example of a configuration of a main part of a semiconductor package according to the present invention. Reference numeral 7 denotes a resin circuit board having a region for mounting and mounting electronic components on one principal surface;
Reference numeral 9 denotes an electronic component such as a required IC chip mounted and mounted on one main surface of the resin circuit board 7. Reference numeral 9 denotes another side of the resin circuit board 7 through the through hole 10 of the resin circuit board 7. The external connection terminal led out to the IC chip 8
This is a mold resin layer that seals and covers the surface of the mounting area, such as. In this configuration example, the connection terminals (connection pads) 7a on the surface of the resin-based circuit board 7 are formed of conductive paste, and the corresponding connection bumps 8a of the mounted and mounted IC chip 8 are press-fitted. Thereafter, the conductive paste is cured and fixedly connected.

【0014】次に、上記構成の半導体パッケージの製造
例を説明する。
Next, an example of manufacturing the semiconductor package having the above configuration will be described.

【0015】先ず、片面に(一主面に)フリップチップ
実装用の接続端子部を含む配線を有し、かつ前記接続端
子部の外周側に設けられたスルホール10を介して裏面
(他主面)に外部接続用端子9を導出した構成の樹脂系
回路基板7を用意する。この樹脂系回路基板7は、たと
えば長さ20mm,幅10mm,厚さ 0.2mmで、長さ15mm,幅 5
mm,厚さ0.25mmのICチップ8を搭載・実装するもので
ある。
First, a wiring including a connection terminal portion for flip-chip mounting is provided on one surface (one main surface), and a back surface (another main surface) is provided through a through hole 10 provided on the outer peripheral side of the connection terminal portion. 2), a resin circuit board 7 having a configuration in which the external connection terminals 9 are led out is prepared. This resin-based circuit board 7 has a length of 20 mm, a width of 10 mm, a thickness of 0.2 mm, a length of 15 mm, a width of 5 mm, for example.
The IC chip 8 having a thickness of 0.25 mm and a thickness of 0.25 mm is mounted and mounted.

【0016】次に、前記樹脂系回路基板7を、たとえば
真空吸着機構付きのスクリーン印刷機のステージ上に固
定し、前記ICチップ8の電極端子に対応する接続用パ
ッド7aを形成する。すなわち、搭載・実装するICチッ
プ8の電極端子(たとえば,100× 100μm)に対応する
開口(たとえば, 150× 150μm)を有する厚さ 100μm
のメタルマスクを用いて、樹脂系回路基板7の一主面に
銀ペースト(たとえば銀の粒径 1μm ,粘度1000ps)を
スクリーン印刷し、接続端子部面上に直径 150μm ,高
さ約80μm の接続用パッド7aを形成する。一方、電極端
子面上に電気メッキにより接続用の金バンプ(たとえ
ば,高さ30μm , 100× 100μm)8aを形成したICチッ
プ8を用意する。
Next, the resin-based circuit board 7 is fixed on, for example, a stage of a screen printer having a vacuum suction mechanism, and connection pads 7a corresponding to the electrode terminals of the IC chip 8 are formed. That is, a thickness of 100 μm having an opening (for example, 150 × 150 μm) corresponding to an electrode terminal (for example, 100 × 100 μm) of the IC chip 8 to be mounted / mounted.
Using a metal mask, a silver paste (for example, silver particle diameter 1 μm, viscosity 1000 ps) is screen-printed on one main surface of the resin circuit board 7, and a connection having a diameter of 150 μm and a height of about 80 μm is formed on the connection terminal surface. Pads 7a are formed. On the other hand, an IC chip 8 is prepared in which gold bumps (for example, height 30 μm, 100 × 100 μm) 8 a for connection are formed on the electrode terminal surfaces by electroplating.

【0017】前記樹脂系基板7の一主面に、前記ICチ
ップ8を互いに対応する接続用パッド7aおよび接続用の
金バンプ8aを位置合わせ・配置し、前記樹脂系基板7面
および電子部品8の対応・位置合わせした接続用端子7
a,8a同士を加圧することにより、接続用パッド7aに接
続用バンプ8aの少なくとも先端部を埋め込む形に圧入し
て固定接続し、モジュールを組み立てる。この工程にお
いては、前記接続用端子7a,8a同士の接合部以外の領域
で、絶縁性接着剤により樹脂系基板7面とICチップ8
下面とを接着して、前記接続固定の補強を行ってもよ
い。この状態で、前記接続用パッド7aを成す銀ペースト
を熱硬化させることによって、いわゆるフリップチップ
ボンディングが完了し、図2に断面的に示すごとく、樹
脂系基板7による固定・保持ともに、電気的な接続が達
成され、所望の半導体モジュールが組み立てられる。
A connection pad 7a and a connection gold bump 8a corresponding to the IC chip 8 are aligned and arranged on one main surface of the resin-based substrate 7, and the surface of the resin-based substrate 7 and the electronic component 8 Corresponding and aligned connection terminals 7
The modules a and 8a are press-fitted to each other and press-fitted into the connection pad 7a so as to embed at least the tip of the connection bump 8a, and fixedly connected to assemble the module. In this step, the surface of the resin-based substrate 7 and the IC chip 8 are coated with an insulating adhesive in a region other than the joint between the connection terminals 7a and 8a.
The connection and fixing may be reinforced by bonding to the lower surface. In this state, the so-called flip-chip bonding is completed by thermally curing the silver paste forming the connection pads 7a. As shown in cross-section in FIG. The connection is achieved and the desired semiconductor module is assembled.

【0018】次いで、前記組み立てたモジュールを真空
・減圧化が可能な、射出成型用の金型内に装着配置し、
モールド用樹脂を金型内に圧注入して、モジュールの電
子部品実装面側をモールドする。図3はこの工程の実施
態様を模式的に示したもので、加熱装置付きの金型(上
型) 12aおよび加熱装置付きの金型(下型) 12bから成
る金型12、加圧機構13、前記金型12内を真空・減圧化す
る真空ポンプ14、前記金型12内にモールド用樹脂を供給
する樹脂供給機構15、前記金型12内の真空・減圧化と常
圧化とを切り替えるバルブ16とを具備して成る射出成型
用の金型装置内に、前記組み立てたモジュールを装着配
置する。一方、前記真空ポンプ14を動作させて、射出成
型用の金型装置内を真空・減圧化させた後、前記樹脂供
給機構15内の低粘度エポキシ樹脂を、組み立てたモジュ
ールが装着配置された射出成型用の金型装置内に供給・
充填する。その後、前記金型 12a, 12bの加熱装置を動
作させ、金型12をモールド用樹脂の硬化温度に加熱・保
持して、前記モールド樹脂を硬化させることにより、前
記図1に図示した構成の半導体パッケージを得ることが
できる。
Next, the assembled module is mounted and arranged in a mold for injection molding, which can be evacuated and decompressed,
The molding resin is injected into the mold under pressure to mold the electronic component mounting surface side of the module. FIG. 3 schematically shows an embodiment of this step. The mold 12 includes a mold (upper mold) 12a with a heating device, a mold (lower mold) 12b with a heating device, and a pressurizing mechanism 13. A vacuum pump 14 for evacuating and depressurizing the inside of the mold 12, a resin supply mechanism 15 for supplying a molding resin into the mold 12, and switching between vacuum / decompression and normal pressure inside the mold 12. The assembled module is mounted and arranged in a mold apparatus for injection molding including the valve 16. On the other hand, the vacuum pump 14 is operated to evacuate and depressurize the inside of the mold apparatus for injection molding, and then the low-viscosity epoxy resin in the resin supply mechanism 15 is injected into the module where the assembled module is mounted. Supply into mold equipment for molding
Fill. Thereafter, the heating device for the molds 12a and 12b is operated, and the mold 12 is heated and held at the curing temperature of the molding resin to cure the molding resin, whereby the semiconductor having the configuration shown in FIG. You can get the package.

【0019】前記構成された半導体パッケージは、総厚
0.53μm であり、このことはたとえば総厚を同一とした
とき、COB法による半導体モジュールを用いる場合に
比較して、ボンディングワイヤの高さ分だけ、搭載・実
装するICチップ8や樹脂系基板7の厚さを厚く設定し
得ることになるので、より製造し易くまた量産性の点で
すぐれているといえる。逆に実装するICチップ8や樹
脂系基板7の厚さが同一であれば、総厚を薄くできると
いう利点がある。
The semiconductor package thus configured has a total thickness.
This means that, for example, when the total thickness is the same, the IC chip 8 and the resin-based substrate 7 to be mounted and mounted by the height of the bonding wire as compared with the case where the semiconductor module by the COB method is used. Can be set thicker, which means that it is easier to manufacture and superior in mass productivity. Conversely, if the thickness of the IC chip 8 and the resin-based substrate 7 to be mounted are the same, there is an advantage that the total thickness can be reduced.

【0020】この実施例における射出成型の場合は、モ
ールドに用いた樹脂が比較的低粘度あるいは液状のエポ
キシ樹脂で、かつ金型内が真空・減圧されているため、
流動性も向上し、モジュールの微細領域などへの樹脂浸
透(進入)もスムースに進行し、緻密な充填・モールド
が可能であるとともに、対応する接続用パッド7aおよび
接続用バンプ8a間の脱離やICチップ8の損傷などの恐
れも全面的に解消される。このような現象は、従来の一
般的な片面モールド封止においてしばしば遭遇する問題
に対して、大幅な改良ないし利点をもたらすことにな
る。つまり、従来のモールド手段では、モジュールの微
細領域などへの樹脂浸透(進入)を行うためには、モー
ルド用樹脂を高圧注入する必要があり、樹脂系基板7自
体の損傷や接続用パッド7aの損傷、さらにはICチップ
8の接続用バンプ8aなどの損傷が起こり易くて、歩留ま
りよく半導体パッケージを得難かったことに較べて、実
用上多くの利点をもたらすものといえる。
In the case of injection molding in this embodiment, the resin used for the mold is a relatively low-viscosity or liquid epoxy resin and the inside of the mold is evacuated and decompressed.
Fluidity is also improved, and resin penetration (entry) into the micro-areas of the module progresses smoothly, enabling dense filling and molding, and detachment between the corresponding connection pads 7a and connection bumps 8a. Also, the fear of damage to the IC chip 8 or the like is completely eliminated. Such a phenomenon provides a significant improvement or advantage over the problems often encountered in conventional general single-sided mold encapsulation. In other words, in the conventional molding means, it is necessary to inject the molding resin at a high pressure in order to infiltrate (enter) the resin into the fine area of the module, etc., so that the resin-based substrate 7 itself may be damaged or the connection pads 7a may be damaged. Damage, and furthermore, damage to the connection bumps 8a of the IC chip 8 and the like are liable to occur, so that it can be said that this brings many practical advantages as compared with the difficulty in obtaining a semiconductor package with high yield.

【0021】さらに比較例として、COB法による図6
の構成に置いては、厚さ 0.2mmの樹脂系基板,厚さ0.25
mmのICチップを搭載・配置し、ワイヤボンディングで
接続し(ワイヤボンディング部の高さ0.15mm)、モール
ド樹脂層の最薄部が0.05mmとなり、総厚が0.65mmとなっ
て、前記したように薄形化が疎外されている。
As a comparative example, FIG.
In the above configuration, a resin-based board with a thickness of 0.2 mm and a thickness of 0.25
The IC chip of mm is mounted and arranged and connected by wire bonding (height of the wire bonding part is 0.15 mm), the thinnest part of the mold resin layer is 0.05 mm, and the total thickness is 0.65 mm, as described above. Thinning has been alienated.

【0022】なお、上記構成例においては、外部接続用
端子9を樹脂系基板7の裏面側に導出したが、たとえば
図4に要部構成を断面的に示すごとく、トランスファモ
ールド側に導出した構成としてもよい。
In the above configuration example, the external connection terminals 9 are led out to the back side of the resin-based substrate 7, but, for example, as shown in FIG. It may be.

【0023】実施例2 実施例1の場合のICチップ8において、いわゆる選択
的なメッキもしくは蒸着(ソルダーマスクを用いて)に
より、半田(たとえば63Sn−37Pb)を電極端子部面
( 100× 100μm )に高さ 100μm の接続用パッド8aを
形成したものを用い、フリッブチップボンダーにより、
前記樹脂系基板7の一主面にICチップ8を位置決め・
仮固定した後、リフロー炉内を通過させて、前記半田溶
融温度(183℃)以上に加熱してフリッブチップボンディ
ングを行い、半導体モジュールを組み立てた。
Embodiment 2 In the IC chip 8 in the embodiment 1, solder (for example, 63Sn-37Pb) is applied to the electrode terminal surface (100 × 100 μm) by so-called selective plating or vapor deposition (using a solder mask). Using a 100μm-high connection pad 8a formed by a flip chip bonder,
Position IC chip 8 on one main surface of resin-based substrate 7
After being temporarily fixed, the semiconductor module was passed through a reflow furnace and heated to a temperature equal to or higher than the solder melting temperature (183 ° C.) to perform flip chip bonding, thereby assembling a semiconductor module.

【0024】次いで、前記実施例1の場合と同様の射出
成型用の金型装置を用い、同様の条件でモールドを行っ
て、半導体パッケージを製造した。この半導体パッケー
ジは、実施例1の場合と同じく、薄形・コンパクトで特
性的な信頼性も高く、かつ歩留まりも良好であった。
Next, a semiconductor package was manufactured by performing molding under the same conditions using the same mold apparatus for injection molding as in the case of the first embodiment. As in the case of the first embodiment, this semiconductor package was thin and compact, had high characteristic reliability, and had a good yield.

【0025】なお、本発明は上記例示の構成に限定され
るものでなく、発明の趣旨の範囲で種々の変形を採り得
る。たとえば搭載・実装するICチップは、図5に要部
構成を断面的に示すごとく、複数個であってもよい。
It should be noted that the present invention is not limited to the configuration described above, and various modifications can be made within the spirit of the invention. For example, a plurality of IC chips to be mounted and mounted may be provided as shown in FIG.

【0026】[0026]

【発明の効果】上記説明から分かるように、本発明に係
る半導体パッケージは、薄形化・コンパクト化し易く、
かつ特性ないし機能面の信頼性も高いので、たとえばカ
ード用の機能部品として好適するものといえる。特に、
前記薄形化が可能なことは、一方では樹脂系基板の厚さ
や,搭載・実装するICチップなどの厚さの選択・設定
範囲を拡大し得ることになり、用途に対応した特性ない
し機能の調整を可能とするので、用途の拡大にも寄与す
るといえる。
As can be seen from the above description, the semiconductor package according to the present invention can be easily made thin and compact.
In addition, since the reliability of characteristics and functions is high, it can be said that it is suitable as a functional component for a card, for example. In particular,
The ability to reduce the thickness allows the selection and setting range of the thickness of the resin-based substrate and the thickness of the IC chip to be mounted and mounted to be expanded. Since the adjustment is possible, it can be said that it also contributes to the expansion of applications.

【0027】また、本発明に係る半導体パッケージの製
造方法によれば、上記したようにすぐれた機能を備えた
半導体パッケージを歩留まりよく、かつ量産的に製造し
得るので、低コスト化などの点と相俟って実用上多くの
利点をもたらすものといえる。 なお、COB法および
フリップチップ実装は、前記指摘したように、バーンイ
ンテストの実施が不可能なため、信頼性の保証が困難で
あった。これに対して本発明に係る半導体パッケージ
は、射出成型モールド後、バーンインテストを実施し得
るので、いわゆるリペア技術を用いることなく、信頼性
の高い実装回路装置の構成が可能となる。つまり、本発
明に係る半導体パッケージを搭載・実装することにより
高い信頼性の保証が可能となり、結果的に歩留まり向上
および製造コストの低減など図り得る。
Further, according to the method of manufacturing a semiconductor package according to the present invention, a semiconductor package having excellent functions as described above can be manufactured in good yield and in mass production. It can be said that they bring many advantages in practical use. In the COB method and the flip chip mounting, as described above, since it is impossible to perform a burn-in test, it is difficult to guarantee the reliability. On the other hand, in the semiconductor package according to the present invention, a burn-in test can be performed after injection molding, so that a highly reliable mounting circuit device can be configured without using a so-called repair technique. That is, by mounting and mounting the semiconductor package according to the present invention, high reliability can be guaranteed, and as a result, yield can be improved and manufacturing cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る半導体パッケージの要部構成例を
示す断面図。
FIG. 1 is a sectional view showing an example of a configuration of a main part of a semiconductor package according to the present invention.

【図2】本発明に係る半導体パッケージを構成する半導
体モジュールの要部構成例を示す断面図。
FIG. 2 is a cross-sectional view showing a configuration example of a main part of a semiconductor module constituting a semiconductor package according to the present invention.

【図3】本発明に係る半導体パッケージの製造工程にお
ける樹脂モールドの実施態様の概略を模式的に示す断面
図。
FIG. 3 is a cross-sectional view schematically showing an outline of an embodiment of a resin mold in a semiconductor package manufacturing process according to the present invention.

【図4】本発明に係る半導体パッケージの他の要部構成
例を示す断面図。
FIG. 4 is a cross-sectional view showing another configuration example of the main part of the semiconductor package according to the present invention.

【図5】本発明に係る半導体パッケージを構成する他の
半導体モジュールの要部構成例を示す断面図。
FIG. 5 is a cross-sectional view showing an example of a configuration of a main part of another semiconductor module constituting the semiconductor package according to the present invention.

【図6】従来の半導体パッケージの要部構成を示す断面
図。
FIG. 6 is a cross-sectional view showing a main part configuration of a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

1,8…ICチップ 2,7…樹脂系基板 3,10
…スルホール 4,9…外部接続用端子 5…モー
ルド樹脂層 6…ボンディングワイヤ 7a…接続用
パッド 8a…接続用パンブ 11…モールド樹脂層
12…モールド用金型 12a…加熱装置付き金型(上
型) 12b…加熱装置付き金型(下型) 13…加圧
機構 14…真空ポンプ 15…モールド用樹脂供給機
構 16…切り替えバルブ
1,8 ... IC chip 2,7 ... Resin substrate 3,10
... Through holes 4, 9 ... Terminals for external connection 5 ... Mold resin layer 6 ... Bonding wires 7a ... Pads for connection 8a ... Pumps for connection 11 ... Mold resin layer
12 Mold for mold 12a Mold for heating device (upper mold) 12b Mold for heating device (lower mold) 13 Pressure mechanism 14 Vacuum pump 15 Resin supply mechanism for molding 16 Switching valve

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/56 H01L 21/60 311 H01L 23/28 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/56 H01L 21/60 311 H01L 23/28

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】配線回路を備えた樹脂系基板の一主面に、
少なくとも1個のICチップを含む電子部品を樹脂系基
板面の対応する接続用端子とフェースダウン型に位置合
わせ・配置する工程と、 前記樹脂系基板面および電子部品の対応・位置合わせし
た接続用端子同士をフリップチップボンディングにより
固定接続してモジュールを組み立てる工程と、前記組み
立てたモジュールを真空・減圧化が可能な金型内に装着
配置し、硬化型モールド用樹脂を真空・減圧化した金型
内に液状にて圧注入して、モジュールの電子部品実装面
側をモールドする工程とを具備してなることを特徴とす
る半導体パッケージの製造方法。
1. A resin-based substrate provided with a wiring circuit on one principal surface,
A step of aligning and arranging an electronic component including at least one IC chip in a face-down manner with a corresponding connection terminal on the resin-based substrate surface, and a connection for matching and aligning the resin-based substrate surface and the electronic component. A step of assembling a module by fixing and connecting the terminals to each other by flip chip bonding, and mounting and disposing the assembled module in a mold that can be evacuated and decompressed, and a mold in which the hardening mold resin is evacuated and decompressed. And injecting a liquid into the module, and molding the electronic component mounting surface side of the module.
JP21750393A 1993-09-01 1993-09-01 Semiconductor package and manufacturing method thereof Expired - Lifetime JP3234062B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP21750393A JP3234062B2 (en) 1993-09-01 1993-09-01 Semiconductor package and manufacturing method thereof
EP94306204A EP0644587B1 (en) 1993-09-01 1994-08-23 Semiconductor package and fabrication method
DE69431023T DE69431023T2 (en) 1993-09-01 1994-08-23 Semiconductor structure and manufacturing method
KR1019940021753A KR0172203B1 (en) 1993-09-01 1994-08-31 Semiconductor package and its manufacturing method
US08/749,028 US5866950A (en) 1993-09-01 1996-11-14 Semiconductor package and fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21750393A JP3234062B2 (en) 1993-09-01 1993-09-01 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH0774194A JPH0774194A (en) 1995-03-17
JP3234062B2 true JP3234062B2 (en) 2001-12-04

Family

ID=16705260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21750393A Expired - Lifetime JP3234062B2 (en) 1993-09-01 1993-09-01 Semiconductor package and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3234062B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11996505B2 (en) * 2018-12-10 2024-05-28 Ams Sensors Singapore Pte. Ltd. Vacuum injection molding for optoelectronic modules

Also Published As

Publication number Publication date
JPH0774194A (en) 1995-03-17

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